diff options
| author | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2015-02-10 11:35:36 -0800 |
|---|---|---|
| committer | Dmitry Torokhov <dmitry.torokhov@gmail.com> | 2015-02-10 11:35:36 -0800 |
| commit | 4ba24fef3eb3b142197135223b90ced2f319cd53 (patch) | |
| tree | a20c125b27740ec7b4c761b11d801108e1b316b2 /arch/arm/boot/dts | |
| parent | 47c1ffb2b6b630894e9a16442611c056ab21c057 (diff) | |
| parent | 98a4a59ee31a12105a2b84f5b8b515ac2cb208ef (diff) | |
Merge branch 'next' into for-linus
Prepare first round of input updates for 3.20.
Diffstat (limited to 'arch/arm/boot/dts')
445 files changed, 37042 insertions, 6188 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index b8c5cd3ddeb9..91bd5bd62857 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -48,11 +48,23 @@ dtb-$(CONFIG_ARCH_AT91) += sama5d33ek.dtb dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb dtb-$(CONFIG_ARCH_AT91) += sama5d36ek.dtb +# sama5d4 +dtb-$(CONFIG_ARCH_AT91) += at91-sama5d4ek.dtb dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb -dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb +dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b-plus.dtb +dtb-$(CONFIG_ARCH_BCM_5301X) += \ + bcm4708-buffalo-wzr-1750dhp.dtb \ + bcm4708-netgear-r6250.dtb \ + bcm4708-netgear-r6300-v2.dtb \ + bcm47081-asus-rt-n18u.dtb \ + bcm47081-buffalo-wzr-600dhp2.dtb +dtb-$(CONFIG_ARCH_BCM_63XX) += bcm963138dvt.dtb +dtb-$(CONFIG_ARCH_BCM_CYGNUS) += bcm911360_entphn.dtb \ + bcm911360k.dtb \ + bcm958300k.dtb dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \ bcm21664-garnet.dtb dtb-$(CONFIG_ARCH_BERLIN) += \ @@ -64,7 +76,9 @@ dtb-$(CONFIG_ARCH_BRCMSTB) += \ dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \ da850-evm.dtb dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb -dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ +dtb-$(CONFIG_ARCH_EXYNOS) += exynos3250-monk.dtb \ + exynos3250-rinato.dtb \ + exynos4210-origen.dtb \ exynos4210-smdkv310.dtb \ exynos4210-trats.dtb \ exynos4210-universal_c210.dtb \ @@ -78,6 +92,7 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ exynos5250-arndale.dtb \ exynos5250-smdk5250.dtb \ exynos5250-snow.dtb \ + exynos5250-spring.dtb \ exynos5260-xyref5260.dtb \ exynos5410-smdk5410.dtb \ exynos5420-arndale-octa.dtb \ @@ -90,6 +105,7 @@ dtb-$(CONFIG_ARCH_HI3xxx) += hi3620-hi4511.dtb dtb-$(CONFIG_ARCH_HIX5HD2) += hisi-x5hd2-dkb.dtb dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \ ecx-2000.dtb +dtb-$(CONFIG_ARCH_HIP04) += hip04-d01.dtb dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \ integratorcp.dtb dtb-$(CONFIG_ARCH_KEYSTONE) += k2hk-evm.dtb \ @@ -100,6 +116,7 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \ kirkwood-d2net.dtb \ kirkwood-db-88f6281.dtb \ kirkwood-db-88f6282.dtb \ + kirkwood-dir665.dtb \ kirkwood-dns320.dtb \ kirkwood-dns325.dtb \ kirkwood-dockstar.dtb \ @@ -144,8 +161,8 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \ kirkwood-openrd-client.dtb \ kirkwood-openrd-ultimate.dtb \ kirkwood-rd88f6192.dtb \ - kirkwood-rd88f6281-a0.dtb \ - kirkwood-rd88f6281-a1.dtb \ + kirkwood-rd88f6281-z0.dtb \ + kirkwood-rd88f6281-a.dtb \ kirkwood-rs212.dtb \ kirkwood-rs409.dtb \ kirkwood-rs411.dtb \ @@ -159,8 +176,14 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \ kirkwood-ts419-6282.dtb dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb +dtb-$(CONFIG_MACH_MESON6) += meson6-atv1200.dtb +dtb-$(CONFIG_ARCH_MMP) += pxa168-aspenite.dtb \ + pxa910-dkb.dtb \ + mmp2-brownstone.dtb dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb dtb-$(CONFIG_ARCH_MXC) += \ + imx1-ads.dtb \ + imx1-apf9328.dtb \ imx25-eukrea-mbimxsd25-baseboard.dtb \ imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dtb \ imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dtb \ @@ -199,6 +222,7 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx6dl-gw52xx.dtb \ imx6dl-gw53xx.dtb \ imx6dl-gw54xx.dtb \ + imx6dl-gw552x.dtb \ imx6dl-hummingboard.dtb \ imx6dl-nitrogen6x.dtb \ imx6dl-phytec-pbab01.dtb \ @@ -223,6 +247,8 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx6q-gw53xx.dtb \ imx6q-gw5400-a.dtb \ imx6q-gw54xx.dtb \ + imx6q-gw552x.dtb \ + imx6q-hummingboard.dtb \ imx6q-nitrogen6x.dtb \ imx6q-phytec-pbab01.dtb \ imx6q-rex-pro.dtb \ @@ -230,6 +256,7 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx6q-sabrelite.dtb \ imx6q-sabresd.dtb \ imx6q-sbc6x.dtb \ + imx6q-tbs2910.dtb \ imx6q-udoo.dtb \ imx6q-wandboard.dtb \ imx6q-wandboard-revb1.dtb \ @@ -240,7 +267,10 @@ dtb-$(CONFIG_ARCH_MXC) += \ imx6q-tx6q-1110.dtb \ imx6sl-evk.dtb \ imx6sx-sdb.dtb \ - vf610-colibri.dtb \ + ls1021a-qds.dtb \ + ls1021a-twr.dtb \ + vf500-colibri-eval-v3.dtb \ + vf610-colibri-eval-v3.dtb \ vf610-cosmic.dtb \ vf610-twr.dtb dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ @@ -264,7 +294,8 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ imx28-m28evk.dtb \ imx28-sps1.dtb \ imx28-tx28.dtb -dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb +dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb \ + ste-nomadik-nhk15.dtb dtb-$(CONFIG_ARCH_NSPIRE) += nspire-cx.dtb \ nspire-tp.dtb \ nspire-clp.dtb @@ -286,9 +317,15 @@ dtb-$(CONFIG_ARCH_OMAP3) += am3517-craneboard.dtb \ omap3-devkit8000.dtb \ omap3-evm.dtb \ omap3-evm-37xx.dtb \ - omap3-gta04.dtb \ + omap3-gta04a3.dtb \ + omap3-gta04a4.dtb \ + omap3-gta04a5.dtb \ + omap3-ha.dtb \ + omap3-ha-lcd.dtb \ omap3-igep0020.dtb \ + omap3-igep0020-rev-f.dtb \ omap3-igep0030.dtb \ + omap3-igep0030-rev-g.dtb \ omap3-ldp.dtb \ omap3-lilly-dbb056.dtb \ omap3-n900.dtb \ @@ -309,6 +346,7 @@ dtb-$(CONFIG_ARCH_OMAP3) += am3517-craneboard.dtb \ omap3-sbc-t3517.dtb \ omap3-sbc-t3530.dtb \ omap3-sbc-t3730.dtb \ + omap3-thunder.dtb \ omap3-zoom3.dtb dtb-$(CONFIG_SOC_AM33XX) += am335x-base0033.dtb \ am335x-bone.dtb \ @@ -316,7 +354,8 @@ dtb-$(CONFIG_SOC_AM33XX) += am335x-base0033.dtb \ am335x-evm.dtb \ am335x-evmsk.dtb \ am335x-nano.dtb \ - am335x-pepper.dtb + am335x-pepper.dtb \ + am335x-lxm.dtb dtb-$(CONFIG_ARCH_OMAP4) += omap4-duovero-parlor.dtb \ omap4-panda.dtb \ omap4-panda-a4.dtb \ @@ -332,6 +371,7 @@ dtb-$(CONFIG_SOC_OMAP5) += omap5-cm-t54.dtb \ omap5-sbc-t54.dtb \ omap5-uevm.dtb dtb-$(CONFIG_SOC_DRA7XX) += dra7-evm.dtb \ + am57xx-beagle-x15.dtb \ dra72-evm.dtb dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-d2-network.dtb \ orion5x-lacie-ethernet-disk-mini-v2.dtb \ @@ -339,13 +379,19 @@ dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-d2-network.dtb \ orion5x-rd88f5182-nas.dtb dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb dtb-$(CONFIG_ARCH_QCOM) += \ + qcom-apq8064-cm-qs600.dtb \ qcom-apq8064-ifc6410.dtb \ qcom-apq8074-dragonboard.dtb \ + qcom-apq8084-ifc6540.dtb \ qcom-apq8084-mtp.dtb \ + qcom-ipq8064-ap148.dtb \ qcom-msm8660-surf.dtb \ - qcom-msm8960-cdp.dtb + qcom-msm8960-cdp.dtb \ + qcom-msm8974-sony-xperia-honami.dtb +dtb-$(CONFIG_ARCH_REALVIEW) += arm-realview-pb1176.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3066a-bqcurie2.dtb \ + rk3066a-marsboard.dtb \ rk3188-radxarock.dtb \ rk3288-evb-act8846.dtb \ rk3288-evb-rk808.dtb @@ -357,26 +403,27 @@ dtb-$(CONFIG_ARCH_S5PV210) += s5pv210-aquila.dtb \ s5pv210-smdkc110.dtb \ s5pv210-smdkv210.dtb \ s5pv210-torbreck.dtb -dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += r7s72100-genmai.dtb \ +dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += \ + r8a73a4-ape6evm.dtb \ + r8a73a4-ape6evm-reference.dtb \ r8a7740-armadillo800eva.dtb \ r8a7778-bockw.dtb \ r8a7778-bockw-reference.dtb \ - r8a7740-armadillo800eva-reference.dtb \ r8a7779-marzen.dtb \ - r8a7791-koelsch.dtb \ r8a7790-lager.dtb \ + sh7372-mackerel.dtb \ sh73a0-kzm9g.dtb \ - sh73a0-kzm9g-reference.dtb \ - r8a73a4-ape6evm.dtb \ - r8a73a4-ape6evm-reference.dtb \ - sh7372-mackerel.dtb + sh73a0-kzm9g-reference.dtb dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \ r7s72100-genmai.dtb \ + r8a7740-armadillo800eva.dtb \ + r8a7779-marzen.dtb \ + r8a7790-lager.dtb \ r8a7791-henninger.dtb \ r8a7791-koelsch.dtb \ - r8a7790-lager.dtb \ - r8a7779-marzen.dtb + r8a7794-alt.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \ + socfpga_arria10_socdk.dtb \ socfpga_cyclone5_socdk.dtb \ socfpga_cyclone5_sockit.dtb \ socfpga_cyclone5_socrates.dtb \ @@ -389,6 +436,7 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \ spear320-hmi.dtb dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb dtb-$(CONFIG_ARCH_STI)+= stih407-b2120.dtb \ + stih410-b2120.dtb \ stih415-b2000.dtb \ stih415-b2020.dtb \ stih416-b2000.dtb \ @@ -406,6 +454,7 @@ dtb-$(CONFIG_MACH_SUN4I) += \ dtb-$(CONFIG_MACH_SUN5I) += \ sun5i-a10s-olinuxino-micro.dtb \ sun5i-a10s-r7-tv-dongle.dtb \ + sun5i-a13-hsg-h702.dtb \ sun5i-a13-olinuxino.dtb \ sun5i-a13-olinuxino-micro.dtb dtb-$(CONFIG_MACH_SUN6I) += \ @@ -414,13 +463,20 @@ dtb-$(CONFIG_MACH_SUN6I) += \ sun6i-a31-hummingbird.dtb \ sun6i-a31-m9.dtb dtb-$(CONFIG_MACH_SUN7I) += \ + sun7i-a20-bananapi.dtb \ sun7i-a20-cubieboard2.dtb \ sun7i-a20-cubietruck.dtb \ + sun7i-a20-hummingbird.dtb \ sun7i-a20-i12-tvbox.dtb \ + sun7i-a20-m3.dtb \ + sun7i-a20-olinuxino-lime.dtb \ + sun7i-a20-olinuxino-lime2.dtb \ sun7i-a20-olinuxino-micro.dtb \ sun7i-a20-pcduino3.dtb dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-a23-ippo-q8h-v5.dtb +dtb-$(CONFIG_MACH_SUN9I) += \ + sun9i-a80-optimus.dtb dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ tegra20-iris-512.dtb \ tegra20-medcom-wide.dtb \ @@ -440,6 +496,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ tegra114-roth.dtb \ tegra114-tn7.dtb \ tegra124-jetson-tk1.dtb \ + tegra124-nyan-big.dtb \ tegra124-venice2.dtb dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \ @@ -465,13 +522,15 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \ zynq-parallella.dtb \ zynq-zc702.dtb \ zynq-zc706.dtb \ - zynq-zed.dtb + zynq-zed.dtb \ + zynq-zybo.dtb dtb-$(CONFIG_MACH_ARMADA_370) += \ armada-370-db.dtb \ armada-370-mirabox.dtb \ armada-370-netgear-rn102.dtb \ armada-370-netgear-rn104.dtb \ - armada-370-rd.dtb + armada-370-rd.dtb \ + armada-370-synology-ds213j.dtb dtb-$(CONFIG_MACH_ARMADA_375) += \ armada-375-db.dtb dtb-$(CONFIG_MACH_ARMADA_38X) += \ @@ -484,23 +543,20 @@ dtb-$(CONFIG_MACH_ARMADA_XP) += \ armada-xp-lenovo-ix4-300d.dtb \ armada-xp-matrix.dtb \ armada-xp-netgear-rn2120.dtb \ - armada-xp-openblocks-ax3-4.dtb + armada-xp-openblocks-ax3-4.dtb \ + armada-xp-synology-ds414.dtb dtb-$(CONFIG_MACH_DOVE) += dove-cm-a510.dtb \ dove-cubox.dtb \ dove-cubox-es.dtb \ dove-d2plug.dtb \ dove-d3plug.dtb \ dove-dove-db.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt6589-aquaris5.dtb \ + mt6592-evb.dtb \ + mt8127-moose.dtb \ + mt8135-evbp1.dtb -targets += dtbs dtbs_install -targets += $(dtb-y) endif -# *.dtb used to be generated in the directory above. Clean out the -# old build results so people don't accidentally use them. -dtbs: $(addprefix $(obj)/, $(dtb-y)) - $(Q)rm -f $(obj)/../*.dtb - -clean-files := *.dtb - -dtbs_install: $(addsuffix _dtbinst_, $(dtb-y)) +always := $(dtb-y) +clean-files := *.dtb diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi index bde1777b62be..6cc25ed912ee 100644 --- a/arch/arm/boot/dts/am335x-bone-common.dtsi +++ b/arch/arm/boot/dts/am335x-bone-common.dtsi @@ -7,9 +7,6 @@ */ / { - model = "TI AM335x BeagleBone"; - compatible = "ti,am335x-bone", "ti,am33xx"; - cpus { cpu@0 { cpu0-supply = <&dcdc2_reg>; @@ -227,6 +224,7 @@ &tps { regulators { dcdc1_reg: regulator@0 { + regulator-name = "vdds_dpr"; regulator-always-on; }; @@ -249,18 +247,22 @@ }; ldo1_reg: regulator@3 { + regulator-name = "vio,vrtc,vdds"; regulator-always-on; }; ldo2_reg: regulator@4 { + regulator-name = "vdd_3v3aux"; regulator-always-on; }; ldo3_reg: regulator@5 { + regulator-name = "vdd_1v8"; regulator-always-on; }; ldo4_reg: regulator@6 { + regulator-name = "vdd_3v3a"; regulator-always-on; }; }; diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts index 94ee427a6db1..83d40f7655e5 100644 --- a/arch/arm/boot/dts/am335x-bone.dts +++ b/arch/arm/boot/dts/am335x-bone.dts @@ -10,6 +10,11 @@ #include "am33xx.dtsi" #include "am335x-bone-common.dtsi" +/ { + model = "TI AM335x BeagleBone"; + compatible = "ti,am335x-bone", "ti,am33xx"; +}; + &ldo3_reg { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts index 305975d3f531..5c42d259fa68 100644 --- a/arch/arm/boot/dts/am335x-boneblack.dts +++ b/arch/arm/boot/dts/am335x-boneblack.dts @@ -10,6 +10,11 @@ #include "am33xx.dtsi" #include "am335x-bone-common.dtsi" +/ { + model = "TI AM335x BeagleBone Black"; + compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx"; +}; + &ldo3_reg { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -75,3 +80,7 @@ status = "okay"; }; }; + +&rtc { + system-power-controller; +}; diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts index e2156a583de7..66342515df20 100644 --- a/arch/arm/boot/dts/am335x-evm.dts +++ b/arch/arm/boot/dts/am335x-evm.dts @@ -307,6 +307,13 @@ 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ >; }; + + dcan1_pins_default: dcan1_pins_default { + pinctrl-single,pins = < + 0x168 (PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */ + 0x16c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart0_rtsn.d_can1_rx */ + >; + }; }; &uart0 { @@ -437,9 +444,9 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&nandflash_pins_s0>; - ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ + ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ nand@0,0 { - reg = <0 0 0>; /* CS0, offset 0 */ + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ ti,nand-ecc-opt = "bch8"; ti,elm-id = <&elm>; nand-bus-width = <8>; @@ -489,7 +496,7 @@ reg = <0x00060000 0x00020000>; }; partition@4 { - label = "NAND.u-boot-spl"; + label = "NAND.u-boot-spl-os"; reg = <0x00080000 0x00040000>; }; partition@5 { @@ -641,6 +648,7 @@ ti,x-plate-resistance = <200>; ti,coordinate-readouts = <5>; ti,wire-config = <0x00 0x11 0x22 0x33>; + ti,charge-delay = <0x400>; }; adc { @@ -664,3 +672,9 @@ &aes { status = "okay"; }; + +&dcan1 { + status = "disabled"; /* Enable only if Profile 1 is selected */ + pinctrl-names = "default"; + pinctrl-0 = <&dcan1_pins_default>; +}; diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi index a1a0cc5eb35c..c0e1135256cc 100644 --- a/arch/arm/boot/dts/am335x-igep0033.dtsi +++ b/arch/arm/boot/dts/am335x-igep0033.dtsi @@ -126,10 +126,10 @@ pinctrl-names = "default"; pinctrl-0 = <&nandflash_pins>; - ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ + ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ nand@0,0 { - reg = <0 0 0>; /* CS0, offset 0 */ + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ nand-bus-width = <8>; ti,nand-ecc-opt = "bch8"; gpmc,device-width = <1>; diff --git a/arch/arm/boot/dts/am335x-lxm.dts b/arch/arm/boot/dts/am335x-lxm.dts new file mode 100644 index 000000000000..7266a00aab2e --- /dev/null +++ b/arch/arm/boot/dts/am335x-lxm.dts @@ -0,0 +1,362 @@ +/* + * Copyright (C) 2014 NovaTech LLC - http://www.novatechweb.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "am33xx.dtsi" + +/ { + model = "NovaTech OrionLXm"; + compatible = "novatech,am335x-lxm", "ti,am33xx"; + + cpus { + cpu@0 { + cpu0-supply = <&vdd1_reg>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; + + /* Power supply provides a fixed 5V @2A */ + vbat: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vbat"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; + + /* Power supply provides a fixed 3.3V @3A */ + vmmcsd_fixed: fixedregulator@1 { + compatible = "regulator-fixed"; + regulator-name = "vmmcsd_fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; +}; + +&am33xx_pinmux { + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + 0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3 */ + 0xf4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2 */ + 0xf8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1 */ + 0xfc (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0 */ + 0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk */ + 0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd */ + >; + }; + + i2c0_pins: pinmux_i2c0_pins { + pinctrl-single,pins = < + 0x188 (PIN_INPUT | MUX_MODE0) /* i2c0_sda.i2c0_sda */ + 0x18c (PIN_INPUT | MUX_MODE0) /* i2c0_scl.i2c0_scl */ + >; + }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_int */ + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_crs_dv */ + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_rxer */ + 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* rmii1_txen */ + 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* rmii1_td1 */ + 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* rmii1_td0 */ + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_rd1 */ + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_rd0 */ + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk */ + + /* Slave 2 */ + 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_txen */ + 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_td1 */ + 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_td0 */ + 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rd1 */ + 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rd0 */ + 0x70 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_crs_dv */ + 0x74 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rxer */ + 0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_int */ + 0x108 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii2_refclk */ + >; + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 reset value */ + 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_int */ + 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_crs_dv */ + 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_rxer */ + 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_txen */ + 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_td1 */ + 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_td0 */ + 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_rd1 */ + 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_rd0 */ + 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_refclk */ + + /* Slave 2 reset value*/ + 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_txen */ + 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_td1 */ + 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_td0 */ + 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_rd1 */ + 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_rd0 */ + 0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_crs_dv */ + 0x74 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_rxer */ + 0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_int */ + 0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_refclk */ + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ + 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + /* MDIO reset value */ + 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) + 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) + >; + }; + + emmc_pins: pinmux_emmc_pins { + pinctrl-single,pins = < + 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */ + 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */ + 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */ + 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */ + 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */ + 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */ + 0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */ + 0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */ + 0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */ + 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */ + >; + }; + + uart0_pins: pinmux_uart0_pins { + pinctrl-single,pins = < + 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ + 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ + >; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + + status = "okay"; + clock-frequency = <400000>; + + serial_config1: serial_config1@20 { + compatible = "nxp,pca9539"; + reg = <0x20>; + }; + + serial_config2: serial_config2@21 { + compatible = "nxp,pca9539"; + reg = <0x21>; + }; + + tps: tps@2d { + compatible = "ti,tps65910"; + reg = <0x2d>; + }; +}; + +/include/ "tps65910.dtsi" + +&tps { + vcc1-supply = <&vbat>; + vcc2-supply = <&vbat>; + vcc3-supply = <&vbat>; + vcc4-supply = <&vbat>; + vcc5-supply = <&vbat>; + vcc6-supply = <&vbat>; + vcc7-supply = <&vbat>; + vccio-supply = <&vbat>; + + regulators { + /* vrtc - unused */ + + vio_reg: regulator@1 { + regulator-name = "vio_1v5,ddr"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd1_reg: regulator@2 { + regulator-name = "vdd1,mpu"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + vdd2_reg: regulator@3 { + regulator-name = "vdd2_1v1,core"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + /* vdd3 - unused */ + + /* vdig1 - unused */ + + vdig2_reg: regulator@6 { + regulator-name = "vdig2_1v8,vdds_pll"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + /* vpll - unused */ + + vdac_reg: regulator@8 { + regulator-name = "vdac_1v8,vdds"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vaux1_reg: regulator@9 { + regulator-name = "vaux1_1v8,usb"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vaux2_reg: regulator@10 { + regulator-name = "vaux2_3v3,io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vaux33_reg: regulator@11 { + regulator-name = "vaux33_3v3,usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vmmc_reg: regulator@12 { + regulator-name = "vmmc_3v3,io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; +}; + +&sham { + status = "okay"; +}; + +&aes { + status = "okay"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&usb_ctrl_mod { + status = "okay"; +}; + +&usb0_phy { + status = "okay"; +}; + +&usb1_phy { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; + +&usb1 { + status = "okay"; + dr_mode = "host"; +}; + +&cppi41dma { + status = "okay"; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <5>; + phy-mode = "rmii"; + dual_emac_res_vlan = <2>; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <4>; + phy-mode = "rmii"; + dual_emac_res_vlan = <3>; +}; + +&mac { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + dual_emac = <1>; + status = "okay"; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <4>; + status = "okay"; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&emmc_pins>; + vmmc-supply = <&vmmcsd_fixed>; + bus-width = <8>; + ti,non-removable; + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi index 3a0a161342ba..acd37057bca9 100644 --- a/arch/arm/boot/dts/am33xx.dtsi +++ b/arch/arm/boot/dts/am33xx.dtsi @@ -83,6 +83,11 @@ }; }; + am33xx_control_module: control_module@4a002000 { + compatible = "syscon"; + reg = <0x44e10000 0x7fc>; + }; + am33xx_pinmux: pinmux@44e10800 { compatible = "pinctrl-single"; reg = <0x44e10800 0x0238>; @@ -132,11 +137,15 @@ }; }; + cm: syscon@44e10000 { + compatible = "ti,am33xx-controlmodule", "syscon"; + reg = <0x44e10000 0x800>; + }; + intc: interrupt-controller@48200000 { - compatible = "ti,omap2-intc"; + compatible = "ti,am33xx-intc"; interrupt-controller; #interrupt-cells = <1>; - ti,intc-size = <128>; reg = <0x48200000 0x1000>; }; @@ -200,6 +209,8 @@ reg = <0x44e09000 0x2000>; interrupts = <72>; status = "disabled"; + dmas = <&edma 26>, <&edma 27>; + dma-names = "tx", "rx"; }; uart1: serial@48022000 { @@ -209,6 +220,8 @@ reg = <0x48022000 0x2000>; interrupts = <73>; status = "disabled"; + dmas = <&edma 28>, <&edma 29>; + dma-names = "tx", "rx"; }; uart2: serial@48024000 { @@ -218,6 +231,8 @@ reg = <0x48024000 0x2000>; interrupts = <74>; status = "disabled"; + dmas = <&edma 30>, <&edma 31>; + dma-names = "tx", "rx"; }; uart3: serial@481a6000 { @@ -329,20 +344,24 @@ interrupts = <91>; }; - dcan0: d_can@481cc000 { - compatible = "bosch,d_can"; + dcan0: can@481cc000 { + compatible = "ti,am3352-d_can"; ti,hwmods = "d_can0"; - reg = <0x481cc000 0x2000 - 0x44e10644 0x4>; + reg = <0x481cc000 0x2000>; + clocks = <&dcan0_fck>; + clock-names = "fck"; + syscon-raminit = <&am33xx_control_module 0x644 0>; interrupts = <52>; status = "disabled"; }; - dcan1: d_can@481d0000 { - compatible = "bosch,d_can"; + dcan1: can@481d0000 { + compatible = "ti,am3352-d_can"; ti,hwmods = "d_can1"; - reg = <0x481d0000 0x2000 - 0x44e10644 0x4>; + reg = <0x481d0000 0x2000>; + clocks = <&dcan1_fck>; + clock-names = "fck"; + syscon-raminit = <&am33xx_control_module 0x644 1>; interrupts = <55>; status = "disabled"; }; @@ -352,8 +371,13 @@ reg = <0x480C8000 0x200>; interrupts = <77>; ti,hwmods = "mailbox"; + #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <8>; + mbox_wkupm3: wkup_m3 { + ti,mbox-tx = <0 0 0>; + ti,mbox-rx = <0 0 3>; + }; }; timer1: timer@44e31000 { @@ -411,7 +435,7 @@ }; rtc: rtc@44e3e000 { - compatible = "ti,da830-rtc"; + compatible = "ti,am3352-rtc", "ti,da830-rtc"; reg = <0x44e3e000 0x1000>; interrupts = <75 76>; @@ -696,6 +720,7 @@ */ interrupts = <40 41 42 43>; ranges; + syscon = <&cm>; status = "disabled"; davinci_mdio: mdio@4a101000 { @@ -726,9 +751,8 @@ }; ocmcram: ocmcram@40300000 { - compatible = "ti,am3352-ocmcram"; - reg = <0x40300000 0x10000>; - ti,hwmods = "ocmcram"; + compatible = "mmio-sram"; + reg = <0x40300000 0x10000>; /* 64k */ }; wkup_m3: wkup_m3@44d00000 { diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi index 8689949bdba3..b62a1cd776cd 100644 --- a/arch/arm/boot/dts/am4372.dtsi +++ b/arch/arm/boot/dts/am4372.dtsi @@ -57,11 +57,18 @@ cache-level = <2>; }; + am43xx_control_module: control_module@4a002000 { + compatible = "syscon"; + reg = <0x44e10000 0x7f4>; + }; + am43xx_pinmux: pinmux@44e10800 { - compatible = "pinctrl-single"; + compatible = "ti,am437-padconf", "pinctrl-single"; reg = <0x44e10800 0x31c>; #address-cells = <1>; #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0xffffffff>; }; @@ -166,8 +173,13 @@ reg = <0x480C8000 0x200>; interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "mailbox"; + #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <8>; + mbox_wkupm3: wkup_m3 { + ti,mbox-tx = <0 0 0>; + ti,mbox-rx = <0 0 3>; + }; }; timer1: timer@44e31000 { @@ -661,6 +673,26 @@ }; }; + tscadc: tscadc@44e0d000 { + compatible = "ti,am3359-tscadc"; + reg = <0x44e0d000 0x1000>; + ti,hwmods = "adc_tsc"; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&adc_tsc_fck>; + clock-names = "fck"; + status = "disabled"; + + tsc { + compatible = "ti,am3359-tsc"; + }; + + adc { + #io-channel-cells = <1>; + compatible = "ti,am3359-adc"; + }; + + }; + sham: sham@53100000 { compatible = "ti,omap5-sham"; ti,hwmods = "sham"; @@ -811,6 +843,8 @@ maximum-speed = "high-speed"; dr_mode = "otg"; status = "disabled"; + snps,dis_u3_susphy_quirk; + snps,dis_u2_susphy_quirk; }; }; @@ -833,6 +867,8 @@ maximum-speed = "high-speed"; dr_mode = "otg"; status = "disabled"; + snps,dis_u3_susphy_quirk; + snps,dis_u2_susphy_quirk; }; }; @@ -885,6 +921,33 @@ clock-names = "fck"; }; }; + + ocmcram: ocmcram@40300000 { + compatible = "mmio-sram"; + reg = <0x40300000 0x40000>; /* 256k */ + }; + + dcan0: can@481cc000 { + compatible = "ti,am4372-d_can", "ti,am3352-d_can"; + ti,hwmods = "d_can0"; + clocks = <&dcan0_fck>; + clock-names = "fck"; + reg = <0x481cc000 0x2000>; + syscon-raminit = <&am43xx_control_module 0x644 0>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + dcan1: can@481d0000 { + compatible = "ti,am4372-d_can", "ti,am3352-d_can"; + ti,hwmods = "d_can1"; + clocks = <&dcan1_fck>; + clock-names = "fck"; + reg = <0x481d0000 0x2000>; + syscon-raminit = <&am43xx_control_module 0x644 1>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts index e7ac47fa6615..7eaae4cf9f89 100644 --- a/arch/arm/boot/dts/am437x-gp-evm.dts +++ b/arch/arm/boot/dts/am437x-gp-evm.dts @@ -254,6 +254,20 @@ 0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7) >; }; + + dcan0_default: dcan0_default_pins { + pinctrl-single,pins = < + 0x178 (PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */ + 0x17c (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */ + >; + }; + + dcan1_default: dcan1_default_pins { + pinctrl-single,pins = < + 0x180 (PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */ + 0x184 (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */ + >; + }; }; &i2c0 { @@ -291,8 +305,8 @@ dcdc3: regulator-dcdc3 { compatible = "ti,tps65218-dcdc3"; regulator-name = "vdcdc3"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; @@ -343,6 +357,14 @@ status = "okay"; }; +&tscadc { + status = "okay"; + + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; + &ecap0 { status = "okay"; pinctrl-names = "default"; @@ -511,3 +533,15 @@ }; }; }; + +&dcan0 { + pinctrl-names = "default"; + pinctrl-0 = <&dcan0_default>; + status = "okay"; +}; + +&dcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&dcan1_default>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts index 859ff3d620ee..53bbfc90b26a 100644 --- a/arch/arm/boot/dts/am437x-sk-evm.dts +++ b/arch/arm/boot/dts/am437x-sk-evm.dts @@ -100,7 +100,7 @@ }; lcd0: display { - compatible = "osddisplays,osd057T0559-34ts", "panel-dpi"; + compatible = "newhaven,nhd-4.3-480272ef-atxl", "panel-dpi"; label = "lcd"; pinctrl-names = "default"; @@ -112,11 +112,11 @@ clock-frequency = <9000000>; hactive = <480>; vactive = <272>; - hfront-porch = <8>; - hback-porch = <43>; - hsync-len = <4>; - vback-porch = <12>; - vfront-porch = <4>; + hfront-porch = <2>; + hback-porch = <2>; + hsync-len = <41>; + vfront-porch = <2>; + vback-porch = <2>; vsync-len = <10>; hsync-active = <0>; vsync-active = <0>; @@ -320,8 +320,7 @@ lcd_pins: lcd_pins { pinctrl-single,pins = < - /* GPIO 5_8 to select LCD / HDMI */ - 0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7) + 0x1c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpcm_ad7.gpio1_7 */ >; }; }; @@ -363,8 +362,8 @@ dcdc3: regulator-dcdc3 { compatible = "ti,tps65218-dcdc3"; regulator-name = "vdds_ddr"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts index ac3e4859935f..662261d6b2ca 100644 --- a/arch/arm/boot/dts/am43x-epos-evm.dts +++ b/arch/arm/boot/dts/am43x-epos-evm.dts @@ -358,8 +358,8 @@ dcdc3: regulator-dcdc3 { compatible = "ti,tps65218-dcdc3"; regulator-name = "vdcdc3"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; regulator-boot-on; regulator-always-on; }; @@ -438,9 +438,9 @@ status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */ pinctrl-names = "default"; pinctrl-0 = <&nand_flash_x8>; - ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */ + ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ nand@0,0 { - reg = <0 0 0>; /* CS0, offset 0 */ + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ ti,nand-ecc-opt = "bch16"; ti,elm-id = <&elm>; nand-bus-width = <8>; @@ -519,6 +519,14 @@ status = "okay"; }; +&tscadc { + status = "okay"; + + adc { + ti,adc-channels = <0 1 2 3 4 5 6 7>; + }; +}; + &ecap0 { status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts new file mode 100644 index 000000000000..49edbda68cd5 --- /dev/null +++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts @@ -0,0 +1,405 @@ +/* + * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "dra74x.dtsi" +#include <dt-bindings/clk/ti-dra7-atl.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + model = "TI AM5728 BeagleBoard-X15"; + compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7"; + + aliases { + rtc0 = &mcp_rtc; + rtc1 = &tps659038_rtc; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + vdd_3v3: fixedregulator-vdd_3v3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3"; + vin-supply = <®en1>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + vtt_fixed: fixedregulator-vtt { + /* TPS51200 */ + compatible = "regulator-fixed"; + regulator-name = "vtt_fixed"; + vin-supply = <&smps3_reg>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&leds_pins_default>; + + led@0 { + label = "beagle-x15:usr0"; + gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + led@1 { + label = "beagle-x15:usr1"; + gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + + led@2 { + label = "beagle-x15:usr2"; + gpios = <&gpio7 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + led@3 { + label = "beagle-x15:usr3"; + gpios = <&gpio7 15 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "ide-disk"; + default-state = "off"; + }; + }; +}; + +&dra7_pmx_core { + leds_pins_default: leds_pins_default { + pinctrl-single,pins = < + 0x3a8 (PIN_OUTPUT | MUX_MODE14) /* spi1_d1.gpio7_8 */ + 0x3ac (PIN_OUTPUT | MUX_MODE14) /* spi1_d0.gpio7_9 */ + 0x3c0 (PIN_OUTPUT | MUX_MODE14) /* spi2_sclk.gpio7_14 */ + 0x3c4 (PIN_OUTPUT | MUX_MODE14) /* spi2_d1.gpio7_15 */ + >; + }; + + i2c1_pins_default: i2c1_pins_default { + pinctrl-single,pins = < + 0x400 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.sda */ + 0x404 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.scl */ + >; + }; + + i2c3_pins_default: i2c3_pins_default { + pinctrl-single,pins = < + 0x2a4 (PIN_INPUT| MUX_MODE10) /* mcasp1_aclkx.i2c3_sda */ + 0x2a8 (PIN_INPUT| MUX_MODE10) /* mcasp1_fsx.i2c3_scl */ + >; + }; + + uart3_pins_default: uart3_pins_default { + pinctrl-single,pins = < + 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd.rxd */ + 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd.txd */ + >; + }; + + mmc1_pins_default: mmc1_pins_default { + pinctrl-single,pins = < + 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ + 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ + 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc2_pins_default: mmc2_pins_default { + pinctrl-single,pins = < + 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + tps659038_pins_default: tps659038_pins_default { + pinctrl-single,pins = < + 0x418 (PIN_INPUT_PULLUP | MUX_MODE14) /* wakeup0.gpio1_0 */ + >; + }; + + tmp102_pins_default: tmp102_pins_default { + pinctrl-single,pins = < + 0x3C8 (PIN_INPUT_PULLUP | MUX_MODE14) /* spi2_d0.gpio7_16 */ + >; + }; + + mcp79410_pins_default: mcp79410_pins_default { + pinctrl-single,pins = < + 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */ + >; + }; + + usb1_pins: pinmux_usb1_pins { + pinctrl-single,pins = < + 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ + >; + }; + +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_default>; + clock-frequency = <400000>; + + tps659038: tps659038@58 { + compatible = "ti,tps659038"; + reg = <0x58>; + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names = "default"; + pinctrl-0 = <&tps659038_pins_default>; + + #interrupt-cells = <2>; + interrupt-controller; + + ti,system-power-controller; + + tps659038_pmic { + compatible = "ti,tps659038-pmic"; + + regulators { + smps12_reg: smps12 { + /* VDD_MPU */ + regulator-name = "smps12"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps3_reg: smps3 { + /* VDD_DDR */ + regulator-name = "smps3"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + smps45_reg: smps45 { + /* VDD_DSPEVE, VDD_IVA, VDD_GPU */ + regulator-name = "smps45"; + regulator-min-microvolt = < 850000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + regulator-boot-on; + }; + + smps6_reg: smps6 { + /* VDD_CORE */ + regulator-name = "smps6"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1030000>; + regulator-always-on; + regulator-boot-on; + }; + + /* SMPS7 unused */ + + smps8_reg: smps8 { + /* VDD_1V8 */ + regulator-name = "smps8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + /* SMPS9 unused */ + + ldo1_reg: ldo1 { + /* VDD_SD */ + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + ldo2_reg: ldo2 { + /* VDD_SHV5 */ + regulator-name = "ldo2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo3_reg: ldo3 { + /* VDDA_1V8_PHY */ + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo9_reg: ldo9 { + /* VDD_RTC */ + regulator-name = "ldo9"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-always-on; + regulator-boot-on; + }; + + ldoln_reg: ldoln { + /* VDDA_1V8_PLL */ + regulator-name = "ldoln"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldousb_reg: ldousb { + /* VDDA_3V_USB: VDDA_USBHS33 */ + regulator-name = "ldousb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + regen1: regen1 { + /* VDD_3V3_ON */ + regulator-name = "regen1"; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + tps659038_rtc: tps659038_rtc { + compatible = "ti,palmas-rtc"; + interrupt-parent = <&tps659038>; + interrupts = <8 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + }; + + tps659038_pwr_button: tps659038_pwr_button { + compatible = "ti,palmas-pwrbutton"; + interrupt-parent = <&tps659038>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + ti,palmas-long-press-seconds = <12>; + }; + }; + + tmp102: tmp102@48 { + compatible = "ti,tmp102"; + reg = <0x48>; + pinctrl-names = "default"; + pinctrl-0 = <&tmp102_pins_default>; + interrupt-parent = <&gpio7>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins_default>; + clock-frequency = <400000>; + + mcp_rtc: rtc@6f { + compatible = "microchip,mcp7941x"; + reg = <0x6f>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_LOW>; /* IRQ_SYS_1N */ + + pinctrl-names = "default"; + pinctrl-0 = <&mcp79410_pins_default>; + + vcc-supply = <&vdd_3v3>; + wakeup-source; + }; +}; + +&gpio7 { + ti,no-reset-on-init; + ti,no-idle-on-init; +}; + +&cpu0 { + cpu0-supply = <&smps12_reg>; + voltage-tolerance = <1>; +}; + +&uart3 { + status = "okay"; + interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <&dra7_pmx_core 0x248>; + + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins_default>; +}; + +&mmc1 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_default>; + + vmmc-supply = <&ldo1_reg>; + vmmc_aux-supply = <&vdd_3v3>; + pbias-supply = <&pbias_mmc_reg>; + bus-width = <4>; + cd-gpios = <&gpio6 27 0>; /* gpio 219 */ +}; + +&mmc2 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins_default>; + + vmmc-supply = <&vdd_3v3>; + bus-width = <8>; + ti,non-removable; + cap-mmc-dual-data-rate; +}; + +&sata { + status = "okay"; +}; + +&usb2_phy1 { + phy-supply = <&ldousb_reg>; +}; + +&usb1 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins>; +}; diff --git a/arch/arm/boot/dts/arm-realview-pb1176.dts b/arch/arm/boot/dts/arm-realview-pb1176.dts new file mode 100644 index 000000000000..ff26c7ed8c41 --- /dev/null +++ b/arch/arm/boot/dts/arm-realview-pb1176.dts @@ -0,0 +1,412 @@ +/* + * Copyright 2014 Linaro Ltd + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +/dts-v1/; +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> +#include "skeleton.dtsi" + +/ { + model = "ARM RealView PB1176"; + compatible = "arm,realview-pb1176"; + + chosen { }; + + aliases { + serial0 = &pb1176_serial0; + serial1 = &pb1176_serial1; + serial2 = &pb1176_serial2; + serial3 = &pb1176_serial3; + serial4 = &fpga_serial; + }; + + memory { + /* 128 MiB memory @ 0x0 */ + reg = <0x00000000 0x08000000>; + }; + + /* The voltage to the MMC card is hardwired at 3.3V */ + vmmc: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + xtal24mhz: xtal24mhz@24M { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + timclk: timclk@1M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <24>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + mclk: mclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + kmiclk: kmiclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + sspclk: sspclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + uartclk: uartclk@24M { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clock-div = <1>; + clock-mult = <1>; + clocks = <&xtal24mhz>; + }; + + /* FIXME: this actually hangs off the PLL clocks */ + pclk: pclk@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "arm,realview-pb1176-soc", "simple-bus"; + regmap = <&syscon>; + ranges; + + syscon: syscon@10000000 { + compatible = "arm,realview-pb1176-syscon", "syscon"; + reg = <0x10000000 0x1000>; + + led@08.0 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x01>; + label = "versatile:0"; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + led@08.1 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x02>; + label = "versatile:1"; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + led@08.2 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x04>; + label = "versatile:2"; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + led@08.3 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x08>; + label = "versatile:3"; + default-state = "off"; + }; + led@08.4 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x10>; + label = "versatile:4"; + default-state = "off"; + }; + led@08.5 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x20>; + label = "versatile:5"; + default-state = "off"; + }; + led@08.6 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x40>; + label = "versatile:6"; + default-state = "off"; + }; + led@08.7 { + compatible = "register-bit-led"; + offset = <0x08>; + mask = <0x80>; + label = "versatile:7"; + default-state = "off"; + }; + }; + + /* Primary DevChip GIC synthesized with the CPU */ + intc_dc1176: interrupt-controller@10120000 { + compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0x10121000 0x1000>, + <0x10120000 0x100>; + }; + + L2: l2-cache { + compatible = "arm,l220-cache"; + reg = <0x10110000 0x1000>; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; + cache-unified; + cache-level = <2>; + /* + * Override default cache size, sets and + * associativity as these may be erroneously set + * up by boot loader(s). + */ + arm,override-auxreg; + cache-size = <131072>; // 128kB + cache-sets = <512>; + cache-line-size = <32>; + }; + + pmu { + compatible = "arm,arm1176-pmu"; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + timer01: timer@10104000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x10104000 0x1000>; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, <0 9 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&timclk>, <&timclk>, <&pclk>; + clock-names = "timer1", "timer2", "apb_pclk"; + }; + + timer23: timer@10105000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x10105000 0x1000>; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; + arm,sp804-has-irq = <1>; + clocks = <&timclk>, <&timclk>, <&pclk>; + clock-names = "timer1", "timer2", "apb_pclk"; + }; + + pb1176_rtc: rtc@10108000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x10108000 0x1000>; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + pb1176_gpio0: gpio@1010a000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x1010a000 0x1000>; + gpio-controller; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + pb1176_ssp: ssp@1010b000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x1010b000 0x1000>; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sspclk>, <&pclk>; + clock-names = "SSPCLK", "apb_pclk"; + }; + + pb1176_serial0: serial@1010c000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1010c000 0x1000>; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + pb1176_serial1: serial@1010d000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1010d000 0x1000>; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + pb1176_serial2: serial@1010e000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1010e000 0x1000>; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + pb1176_serial3: serial@1010f000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x1010f000 0x1000>; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + }; + + /* These peripherals are inside the FPGA rather than the DevChip */ + fpga { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + fpga_mci: mmcsd@10005000 { + compatible = "arm,pl18x", "arm,primecell"; + reg = <0x10005000 0x1000>; + interrupt-parent = <&intc_fpga1176>; + interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>, + <0 2 IRQ_TYPE_LEVEL_HIGH>; + /* Due to frequent FIFO overruns, use just 500 kHz */ + max-frequency = <500000>; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + clocks = <&mclk>, <&pclk>; + clock-names = "mclk", "apb_pclk"; + vmmc-supply = <&vmmc>; + cd-gpios = <&fpga_gpio1 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&fpga_gpio1 1 GPIO_ACTIVE_HIGH>; + }; + + fpga_kmi0: kmi@10006000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x10006000 0x1000>; + interrupt-parent = <&intc_fpga1176>; + interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&kmiclk>, <&pclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + fpga_kmi1: kmi@10007000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x10007000 0x1000>; + interrupt-parent = <&intc_fpga1176>; + interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&kmiclk>, <&pclk>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + fpga_charlcd: charlcd@10008000 { + compatible = "arm,versatile-lcd"; + reg = <0x10008000 0x1000>; + interrupt-parent = <&intc_fpga1176>; + interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + fpga_serial: serial@10009000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x10009000 0x1000>; + interrupt-parent = <&intc_fpga1176>; + interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&uartclk>, <&pclk>; + clock-names = "uartclk", "apb_pclk"; + }; + + /* This GIC on the board is cascaded off the DevChip GIC */ + intc_fpga1176: interrupt-controller@10040000 { + compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0x10041000 0x1000>, + <0x10040000 0x100>; + interrupt-parent = <&intc_dc1176>; + interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; + }; + + fpga_gpio0: gpio@10014000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x10014000 0x1000>; + gpio-controller; + interrupt-parent = <&intc_fpga1176>; + interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + fpga_gpio1: gpio@10015000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x10015000 0x1000>; + gpio-controller; + interrupt-parent = <&intc_fpga1176>; + interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + fpga_rtc: rtc@10017000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x10017000 0x1000>; + interrupt-parent = <&intc_fpga1176>; + interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pclk>; + clock-names = "apb_pclk"; + }; + + + }; +}; diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts index 416f4e5a69c1..70b1943a86b1 100644 --- a/arch/arm/boot/dts/armada-370-db.dts +++ b/arch/arm/boot/dts/armada-370-db.dts @@ -43,6 +43,8 @@ }; mdio { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; phy0: ethernet-phy@0 { reg = <0>; }; @@ -53,11 +55,15 @@ }; ethernet@70000 { + pinctrl-0 = <&ge0_rgmii_pins>; + pinctrl-names = "default"; status = "okay"; phy = <&phy0>; phy-mode = "rgmii-id"; }; ethernet@74000 { + pinctrl-0 = <&ge1_rgmii_pins>; + pinctrl-names = "default"; status = "okay"; phy = <&phy1>; phy-mode = "rgmii-id"; @@ -69,6 +75,7 @@ clock-frequency = <100000>; status = "okay"; audio_codec: audio-codec@4a { + #sound-dai-cells = <0>; compatible = "cirrus,cs42l51"; reg = <0x4a>; }; @@ -96,30 +103,6 @@ broken-cd; }; - pinctrl { - /* - * These pins might be muxed as I2S by - * the bootloader, but it conflicts - * with the real I2S pins that are - * muxed using i2s_pins. We must mux - * those pins to a function other than - * I2S. - */ - pinctrl-0 = <&hog_pins1 &hog_pins2>; - pinctrl-names = "default"; - - hog_pins1: hog-pins1 { - marvell,pins = "mpp6", "mpp8", "mpp10", - "mpp12", "mpp13"; - marvell,function = "gpio"; - }; - - hog_pins2: hog-pins2 { - marvell,pins = "mpp5", "mpp7", "mpp9"; - marvell,function = "gpo"; - }; - }; - usb@50000 { status = "okay"; }; @@ -129,6 +112,8 @@ }; spi0: spi@10600 { + pinctrl-0 = <&spi0_pins2>; + pinctrl-names = "default"; status = "okay"; spi-flash@0 { @@ -161,17 +146,60 @@ }; sound { - compatible = "marvell,a370db-audio"; - marvell,audio-controller = <&audio_controller>; - marvell,audio-codec = <&audio_codec &spdif_out &spdif_in>; - status = "okay"; + compatible = "simple-audio-card"; + simple-audio-card,name = "Armada 370 DB Audio"; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,widgets = + "Headphone", "Out Jack", + "Line", "In Jack"; + simple-audio-card,routing = + "Out Jack", "HPL", + "Out Jack", "HPR", + "AIN1L", "In Jack", + "AIN1L", "In Jack"; + status = "okay"; + + simple-audio-card,dai-link@0 { + format = "i2s"; + cpu { + sound-dai = <&audio_controller 0>; + }; + + codec { + sound-dai = <&audio_codec>; + }; + }; + + simple-audio-card,dai-link@1 { + format = "i2s"; + cpu { + sound-dai = <&audio_controller 1>; + }; + + codec { + sound-dai = <&spdif_out>; + }; + }; + + simple-audio-card,dai-link@2 { + format = "i2s"; + cpu { + sound-dai = <&audio_controller 1>; + }; + + codec { + sound-dai = <&spdif_in>; + }; + }; }; spdif_out: spdif-out { - compatible = "linux,spdif-dit"; + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; }; spdif_in: spdif-in { - compatible = "linux,spdif-dir"; + #sound-dai-cells = <0>; + compatible = "linux,spdif-dir"; }; }; diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts index 097df7d8f0f6..e1b0eb6b091f 100644 --- a/arch/arm/boot/dts/armada-370-mirabox.dts +++ b/arch/arm/boot/dts/armada-370-mirabox.dts @@ -54,18 +54,6 @@ status = "okay"; }; - pinctrl { - pwr_led_pin: pwr-led-pin { - marvell,pins = "mpp63"; - marvell,function = "gpo"; - }; - - stat_led_pins: stat-led-pins { - marvell,pins = "mpp64", "mpp65"; - marvell,function = "gpio"; - }; - }; - gpio_leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -91,6 +79,8 @@ }; mdio { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; phy0: ethernet-phy@0 { reg = <0>; }; @@ -100,11 +90,15 @@ }; }; ethernet@70000 { + pinctrl-0 = <&ge0_rgmii_pins>; + pinctrl-names = "default"; status = "okay"; phy = <&phy0>; phy-mode = "rgmii-id"; }; ethernet@74000 { + pinctrl-0 = <&ge1_rgmii_pins>; + pinctrl-names = "default"; status = "okay"; phy = <&phy1>; phy-mode = "rgmii-id"; @@ -163,3 +157,16 @@ }; }; }; + +&pinctrl { + pwr_led_pin: pwr-led-pin { + marvell,pins = "mpp63"; + marvell,function = "gpo"; + }; + + stat_led_pins: stat-led-pins { + marvell,pins = "mpp64", "mpp65"; + marvell,function = "gpio"; + }; +}; + diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts index d6d572e5af32..4e24932c6e30 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts @@ -35,7 +35,7 @@ pcie-controller { status = "okay"; - /* Connected to Marvell SATA controller */ + /* Connected to Marvell 88SE9170 SATA controller */ pcie@1,0 { /* Port 0, Lane 0 */ status = "okay"; @@ -53,60 +53,23 @@ status = "okay"; }; + /* eSATA interface */ sata@a0000 { - nr-ports = <2>; + nr-ports = <1>; status = "okay"; }; - pinctrl { - power_led_pin: power-led-pin { - marvell,pins = "mpp57"; - marvell,function = "gpio"; - }; - - sata1_led_pin: sata1-led-pin { - marvell,pins = "mpp15"; - marvell,function = "gpio"; - }; - - sata2_led_pin: sata2-led-pin { - marvell,pins = "mpp14"; - marvell,function = "gpio"; - }; - - backup_led_pin: backup-led-pin { - marvell,pins = "mpp56"; - marvell,function = "gpio"; - }; - - backup_button_pin: backup-button-pin { - marvell,pins = "mpp58"; - marvell,function = "gpio"; - }; - - power_button_pin: power-button-pin { - marvell,pins = "mpp62"; - marvell,function = "gpio"; - }; - - reset_button_pin: reset-button-pin { - marvell,pins = "mpp6"; - marvell,function = "gpio"; - }; - - poweroff: poweroff { - marvell,pins = "mpp8"; - marvell,function = "gpio"; - }; - }; - mdio { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; phy0: ethernet-phy@0 { /* Marvell 88E1318 */ reg = <0>; }; }; ethernet@74000 { + pinctrl-0 = <&ge1_rgmii_pins>; + pinctrl-names = "default"; status = "okay"; phy = <&phy0>; phy-mode = "rgmii-id"; @@ -122,7 +85,7 @@ status = "okay"; isl12057: isl12057@68 { - compatible = "isl,isl12057"; + compatible = "isil,isl12057"; reg = <0x68>; }; @@ -143,6 +106,10 @@ marvell,nand-enable-arbiter; nand-on-flash-bbt; + /* Use Hardware BCH ECC */ + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + partition@0 { label = "u-boot"; reg = <0x0000000 0x180000>; /* 1.5MB */ @@ -196,20 +163,20 @@ default-state = "keep"; }; - green-sata1-led { - label = "rn102:green:sata1"; + blue-sata1-led { + label = "rn102:blue:sata1"; gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; default-state = "on"; }; - green-sata2-led { - label = "rn102:green:sata2"; + blue-sata2-led { + label = "rn102:blue:sata2"; gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; default-state = "on"; }; - green-backup-led { - label = "rn102:green:backup"; + blue-backup-led { + label = "rn102:blue:backup"; gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; default-state = "on"; }; @@ -248,3 +215,45 @@ gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; }; }; + +&pinctrl { + power_led_pin: power-led-pin { + marvell,pins = "mpp57"; + marvell,function = "gpio"; + }; + + sata1_led_pin: sata1-led-pin { + marvell,pins = "mpp15"; + marvell,function = "gpio"; + }; + + sata2_led_pin: sata2-led-pin { + marvell,pins = "mpp14"; + marvell,function = "gpio"; + }; + + backup_led_pin: backup-led-pin { + marvell,pins = "mpp56"; + marvell,function = "gpio"; + }; + + backup_button_pin: backup-button-pin { + marvell,pins = "mpp58"; + marvell,function = "gpio"; + }; + + power_button_pin: power-button-pin { + marvell,pins = "mpp62"; + marvell,function = "gpio"; + }; + + reset_button_pin: reset-button-pin { + marvell,pins = "mpp6"; + marvell,function = "gpio"; + }; + + poweroff: poweroff { + marvell,pins = "mpp8"; + marvell,function = "gpio"; + }; +}; diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts index c5fe8b5dcdc7..30586e47986a 100644 --- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts +++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts @@ -53,39 +53,9 @@ status = "okay"; }; - pinctrl { - poweroff: poweroff { - marvell,pins = "mpp60"; - marvell,function = "gpio"; - }; - - backup_button_pin: backup-button-pin { - marvell,pins = "mpp52"; - marvell,function = "gpio"; - }; - - power_button_pin: power-button-pin { - marvell,pins = "mpp62"; - marvell,function = "gpio"; - }; - - backup_led_pin: backup-led-pin { - marvell,pins = "mpp63"; - marvell,function = "gpo"; - }; - - power_led_pin: power-led-pin { - marvell,pins = "mpp64"; - marvell,function = "gpio"; - }; - - reset_button_pin: reset-button-pin { - marvell,pins = "mpp65"; - marvell,function = "gpio"; - }; - }; - mdio { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; phy0: ethernet-phy@0 { /* Marvell 88E1318 */ reg = <0>; }; @@ -96,12 +66,16 @@ }; ethernet@70000 { + pinctrl-0 = <&ge0_rgmii_pins>; + pinctrl-names = "default"; status = "okay"; phy = <&phy0>; phy-mode = "rgmii-id"; }; ethernet@74000 { + pinctrl-0 = <&ge1_rgmii_pins>; + pinctrl-names = "default"; status = "okay"; phy = <&phy1>; phy-mode = "rgmii-id"; @@ -117,7 +91,7 @@ status = "okay"; isl12057: isl12057@68 { - compatible = "isl,isl12057"; + compatible = "isil,isl12057"; reg = <0x68>; }; @@ -145,6 +119,10 @@ marvell,nand-enable-arbiter; nand-on-flash-bbt; + /* Use Hardware BCH ECC */ + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + partition@0 { label = "u-boot"; reg = <0x0000000 0x180000>; /* 1.5MB */ @@ -259,3 +237,35 @@ gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; }; }; + +&pinctrl { + poweroff: poweroff { + marvell,pins = "mpp60"; + marvell,function = "gpio"; + }; + + backup_button_pin: backup-button-pin { + marvell,pins = "mpp52"; + marvell,function = "gpio"; + }; + + power_button_pin: power-button-pin { + marvell,pins = "mpp62"; + marvell,function = "gpio"; + }; + + backup_led_pin: backup-led-pin { + marvell,pins = "mpp63"; + marvell,function = "gpo"; + }; + + power_led_pin: power-led-pin { + marvell,pins = "mpp64"; + marvell,function = "gpio"; + }; + + reset_button_pin: reset-button-pin { + marvell,pins = "mpp65"; + marvell,function = "gpio"; + }; +}; diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts index 4169f4096ea3..394308951ed9 100644 --- a/arch/arm/boot/dts/armada-370-rd.dts +++ b/arch/arm/boot/dts/armada-370-rd.dts @@ -9,6 +9,15 @@ * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the default + * 0xd0000000). The 0xf1000000 is the default used by the recent, + * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier + * boards were delivered with an older version of the bootloader that + * left internal registers mapped at 0xd0000000. If you are in this + * situation, you should either update your bootloader (preferred + * solution) or the below Device Tree should be adjusted. */ /dts-v1/; @@ -30,7 +39,7 @@ }; soc { - ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000 + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>; pcie-controller { @@ -59,13 +68,11 @@ }; mdio { + pinctrl-0 = <&mdio_pins>; + pinctrl-names = "default"; phy0: ethernet-phy@0 { reg = <0>; }; - - phy1: ethernet-phy@1 { - reg = <1>; - }; }; ethernet@70000 { @@ -74,9 +81,14 @@ phy-mode = "sgmii"; }; ethernet@74000 { + pinctrl-0 = <&ge1_rgmii_pins>; + pinctrl-names = "default"; status = "okay"; - phy = <&phy1>; phy-mode = "rgmii-id"; + fixed-link { + speed = <1000>; + full-duplex; + }; }; mvsdio@d4000 { @@ -106,6 +118,26 @@ }; }; + gpio-fan { + compatible = "gpio-fan"; + gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = <0 0 3000 1>; + pinctrl-0 = <&fan_pins>; + pinctrl-names = "default"; + }; + + gpio_leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + sw_led { + label = "370rd:green:sw"; + gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + }; + nand@d0000 { status = "okay"; num-cs = <1>; @@ -128,4 +160,56 @@ }; }; }; + + dsa@0 { + compatible = "marvell,dsa"; + #address-cells = <2>; + #size-cells = <0>; + + dsa,ethernet = <ð1>; + dsa,mii-bus = <&mdio>; + + switch@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10 0>; /* MDIO address 16, switch 0 in tree */ + + port@0 { + reg = <0>; + label = "lan0"; + }; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan3"; + }; + + port@5 { + reg = <5>; + label = "cpu"; + }; + }; + }; }; + +&pinctrl { + fan_pins: fan-pins { + marvell,pins = "mpp8"; + marvell,function = "gpio"; + }; + + led_pins: led-pins { + marvell,pins = "mpp32"; + marvell,function = "gpio"; + }; +}; diff --git a/arch/arm/boot/dts/armada-370-synology-ds213j.dts b/arch/arm/boot/dts/armada-370-synology-ds213j.dts new file mode 100644 index 000000000000..70fecde76ccb --- /dev/null +++ b/arch/arm/boot/dts/armada-370-synology-ds213j.dts @@ -0,0 +1,316 @@ +/* + * Device Tree file for Synology DS213j + * + * Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the old 0xd0000000). + * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot + * bootloaders provided by Marvell. It is used in recent versions of + * DSM software provided by Synology. Nonetheless, some earlier boards + * were delivered with an older version of u-boot that left internal + * registers mapped at 0xd0000000. If you have such a device you will + * not be able to directly boot a kernel based on this Device Tree. In + * that case, the preferred solution is to update your bootloader (e.g. + * by upgrading to latest version of DSM, or building a new one and + * installing it from u-boot prompt) or adjust the Devive Tree + * (s/0xf1000000/0xd0000000/ in 'ranges' below). + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include "armada-370.dtsi" + +/ { + model = "Synology DS213j"; + compatible = "synology,ds213j", "marvell,armada370", + "marvell,armada-370-xp"; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = &uart0; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x20000000>; /* 512 MB */ + }; + + soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 + MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>; + + internal-regs { + + /* RTC provided by Seiko S-35390A I2C RTC chip below */ + rtc@10300 { + status = "disabled"; + }; + + spi0: spi@10600 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q064"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <20000000>; + + /* + * Warning! + * + * Synology u-boot uses its compiled-in environment + * and it seems Synology did not care to change u-boot + * default configuration in order to allow saving a + * modified environment at a sensible location. So, + * if you do a 'saveenv' under u-boot, your modified + * environment will be saved at 1MB after the start + * of the flash, i.e. in the middle of the uImage. + * For that reason, it is strongly advised not to + * change the default environment, unless you know + * what you are doing. + */ + partition@00000000 { /* u-boot */ + label = "RedBoot"; + reg = <0x00000000 0x000c0000>; /* 768KB */ + }; + + partition@000c0000 { /* uImage */ + label = "zImage"; + reg = <0x000c0000 0x002d0000>; /* 2880KB */ + }; + + partition@00390000 { /* uInitramfs */ + label = "rd.gz"; + reg = <0x00390000 0x00440000>; /* 4250KB */ + }; + + partition@007d0000 { /* MAC address and serial number */ + label = "vendor"; + reg = <0x007d0000 0x00010000>; /* 64KB */ + }; + + partition@007e0000 { + label = "RedBoot config"; + reg = <0x007e0000 0x00010000>; /* 64KB */ + }; + + partition@007f0000 { + label = "FIS directory"; + reg = <0x007f0000 0x00010000>; /* 64KB */ + }; + }; + }; + + i2c@11000 { + compatible = "marvell,mv64xxx-i2c"; + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; + + /* Main device RTC chip */ + s35390a: s35390a@30 { + compatible = "sii,s35390a"; + reg = <0x30>; + }; + }; + + /* Connected to a header on device's PCB */ + serial@12000 { + status = "okay"; + }; + + /* Connected to a TI MSP430F2111 for power control */ + serial@12100 { + status = "okay"; + }; + + poweroff@12100 { + compatible = "synology,power-off"; + reg = <0x12100 0x100>; + clocks = <&coreclk 0>; + }; + + /* rear USB port, near reset button */ + usb@50000 { + status = "okay"; + }; + + /* rear USB port, near RJ45 port */ + usb@51000 { + status = "okay"; + }; + + mdio { + phy1: ethernet-phy@1 { /* Marvell 88E1512 */ + reg = <1>; + }; + }; + + ethernet@70000 { + status = "okay"; + phy = <&phy1>; + phy-mode = "sgmii"; + }; + + sata@a0000 { + nr-ports = <2>; + status = "okay"; + }; + }; + }; + + gpio-fan-32-38 { + status = "okay"; + compatible = "gpio-fan"; + pinctrl-0 = <&fan_ctrl_low_pin &fan_ctrl_mid_pin + &fan_ctrl_high_pin &fan_alarm_pin>; + pinctrl-names = "default"; + gpios = <&gpio1 31 GPIO_ACTIVE_HIGH + &gpio2 0 GPIO_ACTIVE_HIGH + &gpio2 1 GPIO_ACTIVE_HIGH>; + alarm-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = < 0 0 + 1000 1 + 1150 2 + 1350 4 + 1500 3 + 1650 5 + 1750 6 + 1900 7 >; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&disk1_led_pin + &disk2_led_pin>; + pinctrl-names = "default"; + + disk1-led-amber { + label = "synology:amber:disk1"; + gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + + disk2-led-amber { + label = "synology:amber:disk2"; + gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + default-state = "keep"; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin>; + pinctrl-names = "default"; + + sata1_regulator: sata1-regulator { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "SATA1 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <2000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + }; + + sata2_regulator: sata2-regulator { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "SATA2 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <4000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 30 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&pinctrl { + disk1_led_pin: disk1-led-pin { + marvell,pins = "mpp31"; + marvell,function = "gpio"; + }; + + disk2_led_pin: disk2-led-pin { + marvell,pins = "mpp32"; + marvell,function = "gpio"; + }; + + sata1_pwr_pin: sata1-pwr-pin { + marvell,pins = "mpp37"; + marvell,function = "gpio"; + }; + + sata2_pwr_pin: sata2-pwr-pin { + marvell,pins = "mpp62"; + marvell,function = "gpio"; + }; + + sata1_pres_pin: sata1-pres-pin { + marvell,pins = "mpp60"; + marvell,function = "gpio"; + }; + + sata2_pres_pin: sata2-pres-pin { + marvell,pins = "mpp48"; + marvell,function = "gpio"; + }; + + syno_id_bit0_pin: syno-id-bit0-pin { + marvell,pins = "mpp55"; + marvell,function = "gpio"; + }; + + syno_id_bit1_pin: syno-id-bit1-pin { + marvell,pins = "mpp56"; + marvell,function = "gpio"; + }; + + syno_id_bit2_pin: syno-id-bit2-pin { + marvell,pins = "mpp57"; + marvell,function = "gpio"; + }; + + syno_id_bit3_pin: syno-id-bit3-pin { + marvell,pins = "mpp58"; + marvell,function = "gpio"; + }; + + fan_ctrl_low_pin: fan-ctrl-low-pin { + marvell,pins = "mpp65"; + marvell,function = "gpio"; + }; + + fan_ctrl_mid_pin: fan-ctrl-mid-pin { + marvell,pins = "mpp64"; + marvell,function = "gpio"; + }; + + fan_ctrl_high_pin: fan-ctrl-high-pin { + marvell,pins = "mpp63"; + marvell,function = "gpo"; + }; + + fan_alarm_pin: fan-alarm-pin { + marvell,pins = "mpp38"; + marvell,function = "gpio"; + }; +}; diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi index 23227e0027ec..1af428602748 100644 --- a/arch/arm/boot/dts/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/armada-370-xp.dtsi @@ -110,7 +110,7 @@ }; spi0: spi@10600 { - compatible = "marvell,orion-spi"; + compatible = "marvell,armada-370-spi", "marvell,orion-spi"; reg = <0x10600 0x28>; #address-cells = <1>; #size-cells = <0>; @@ -121,7 +121,7 @@ }; spi1: spi@10680 { - compatible = "marvell,orion-spi"; + compatible = "marvell,armada-370-spi", "marvell,orion-spi"; reg = <0x10680 0x28>; #address-cells = <1>; #size-cells = <0>; @@ -151,7 +151,7 @@ status = "disabled"; }; - serial@12000 { + uart0: serial@12000 { compatible = "snps,dw-apb-uart"; reg = <0x12000 0x100>; reg-shift = <2>; @@ -160,7 +160,8 @@ clocks = <&coreclk 0>; status = "disabled"; }; - serial@12100 { + + uart1: serial@12100 { compatible = "snps,dw-apb-uart"; reg = <0x12100 0x100>; reg-shift = <2>; @@ -170,6 +171,10 @@ status = "disabled"; }; + pinctrl: pin-ctrl@18000 { + reg = <0x18000 0x38>; + }; + coredivclk: corediv-clock@18740 { compatible = "marvell,armada-370-corediv-clock"; reg = <0x18740 0xc>; @@ -180,7 +185,8 @@ mbusc: mbus-controller@20000 { compatible = "marvell,mbus-controller"; - reg = <0x20000 0x100>, <0x20180 0x20>; + reg = <0x20000 0x100>, <0x20180 0x20>, + <0x20250 0x8>; }; mpic: interrupt-controller@20000 { @@ -232,7 +238,7 @@ status = "disabled"; }; - mdio { + mdio: mdio { #address-cells = <1>; #size-cells = <0>; compatible = "marvell,orion-mdio"; diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi index 21b588b6f6bd..fdb3c12a6139 100644 --- a/arch/arm/boot/dts/armada-370.dtsi +++ b/arch/arm/boot/dts/armada-370.dtsi @@ -95,62 +95,30 @@ compatible = "marvell,aurora-outer-cache"; reg = <0x08000 0x1000>; cache-id-part = <0x100>; + cache-unified; wt-override; }; - i2c0: i2c@11000 { - reg = <0x11000 0x20>; + /* + * Default SPI pinctrl setting, can be overwritten on + * board level if a different configuration is used. + */ + spi0: spi@10600 { + pinctrl-0 = <&spi0_pins1>; + pinctrl-names = "default"; }; - i2c1: i2c@11100 { - reg = <0x11100 0x20>; + spi1: spi@10680 { + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; }; - system-controller@18200 { - compatible = "marvell,armada-370-xp-system-controller"; - reg = <0x18200 0x100>; + i2c0: i2c@11000 { + reg = <0x11000 0x20>; }; - pinctrl { - compatible = "marvell,mv88f6710-pinctrl"; - reg = <0x18000 0x38>; - - sdio_pins1: sdio-pins1 { - marvell,pins = "mpp9", "mpp11", "mpp12", - "mpp13", "mpp14", "mpp15"; - marvell,function = "sd0"; - }; - - sdio_pins2: sdio-pins2 { - marvell,pins = "mpp47", "mpp48", "mpp49", - "mpp50", "mpp51", "mpp52"; - marvell,function = "sd0"; - }; - - sdio_pins3: sdio-pins3 { - marvell,pins = "mpp48", "mpp49", "mpp50", - "mpp51", "mpp52", "mpp53"; - marvell,function = "sd0"; - }; - - i2c0_pins: i2c0-pins { - marvell,pins = "mpp2", "mpp3"; - marvell,function = "i2c0"; - }; - - i2s_pins1: i2s-pins1 { - marvell,pins = "mpp5", "mpp6", "mpp7", - "mpp8", "mpp9", "mpp10", - "mpp12", "mpp13"; - marvell,function = "audio"; - }; - - i2s_pins2: i2s-pins2 { - marvell,pins = "mpp49", "mpp47", "mpp50", - "mpp59", "mpp57", "mpp61", - "mpp62", "mpp60", "mpp58"; - marvell,function = "audio"; - }; + i2c1: i2c@11100 { + reg = <0x11100 0x20>; }; gpio0: gpio@18100 { @@ -186,6 +154,26 @@ interrupts = <91>; }; + /* + * Default UART pinctrl setting without RTS/CTS, can + * be overwritten on board level if a different + * configuration is used. + */ + uart0: serial@12000 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + }; + + uart1: serial@12100 { + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + }; + + system-controller@18200 { + compatible = "marvell,armada-370-xp-system-controller"; + reg = <0x18200 0x100>; + }; + gateclk: clock-gating-control@18220 { compatible = "marvell,armada-370-gating-clock"; reg = <0x18220 0x4>; @@ -206,6 +194,10 @@ status = "okay"; }; + sscg@18330 { + reg = <0x18330 0x4>; + }; + interrupt-controller@20000 { reg = <0x20a00 0x1d0>, <0x21870 0x58>; }; @@ -226,6 +218,7 @@ }; audio_controller: audio-controller@30000 { + #sound-dai-cells = <1>; compatible = "marvell,armada370-audio"; reg = <0x30000 0x4000>; interrupts = <93>; @@ -282,3 +275,91 @@ }; }; }; + +&pinctrl { + compatible = "marvell,mv88f6710-pinctrl"; + + spi0_pins1: spi0-pins1 { + marvell,pins = "mpp33", "mpp34", + "mpp35", "mpp36"; + marvell,function = "spi0"; + }; + + spi0_pins2: spi0_pins2 { + marvell,pins = "mpp32", "mpp63", + "mpp64", "mpp65"; + marvell,function = "spi0"; + }; + + spi1_pins: spi1-pins { + marvell,pins = "mpp49", "mpp50", + "mpp51", "mpp52"; + marvell,function = "spi1"; + }; + + uart0_pins: uart0-pins { + marvell,pins = "mpp0", "mpp1"; + marvell,function = "uart0"; + }; + + uart1_pins: uart1-pins { + marvell,pins = "mpp41", "mpp42"; + marvell,function = "uart1"; + }; + + sdio_pins1: sdio-pins1 { + marvell,pins = "mpp9", "mpp11", "mpp12", + "mpp13", "mpp14", "mpp15"; + marvell,function = "sd0"; + }; + + sdio_pins2: sdio-pins2 { + marvell,pins = "mpp47", "mpp48", "mpp49", + "mpp50", "mpp51", "mpp52"; + marvell,function = "sd0"; + }; + + sdio_pins3: sdio-pins3 { + marvell,pins = "mpp48", "mpp49", "mpp50", + "mpp51", "mpp52", "mpp53"; + marvell,function = "sd0"; + }; + + i2c0_pins: i2c0-pins { + marvell,pins = "mpp2", "mpp3"; + marvell,function = "i2c0"; + }; + + i2s_pins1: i2s-pins1 { + marvell,pins = "mpp5", "mpp6", "mpp7", + "mpp8", "mpp9", "mpp10", + "mpp12", "mpp13"; + marvell,function = "audio"; + }; + + i2s_pins2: i2s-pins2 { + marvell,pins = "mpp49", "mpp47", "mpp50", + "mpp59", "mpp57", "mpp61", + "mpp62", "mpp60", "mpp58"; + marvell,function = "audio"; + }; + + mdio_pins: mdio-pins { + marvell,pins = "mpp17", "mpp18"; + marvell,function = "ge"; + }; + + ge0_rgmii_pins: ge0-rgmii-pins { + marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8", + "mpp9", "mpp10", "mpp11", "mpp12", + "mpp13", "mpp14", "mpp15", "mpp16"; + marvell,function = "ge0"; + }; + + ge1_rgmii_pins: ge1-rgmii-pins { + marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22", + "mpp23", "mpp24", "mpp25", "mpp26", + "mpp27", "mpp28", "mpp29", "mpp30"; + marvell,function = "ge1"; + }; +}; diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi index c1e49e7bf0fa..50096d3427eb 100644 --- a/arch/arm/boot/dts/armada-375.dtsi +++ b/arch/arm/boot/dts/armada-375.dtsi @@ -14,6 +14,7 @@ #include "skeleton.dtsi" #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/phy/phy.h> #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16)) @@ -36,6 +37,12 @@ #clock-cells = <0>; clock-frequency = <2000000000>; }; + /* 25 MHz reference crystal */ + refclk: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; }; cpus { @@ -185,6 +192,12 @@ }; }; + rtc@10300 { + compatible = "marvell,orion-rtc"; + reg = <0x10300 0x20>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + }; + spi0: spi@10600 { compatible = "marvell,orion-spi"; reg = <0x10600 0x50>; @@ -336,6 +349,12 @@ #clock-cells = <1>; }; + usbcluster: usb-cluster@18400 { + compatible = "marvell,armada-375-usb-cluster"; + reg = <0x18400 0x4>; + #phy-cells = <1>; + }; + mbusc: mbus-controller@20000 { compatible = "marvell,mbus-controller"; reg = <0x20000 0x100>, <0x20180 0x20>; @@ -360,13 +379,15 @@ <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, <&mpic 5>, <&mpic 6>; - clocks = <&coreclk 0>; + clocks = <&coreclk 0>, <&refclk>; + clock-names = "nbclk", "fixed"; }; watchdog@20300 { compatible = "marvell,armada-375-wdt"; reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>; - clocks = <&coreclk 0>; + clocks = <&coreclk 0>, <&refclk>; + clock-names = "nbclk", "fixed"; }; cpurst@20800 { @@ -384,6 +405,8 @@ reg = <0x50000 0x500>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gateclk 18>; + phys = <&usbcluster PHY_TYPE_USB2>; + phy-names = "usb"; status = "disabled"; }; @@ -400,6 +423,8 @@ reg = <0x58000 0x20000>,<0x5b880 0x80>; interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gateclk 16>; + phys = <&usbcluster PHY_TYPE_USB3>; + phy-names = "usb"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/armada-385-db.dts b/arch/arm/boot/dts/armada-385-db.dts index 1af886f1e486..2aaa9d2ac284 100644 --- a/arch/arm/boot/dts/armada-385-db.dts +++ b/arch/arm/boot/dts/armada-385-db.dts @@ -116,11 +116,11 @@ }; sdhci@d8000 { - clock-frequency = <200000000>; broken-cd; wp-inverted; bus-width = <8>; status = "okay"; + no-1-8-v; }; usb3@f0000 { diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 242d0ecc99f3..74391dace9e7 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -25,9 +25,9 @@ aliases { gpio0 = &gpio0; gpio1 = &gpio1; - eth0 = ð0; - eth1 = ð1; - eth2 = ð2; + ethernet0 = ð0; + ethernet1 = ð1; + ethernet2 = ð2; }; soc { diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts index a55a97a70505..ca0200e20751 100644 --- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts +++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts @@ -60,40 +60,6 @@ }; internal-regs { - pinctrl { - pinctrl-0 = <&pmx_phy_int>; - pinctrl-names = "default"; - - pmx_ge0: pmx-ge0 { - marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", - "mpp4", "mpp5", "mpp6", "mpp7", - "mpp8", "mpp9", "mpp10", "mpp11"; - marvell,function = "ge0"; - }; - - pmx_ge1: pmx-ge1 { - marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", - "mpp16", "mpp17", "mpp18", "mpp19", - "mpp20", "mpp21", "mpp22", "mpp23"; - marvell,function = "ge1"; - }; - - pmx_keys: pmx-keys { - marvell,pins = "mpp33"; - marvell,function = "gpio"; - }; - - pmx_spi: pmx-spi { - marvell,pins = "mpp36", "mpp37", "mpp38", "mpp39"; - marvell,function = "spi"; - }; - - pmx_phy_int: pmx-phy-int { - marvell,pins = "mpp32"; - marvell,function = "gpio"; - }; - }; - serial@12000 { status = "okay"; }; @@ -118,14 +84,14 @@ }; ethernet@70000 { - pinctrl-0 = <&pmx_ge0>; + pinctrl-0 = <&ge0_rgmii_pins>; pinctrl-names = "default"; status = "okay"; phy = <&phy0>; phy-mode = "rgmii-id"; }; ethernet@74000 { - pinctrl-0 = <&pmx_ge1>; + pinctrl-0 = <&ge1_rgmii_pins>; pinctrl-names = "default"; status = "okay"; phy = <&phy1>; @@ -134,8 +100,6 @@ spi0: spi@10600 { status = "okay"; - pinctrl-0 = <&pmx_spi>; - pinctrl-names = "default"; spi-flash@0 { #address-cells = <1>; @@ -152,7 +116,7 @@ compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; - pinctrl-0 = <&pmx_keys>; + pinctrl-0 = <&keys_pin>; pinctrl-names = "default"; button@1 { @@ -162,3 +126,18 @@ }; }; }; + +&pinctrl { + pinctrl-0 = <&phy_int_pin>; + pinctrl-names = "default"; + + keys_pin: keys-pin { + marvell,pins = "mpp33"; + marvell,function = "gpio"; + }; + + phy_int_pin: phy-int-pin { + marvell,pins = "mpp32"; + marvell,function = "gpio"; + }; +}; diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts index 0478c55ca656..ea8673647494 100644 --- a/arch/arm/boot/dts/armada-xp-gp.dts +++ b/arch/arm/boot/dts/armada-xp-gp.dts @@ -23,6 +23,7 @@ */ /dts-v1/; +#include <dt-bindings/gpio/gpio.h> #include "armada-xp-mv78460.dtsi" / { @@ -48,6 +49,14 @@ <0x00000001 0x00000000 0x00000001 0x00000000>; }; + cpus { + pm_pic { + ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>, + <&gpio0 17 GPIO_ACTIVE_LOW>, + <&gpio0 18 GPIO_ACTIVE_LOW>; + }; + }; + soc { ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 @@ -115,7 +124,15 @@ serial@12300 { status = "okay"; }; - + pinctrl { + pinctrl-0 = <&pic_pins>; + pinctrl-names = "default"; + pic_pins: pic-pins-0 { + marvell,pins = "mpp16", "mpp17", + "mpp18"; + marvell,function = "gpio"; + }; + }; sata@a0000 { nr-ports = <2>; status = "okay"; diff --git a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts index 469cf7137595..a2ef93c1eb10 100644 --- a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts +++ b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts @@ -22,7 +22,7 @@ chosen { bootargs = "console=ttyS0,115200 earlyprintk"; - stdout-path = "/soc/internal-regs/serial@12000"; + stdout-path = &uart0; }; memory { @@ -51,37 +51,6 @@ }; internal-regs { - pinctrl { - poweroff_pin: poweroff-pin { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - - power_button_pin: power-button-pin { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - reset_button_pin: reset-button-pin { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; - select_button_pin: select-button-pin { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - scroll_button_pin: scroll-button-pin { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - - hdd_led_pin: hdd-led-pin { - marvell,pins = "mpp26"; - marvell,function = "gpio"; - }; - }; - serial@12000 { status = "okay"; }; @@ -97,12 +66,16 @@ }; ethernet@70000 { + pinctrl-0 = <&ge0_rgmii_pins>; + pinctrl-names = "default"; status = "okay"; phy = <&phy0>; phy-mode = "rgmii-id"; }; ethernet@74000 { + pinctrl-0 = <&ge1_rgmii_pins>; + pinctrl-names = "default"; status = "okay"; phy = <&phy1>; phy-mode = "rgmii-id"; @@ -125,6 +98,11 @@ reg = <0x2e>; }; + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + }; + pcf8563@51 { compatible = "nxp,pcf8563"; reg = <0x51>; @@ -226,7 +204,7 @@ gpio-controller; #gpio-cells = <2>; reg = <0>; - registers-number = <2>; + registers-number = <1>; spi-max-frequency = <100000>; }; }; @@ -282,3 +260,34 @@ gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>; }; }; + +&pinctrl { + poweroff_pin: poweroff-pin { + marvell,pins = "mpp24"; + marvell,function = "gpio"; + }; + + power_button_pin: power-button-pin { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + reset_button_pin: reset-button-pin { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + select_button_pin: select-button-pin { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + + scroll_button_pin: scroll-button-pin { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + + hdd_led_pin: hdd-led-pin { + marvell,pins = "mpp26"; + marvell,function = "gpio"; + }; +}; diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi index 2592e1c13560..281ccd24295c 100644 --- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi @@ -167,17 +167,6 @@ }; internal-regs { - pinctrl { - compatible = "marvell,mv78230-pinctrl"; - reg = <0x18000 0x38>; - - sdio_pins: sdio-pins { - marvell,pins = "mpp30", "mpp31", "mpp32", - "mpp33", "mpp34", "mpp35"; - marvell,function = "sd0"; - }; - }; - gpio0: gpio@18100 { compatible = "marvell,orion-gpio"; reg = <0x18100 0x40>; @@ -202,3 +191,7 @@ }; }; }; + +&pinctrl { + compatible = "marvell,mv78230-pinctrl"; +}; diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi index 480e237a870f..d7a8d0b0f385 100644 --- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi @@ -251,17 +251,6 @@ }; internal-regs { - pinctrl { - compatible = "marvell,mv78260-pinctrl"; - reg = <0x18000 0x38>; - - sdio_pins: sdio-pins { - marvell,pins = "mpp30", "mpp31", "mpp32", - "mpp33", "mpp34", "mpp35"; - marvell,function = "sd0"; - }; - }; - gpio0: gpio@18100 { compatible = "marvell,orion-gpio"; reg = <0x18100 0x40>; @@ -305,3 +294,7 @@ }; }; }; + +&pinctrl { + compatible = "marvell,mv78260-pinctrl"; +}; diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi index 2c7b1fef4703..9c40c130d11a 100644 --- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi +++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi @@ -289,17 +289,6 @@ }; internal-regs { - pinctrl { - compatible = "marvell,mv78460-pinctrl"; - reg = <0x18000 0x38>; - - sdio_pins: sdio-pins { - marvell,pins = "mpp30", "mpp31", "mpp32", - "mpp33", "mpp34", "mpp35"; - marvell,function = "sd0"; - }; - }; - gpio0: gpio@18100 { compatible = "marvell,orion-gpio"; reg = <0x18100 0x40>; @@ -343,3 +332,7 @@ }; }; }; + +&pinctrl { + compatible = "marvell,mv78460-pinctrl"; +}; diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts index 0cf999abc4ed..d81430aa4ab3 100644 --- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts +++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts @@ -55,86 +55,10 @@ }; internal-regs { - pinctrl { - poweroff: poweroff { - marvell,pins = "mpp42"; - marvell,function = "gpio"; - }; - - power_button_pin: power-button-pin { - marvell,pins = "mpp27"; - marvell,function = "gpio"; - }; - - reset_button_pin: reset-button-pin { - marvell,pins = "mpp41"; - marvell,function = "gpio"; - }; - - sata1_led_pin: sata1-led-pin { - marvell,pins = "mpp31"; - marvell,function = "gpio"; - }; - - sata2_led_pin: sata2-led-pin { - marvell,pins = "mpp40"; - marvell,function = "gpio"; - }; - - sata3_led_pin: sata3-led-pin { - marvell,pins = "mpp44"; - marvell,function = "gpio"; - }; - - sata4_led_pin: sata4-led-pin { - marvell,pins = "mpp47"; - marvell,function = "gpio"; - }; - - sata1_power_pin: sata1-power-pin { - marvell,pins = "mpp24"; - marvell,function = "gpio"; - }; - - sata2_power_pin: sata2-power-pin { - marvell,pins = "mpp25"; - marvell,function = "gpio"; - }; - - sata3_power_pin: sata3-power-pin { - marvell,pins = "mpp26"; - marvell,function = "gpio"; - }; - - sata4_power_pin: sata4-power-pin { - marvell,pins = "mpp28"; - marvell,function = "gpio"; - }; - - sata1_pres_pin: sata1-pres-pin { - marvell,pins = "mpp32"; - marvell,function = "gpio"; - }; - - sata2_pres_pin: sata2-pres-pin { - marvell,pins = "mpp33"; - marvell,function = "gpio"; - }; - - sata3_pres_pin: sata3-pres-pin { - marvell,pins = "mpp34"; - marvell,function = "gpio"; - }; - - sata4_pres_pin: sata4-pres-pin { - marvell,pins = "mpp35"; - marvell,function = "gpio"; - }; - - err_led_pin: err-led-pin { - marvell,pins = "mpp45"; - marvell,function = "gpio"; - }; + /* Two rear eSATA ports */ + sata@a0000 { + nr-ports = <2>; + status = "okay"; }; serial@12000 { @@ -174,7 +98,7 @@ status = "okay"; isl12057: isl12057@68 { - compatible = "isl,isl12057"; + compatible = "isil,isl12057"; reg = <0x68>; }; @@ -223,6 +147,10 @@ marvell,nand-enable-arbiter; nand-on-flash-bbt; + /* Use Hardware BCH ECC */ + nand-ecc-strength = <4>; + nand-ecc-step-size = <512>; + partition@0 { label = "u-boot"; reg = <0x0000000 0x180000>; /* 1.5MB */ @@ -324,3 +252,85 @@ gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; }; }; + +&pinctrl { + poweroff: poweroff { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + + power_button_pin: power-button-pin { + marvell,pins = "mpp27"; + marvell,function = "gpio"; + }; + + reset_button_pin: reset-button-pin { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + + sata1_led_pin: sata1-led-pin { + marvell,pins = "mpp31"; + marvell,function = "gpio"; + }; + + sata2_led_pin: sata2-led-pin { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + + sata3_led_pin: sata3-led-pin { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + sata4_led_pin: sata4-led-pin { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + + sata1_power_pin: sata1-power-pin { + marvell,pins = "mpp24"; + marvell,function = "gpio"; + }; + + sata2_power_pin: sata2-power-pin { + marvell,pins = "mpp25"; + marvell,function = "gpio"; + }; + + sata3_power_pin: sata3-power-pin { + marvell,pins = "mpp26"; + marvell,function = "gpio"; + }; + + sata4_power_pin: sata4-power-pin { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + + sata1_pres_pin: sata1-pres-pin { + marvell,pins = "mpp32"; + marvell,function = "gpio"; + }; + + sata2_pres_pin: sata2-pres-pin { + marvell,pins = "mpp33"; + marvell,function = "gpio"; + }; + + sata3_pres_pin: sata3-pres-pin { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + + sata4_pres_pin: sata4-pres-pin { + marvell,pins = "mpp35"; + marvell,function = "gpio"; + }; + + err_led_pin: err-led-pin { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; +}; diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts index 4e5a59ee1501..6f6b0916df48 100644 --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts @@ -77,12 +77,7 @@ serial@12100 { status = "okay"; }; - pinctrl { - led_pins: led-pins-0 { - marvell,pins = "mpp49", "mpp51", "mpp53"; - marvell,function = "gpio"; - }; - }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -187,3 +182,10 @@ }; }; }; + +&pinctrl { + led_pins: led-pins-0 { + marvell,pins = "mpp49", "mpp51", "mpp53"; + marvell,function = "gpio"; + }; +}; diff --git a/arch/arm/boot/dts/armada-xp-synology-ds414.dts b/arch/arm/boot/dts/armada-xp-synology-ds414.dts new file mode 100644 index 000000000000..749fdba5a642 --- /dev/null +++ b/arch/arm/boot/dts/armada-xp-synology-ds414.dts @@ -0,0 +1,330 @@ +/* + * Device Tree file for Synology DS414 + * + * Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * Note: this Device Tree assumes that the bootloader has remapped the + * internal registers to 0xf1000000 (instead of the old 0xd0000000). + * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot + * bootloaders provided by Marvell. It is used in recent versions of + * DSM software provided by Synology. Nonetheless, some earlier boards + * were delivered with an older version of u-boot that left internal + * registers mapped at 0xd0000000. If you have such a device you will + * not be able to directly boot a kernel based on this Device Tree. In + * that case, the preferred solution is to update your bootloader (e.g. + * by upgrading to latest version of DSM, or building a new one and + * installing it from u-boot prompt) or adjust the Devive Tree + * (s/0xf1000000/0xd0000000/ in 'ranges' below). + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include "armada-xp-mv78230.dtsi" + +/ { + model = "Synology DS414"; + compatible = "synology,ds414", "marvell,armadaxp-mv78230", + "marvell,armadaxp", "marvell,armada-370-xp"; + + chosen { + bootargs = "console=ttyS0,115200 earlyprintk"; + stdout-path = &uart0; + }; + + memory { + device_type = "memory"; + reg = <0 0x00000000 0 0x40000000>; /* 1GB */ + }; + + soc { + ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 + MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>; + + pcie-controller { + status = "okay"; + + /* + * Connected to Marvell 88SX7042 SATA-II controller + * handling the four disks. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* + * Connected to EtronTech EJ168A XHCI controller + * providing the two rear USB 3.0 ports. + */ + pcie@5,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; + }; + + internal-regs { + + /* RTC is provided by Seiko S-35390A below */ + rtc@10300 { + status = "disabled"; + }; + + spi0: spi@10600 { + status = "okay"; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q064"; + reg = <0>; /* Chip select 0 */ + spi-max-frequency = <20000000>; + + /* + * Warning! + * + * Synology u-boot uses its compiled-in environment + * and it seems Synology did not care to change u-boot + * default configuration in order to allow saving a + * modified environment at a sensible location. So, + * if you do a 'saveenv' under u-boot, your modified + * environment will be saved at 1MB after the start + * of the flash, i.e. in the middle of the uImage. + * For that reason, it is strongly advised not to + * change the default environment, unless you know + * what you are doing. + */ + partition@00000000 { /* u-boot */ + label = "RedBoot"; + reg = <0x00000000 0x000d0000>; /* 832KB */ + }; + + partition@000c0000 { /* uImage */ + label = "zImage"; + reg = <0x000d0000 0x002d0000>; /* 2880KB */ + }; + + partition@003a0000 { /* uInitramfs */ + label = "rd.gz"; + reg = <0x003a0000 0x00430000>; /* 4250KB */ + }; + + partition@007d0000 { /* MAC address and serial number */ + label = "vendor"; + reg = <0x007d0000 0x00010000>; /* 64KB */ + }; + + partition@007e0000 { + label = "RedBoot config"; + reg = <0x007e0000 0x00010000>; /* 64KB */ + }; + + partition@007f0000 { + label = "FIS directory"; + reg = <0x007f0000 0x00010000>; /* 64KB */ + }; + }; + }; + + i2c@11000 { + clock-frequency = <400000>; + status = "okay"; + + s35390a: s35390a@30 { + compatible = "sii,s35390a"; + reg = <0x30>; + }; + }; + + /* Connected to a header on device's PCB. This + * provides the main console for the device. + * + * Warning: the device may not boot with a 3.3V + * USB-serial converter connected when the power + * button is pressed. The converter needs to be + * connected a few seconds after pressing the + * power button. This is possibly due to UART0_TXD + * pin being sampled at reset (bit 0 of SAR). + */ + serial@12000 { + status = "okay"; + }; + + /* Connected to a Microchip PIC16F883 for power control */ + serial@12100 { + status = "okay"; + }; + + poweroff@12100 { + compatible = "synology,power-off"; + reg = <0x12100 0x100>; + clocks = <&coreclk 0>; + }; + + /* Front USB 2.0 port */ + usb@50000 { + status = "okay"; + }; + + mdio { + phy0: ethernet-phy@0 { /* Marvell 88E1512 */ + reg = <0>; + }; + + phy1: ethernet-phy@1 { /* Marvell 88E1512 */ + reg = <1>; + }; + }; + + ethernet@70000 { + status = "okay"; + pinctrl-0 = <&ge0_rgmii_pins>; + pinctrl-names = "default"; + phy = <&phy1>; + phy-mode = "rgmii-id"; + }; + + ethernet@74000 { + pinctrl-0 = <&ge1_rgmii_pins>; + pinctrl-names = "default"; + status = "okay"; + phy = <&phy0>; + phy-mode = "rgmii-id"; + }; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin + &sata3_pwr_pin &sata4_pwr_pin>; + pinctrl-names = "default"; + + sata1_regulator: sata1-regulator { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "SATA1 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <2000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; + }; + + sata2_regulator: sata2-regulator { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "SATA2 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <4000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; + + sata3_regulator: sata3-regulator { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "SATA3 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <6000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>; + }; + + sata4_regulator: sata4-regulator { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "SATA4 Power"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + startup-delay-us = <8000000>; + enable-active-high; + regulator-always-on; + regulator-boot-on; + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&pinctrl { + sata1_pwr_pin: sata1-pwr-pin { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + + sata2_pwr_pin: sata2-pwr-pin { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + + sata3_pwr_pin: sata3-pwr-pin { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + + sata4_pwr_pin: sata4-pwr-pin { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + + sata1_pres_pin: sata1-pres-pin { + marvell,pins = "mpp34"; + marvell,function = "gpio"; + }; + + sata2_pres_pin: sata2-pres-pin { + marvell,pins = "mpp35"; + marvell,function = "gpio"; + }; + + sata3_pres_pin: sata3-pres-pin { + marvell,pins = "mpp40"; + marvell,function = "gpio"; + }; + + sata4_pres_pin: sata4-pres-pin { + marvell,pins = "mpp41"; + marvell,function = "gpio"; + }; + + syno_id_bit0_pin: syno-id-bit0-pin { + marvell,pins = "mpp26"; + marvell,function = "gpio"; + }; + + syno_id_bit1_pin: syno-id-bit1-pin { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + + syno_id_bit2_pin: syno-id-bit2-pin { + marvell,pins = "mpp29"; + marvell,function = "gpio"; + }; + + fan1_alarm_pin: fan1-alarm-pin { + marvell,pins = "mpp33"; + marvell,function = "gpio"; + }; + + fan2_alarm_pin: fan2-alarm-pin { + marvell,pins = "mpp32"; + marvell,function = "gpio"; + }; +}; diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi index bff9f6c18db1..62c3ba958b39 100644 --- a/arch/arm/boot/dts/armada-xp.dtsi +++ b/arch/arm/boot/dts/armada-xp.dtsi @@ -35,13 +35,24 @@ }; internal-regs { + sdramc@1400 { + compatible = "marvell,armada-xp-sdram-controller"; + reg = <0x1400 0x500>; + }; + L2: l2-cache { compatible = "marvell,aurora-system-cache"; reg = <0x08000 0x1000>; cache-id-part = <0x100>; + cache-unified; wt-override; }; + spi0: spi@10600 { + pinctrl-0 = <&spi0_pins>; + pinctrl-names = "default"; + }; + i2c0: i2c@11000 { compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c"; reg = <0x11000 0x100>; @@ -52,8 +63,10 @@ reg = <0x11100 0x100>; }; - serial@12200 { + uart2: serial@12200 { compatible = "snps,dw-apb-uart"; + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; reg = <0x12200 0x100>; reg-shift = <2>; interrupts = <43>; @@ -61,8 +74,11 @@ clocks = <&coreclk 0>; status = "disabled"; }; - serial@12300 { + + uart3: serial@12300 { compatible = "snps,dw-apb-uart"; + pinctrl-0 = <&uart3_pins>; + pinctrl-names = "default"; reg = <0x12300 0x100>; reg-shift = <2>; interrupts = <44>; @@ -199,3 +215,54 @@ }; }; }; + +&pinctrl { + ge0_gmii_pins: ge0-gmii-pins { + marvell,pins = + "mpp0", "mpp1", "mpp2", "mpp3", + "mpp4", "mpp5", "mpp6", "mpp7", + "mpp8", "mpp9", "mpp10", "mpp11", + "mpp12", "mpp13", "mpp14", "mpp15", + "mpp16", "mpp17", "mpp18", "mpp19", + "mpp20", "mpp21", "mpp22", "mpp23"; + marvell,function = "ge0"; + }; + + ge0_rgmii_pins: ge0-rgmii-pins { + marvell,pins = + "mpp0", "mpp1", "mpp2", "mpp3", + "mpp4", "mpp5", "mpp6", "mpp7", + "mpp8", "mpp9", "mpp10", "mpp11"; + marvell,function = "ge0"; + }; + + ge1_rgmii_pins: ge1-rgmii-pins { + marvell,pins = + "mpp12", "mpp13", "mpp14", "mpp15", + "mpp16", "mpp17", "mpp18", "mpp19", + "mpp20", "mpp21", "mpp22", "mpp23"; + marvell,function = "ge1"; + }; + + sdio_pins: sdio-pins { + marvell,pins = "mpp30", "mpp31", "mpp32", + "mpp33", "mpp34", "mpp35"; + marvell,function = "sd0"; + }; + + spi0_pins: spi0-pins { + marvell,pins = "mpp36", "mpp37", + "mpp38", "mpp39"; + marvell,function = "spi"; + }; + + uart2_pins: uart2-pins { + marvell,pins = "mpp42", "mpp43"; + marvell,function = "uart2"; + }; + + uart3_pins: uart3-pins { + marvell,pins = "mpp44", "mpp45"; + marvell,function = "uart3"; + }; +}; diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts b/arch/arm/boot/dts/at91-sama5d4ek.dts new file mode 100644 index 000000000000..9198b719d0ef --- /dev/null +++ b/arch/arm/boot/dts/at91-sama5d4ek.dts @@ -0,0 +1,260 @@ +/* + * at91-sama5d4ek.dts - Device Tree file for SAMA5D4 Evaluation Kit + * + * Copyright (C) 2014 Atmel, + * 2014 Nicolas Ferre <nicolas.ferre@atmel.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/dts-v1/; +#include "sama5d4.dtsi" + +/ { + model = "Atmel SAMA5D4-EK"; + compatible = "atmel,sama5d4ek", "atmel,sama5d4", "atmel,sama5"; + + chosen { + bootargs = "console=ttyS0,115200 ignore_loglevel earlyprintk"; + }; + + memory { + reg = <0x20000000 0x20000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + main_clock: clock@0 { + compatible = "atmel,osc", "fixed-clock"; + clock-frequency = <12000000>; + }; + + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <12000000>; + }; + }; + + ahb { + apb { + lcd_bus@f0000000 { + status = "okay"; + + lcd@f0000000 { + status = "okay"; + }; + + lcdovl1@f0000140 { + status = "okay"; + }; + + lcdovl2@f0000240 { + status = "okay"; + }; + + lcdheo1@f0000340 { + status = "okay"; + }; + }; + + adc0: adc@fc034000 { + /* The vref depends on JP22 of EK. If connect 1-2 then use 3.3V. connect 2-3 use 3.0V */ + atmel,adc-vref = <3300>; + /*atmel,adc-ts-wires = <4>;*/ /* Set up ADC touch screen */ + status = "okay"; /* Enable ADC IIO support */ + }; + + mmc0: mmc@f8000000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>; + slot@1 { + reg = <1>; + bus-width = <4>; + cd-gpios = <&pioE 5 0>; + }; + }; + + spi0: spi@f8010000 { + cs-gpios = <&pioC 3 0>, <0>, <0>, <0>; + status = "okay"; + m25p80@0 { + compatible = "atmel,at25df321a"; + spi-max-frequency = <50000000>; + reg = <0>; + }; + }; + + i2c0: i2c@f8014000 { + status = "okay"; + }; + + macb0: ethernet@f8020000 { + phy-mode = "rmii"; + status = "okay"; + }; + + mmc1: mmc@fc000000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>; + status = "okay"; + slot@0 { + reg = <0>; + bus-width = <4>; + cd-gpios = <&pioE 6 0>; + }; + }; + + usart2: serial@fc008000 { + status = "okay"; + }; + + usart3: serial@fc00c000 { + status = "okay"; + }; + + usart4: serial@fc010000 { + status = "okay"; + }; + + watchdog@fc068640 { + status = "okay"; + }; + + pinctrl@fc06a000 { + board { + pinctrl_mmc0_cd: mmc0_cd { + atmel,pins = + <AT91_PIOE 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; + }; + pinctrl_mmc1_cd: mmc1_cd { + atmel,pins = + <AT91_PIOE 6 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; + }; + pinctrl_usba_vbus: usba_vbus { + atmel,pins = + <AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; + }; + pinctrl_key_gpio: key_gpio_0 { + atmel,pins = + <AT91_PIOE 13 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PE13 gpio */ + }; + }; + }; + }; + + usb0: gadget@00400000 { + atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; + }; + + usb1: ohci@00500000 { + num-ports = <3>; + atmel,vbus-gpio = <0 /* &pioE 10 GPIO_ACTIVE_LOW */ + &pioE 11 GPIO_ACTIVE_LOW + &pioE 12 GPIO_ACTIVE_LOW + >; + status = "okay"; + }; + + usb2: ehci@00600000 { + status = "okay"; + }; + + nand0: nand@80000000 { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + atmel,has-pmecc; + status = "okay"; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + bootloader@40000 { + label = "bootloader"; + reg = <0x40000 0x80000>; + }; + + bootloaderenv@c0000 { + label = "bootloader env"; + reg = <0xc0000 0xc0000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x0f800000>; + }; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio>; + + pb_user1 { + label = "pb_user1"; + gpios = <&pioE 13 GPIO_ACTIVE_HIGH>; + linux,code = <0x100>; + gpio-key,wakeup; + }; + }; +}; diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi index cb100b03a362..dd1313cbc314 100644 --- a/arch/arm/boot/dts/at91sam9260.dtsi +++ b/arch/arm/boot/dts/at91sam9260.dtsi @@ -956,6 +956,14 @@ }; }; + rtc@fffffd20 { + compatible = "atmel,at91sam9260-rtt"; + reg = <0xfffffd20 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + status = "disabled"; + }; + watchdog@fffffd40 { compatible = "atmel,at91sam9260-wdt"; reg = <0xfffffd40 0x10>; @@ -966,6 +974,12 @@ atmel,idle-halt; status = "disabled"; }; + + gpbr: syscon@fffffd50 { + compatible = "atmel,at91sam9260-gpbr", "syscon"; + reg = <0xfffffd50 0x10>; + status = "disabled"; + }; }; nand0: nand@40000000 { diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi index a81aab4281a7..cdb9ed612109 100644 --- a/arch/arm/boot/dts/at91sam9261.dtsi +++ b/arch/arm/boot/dts/at91sam9261.dtsi @@ -828,12 +828,26 @@ clocks = <&mck>; }; + rtc@fffffd20 { + compatible = "atmel,at91sam9260-rtt"; + reg = <0xfffffd20 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&slow_xtal>; + status = "disabled"; + }; + watchdog@fffffd40 { compatible = "atmel,at91sam9260-wdt"; reg = <0xfffffd40 0x10>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; status = "disabled"; }; + + gpbr: syscon@fffffd50 { + compatible = "atmel,at91sam9260-gpbr", "syscon"; + reg = <0xfffffd50 0x10>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi index bb23c2d33cf8..1467750e3377 100644 --- a/arch/arm/boot/dts/at91sam9263.dtsi +++ b/arch/arm/boot/dts/at91sam9263.dtsi @@ -122,9 +122,10 @@ interrupts-extended = <&pmc AT91_PMC_LOCKB>; clocks = <&main>; reg = <1>; - atmel,clk-input-range = <1000000 5000000>; + atmel,clk-input-range = <1000000 32000000>; #atmel,pll-clk-output-range-cells = <4>; - atmel,pll-clk-output-ranges = <70000000 130000000 1 1>; + atmel,pll-clk-output-ranges = <80000000 200000000 0 1>, + <190000000 240000000 2 1>; }; mck: masterck { @@ -345,10 +346,14 @@ }; }; - ramc: ramc@ffffe200 { + ramc0: ramc@ffffe200 { compatible = "atmel,at91sam9260-sdramc"; - reg = <0xffffe200 0x200 - 0xffffe800 0x200>; + reg = <0xffffe200 0x200>; + }; + + ramc1: ramc@ffffe800 { + compatible = "atmel,at91sam9260-sdramc"; + reg = <0xffffe800 0x200>; }; pit: timer@fffffd30 { @@ -672,6 +677,14 @@ }; }; + can { + pinctrl_can_rx_tx: can_rx_tx { + atmel,pins = + <AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* CANRX, conflicts with IRQ0 */ + AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* CANTX, conflicts with PCK0 */ + }; + }; + pioA: gpio@fffff200 { compatible = "atmel,at91rm9200-gpio"; reg = <0xfffff200 0x200>; @@ -834,6 +847,7 @@ compatible = "atmel,hsmci"; reg = <0xfff80000 0x600>; interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; clocks = <&mci0_clk>; @@ -845,6 +859,7 @@ compatible = "atmel,hsmci"; reg = <0xfff84000 0x600>; interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; + pinctrl-names = "default"; #address-cells = <1>; #size-cells = <0>; clocks = <&mci1_clk>; @@ -898,6 +913,38 @@ clock-names = "pwm_clk"; status = "disabled"; }; + + can: can@fffac000 { + compatible = "atmel,at91sam9263-can"; + reg = <0xfffac000 0x300>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_rx_tx>; + clocks = <&can_clk>; + clock-names = "can_clk"; + }; + + rtc@fffffd20 { + compatible = "atmel,at91sam9260-rtt"; + reg = <0xfffffd20 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&slow_xtal>; + status = "disabled"; + }; + + rtc@fffffd50 { + compatible = "atmel,at91sam9260-rtt"; + reg = <0xfffffd50 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&slow_xtal>; + status = "disabled"; + }; + + gpbr: syscon@fffffd60 { + compatible = "atmel,at91sam9260-gpbr", "syscon"; + reg = <0xfffffd60 0x50>; + status = "disabled"; + }; }; fb0: fb@0x00700000 { diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi index 4e0abbd9d655..a50ee587a7af 100644 --- a/arch/arm/boot/dts/at91sam9g20.dtsi +++ b/arch/arm/boot/dts/at91sam9g20.dtsi @@ -22,6 +22,10 @@ compatible = "atmel,at91sam9g20-i2c"; }; + ssc0: ssc@fffbc000 { + compatible = "atmel,at91sam9rl-ssc"; + }; + adc0: adc@fffe0000 { atmel,adc-startup-time = <40>; }; diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi index d2919108e92d..dfaacb113f2e 100644 --- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi +++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi @@ -112,9 +112,23 @@ }; }; + shdwc@fffffd10 { + atmel,wakeup-counter = <10>; + atmel,wakeup-rtt-timer; + }; + + rtc@fffffd20 { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; + status = "okay"; + }; + watchdog@fffffd40 { status = "okay"; }; + + gpbr: syscon@fffffd50 { + status = "okay"; + }; }; nand0: nand@40000000 { diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi index 932a669156af..2a8da8a884b4 100644 --- a/arch/arm/boot/dts/at91sam9g45.dtsi +++ b/arch/arm/boot/dts/at91sam9g45.dtsi @@ -96,8 +96,14 @@ ramc0: ramc@ffffe400 { compatible = "atmel,at91sam9g45-ddramc"; - reg = <0xffffe400 0x200 - 0xffffe600 0x200>; + reg = <0xffffe400 0x200>; + clocks = <&ddrck>; + clock-names = "ddrck"; + }; + + ramc1: ramc@ffffe600 { + compatible = "atmel,at91sam9g45-ddramc"; + reg = <0xffffe600 0x200>; clocks = <&ddrck>; clock-names = "ddrck"; }; @@ -159,7 +165,7 @@ compatible = "atmel,at91rm9200-clk-master"; #clock-cells = <0>; interrupts-extended = <&pmc AT91_PMC_MCKRDY>; - clocks = <&slow_xtal>, <&main>, <&plladiv>, <&utmi>; + clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; atmel,clk-output-range = <0 133333333>; atmel,clk-divisors = <1 2 4 3>; }; @@ -175,7 +181,7 @@ #address-cells = <1>; #size-cells = <0>; interrupt-parent = <&pmc>; - clocks = <&slow_xtal>, <&main>, <&plladiv>, <&utmi>, <&mck>; + clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; prog0: prog0 { #clock-cells = <0>; @@ -486,6 +492,27 @@ }; }; + isi { + pinctrl_isi: isi-0 { + atmel,pins = <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* D8 */ + AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* D9 */ + AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* D10 */ + AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* D11 */ + AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* D0 */ + AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* D1 */ + AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* D2 */ + AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* D3 */ + AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* D4 */ + AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* D5 */ + AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* D6 */ + AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* D7 */ + AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PCK */ + AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* VSYNC */ + AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* HSYNC */ + AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_NONE /* MCK */>; + }; + }; + usart0 { pinctrl_usart0: usart0-0 { atmel,pins = @@ -934,6 +961,13 @@ status = "disabled"; }; + trng@fffcc000 { + compatible = "atmel,at91sam9g45-trng"; + reg = <0xfffcc000 0x4000>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&trng_clk>; + }; + i2c0: i2c@fff84000 { compatible = "atmel,at91sam9g10-i2c"; reg = <0xfff84000 0x100>; @@ -1022,6 +1056,17 @@ }; }; + isi@fffb4000 { + compatible = "atmel,at91sam9g45-isi"; + reg = <0xfffb4000 0x4000>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 5>; + clocks = <&isi_clk>; + clock-names = "isi_clk"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_isi>; + status = "disabled"; + }; + pwm0: pwm@fffb8000 { compatible = "atmel,at91sam9rl-pwm"; reg = <0xfffb8000 0x300>; @@ -1159,6 +1204,53 @@ atmel,can-isoc; }; }; + + sckc@fffffd50 { + compatible = "atmel,at91sam9x5-sckc"; + reg = <0xfffffd50 0x4>; + + slow_osc: slow_osc { + compatible = "atmel,at91sam9x5-clk-slow-osc"; + #clock-cells = <0>; + atmel,startup-time-usec = <1200000>; + clocks = <&slow_xtal>; + }; + + slow_rc_osc: slow_rc_osc { + compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; + #clock-cells = <0>; + atmel,startup-time-usec = <75>; + clock-frequency = <32768>; + clock-accuracy = <50000000>; + }; + + clk32k: slck { + compatible = "atmel,at91sam9x5-clk-slow"; + #clock-cells = <0>; + clocks = <&slow_rc_osc &slow_osc>; + }; + }; + + rtc@fffffd20 { + compatible = "atmel,at91sam9260-rtt"; + reg = <0xfffffd20 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + status = "disabled"; + }; + + rtc@fffffdb0 { + compatible = "atmel,at91rm9200-rtc"; + reg = <0xfffffdb0 0x30>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + status = "disabled"; + }; + + gpbr: syscon@fffffd60 { + compatible = "atmel,at91sam9260-gpbr", "syscon"; + reg = <0xfffffd60 0x10>; + status = "disabled"; + }; }; fb0: fb@0x00500000 { diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts index 96ccc7de4f0a..33ce7ca2c404 100644 --- a/arch/arm/boot/dts/at91sam9m10g45ek.dts +++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts @@ -160,6 +160,19 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm_leds>; }; + + rtc@fffffd20 { + atmel,rtt-rtc-time-reg = <&gpbr 0x0>; + status = "okay"; + }; + + gpbr: syscon@fffffd60 { + status = "okay"; + }; + + rtc@fffffdb0 { + status = "okay"; + }; }; fb0: fb@0x00500000 { diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi index 2bfac310dbec..68eb9aded164 100644 --- a/arch/arm/boot/dts/at91sam9n12.dtsi +++ b/arch/arm/boot/dts/at91sam9n12.dtsi @@ -87,6 +87,8 @@ ramc0: ramc@ffffe800 { compatible = "atmel,at91sam9g45-ddramc"; reg = <0xffffe800 0x200>; + clocks = <&ddrck>; + clock-names = "ddrck"; }; pmc: pmc@fffffc00 { diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts index 83d723711ae1..13bb24ea971a 100644 --- a/arch/arm/boot/dts/at91sam9n12ek.dts +++ b/arch/arm/boot/dts/at91sam9n12ek.dts @@ -136,6 +136,8 @@ }; usb0: ohci@00500000 { + num-ports = <1>; + atmel,vbus-gpio = <&pioB 7 GPIO_ACTIVE_LOW>; status = "okay"; }; }; diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi index ab56c8b81dfa..72424371413e 100644 --- a/arch/arm/boot/dts/at91sam9rl.dtsi +++ b/arch/arm/boot/dts/at91sam9rl.dtsi @@ -204,7 +204,7 @@ }; ssc0: ssc@fffc0000 { - compatible = "atmel,at91rm9200-ssc"; + compatible = "atmel,at91sam9rl-ssc"; reg = <0xfffc0000 0x4000>; interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; @@ -213,7 +213,7 @@ }; ssc1: ssc@fffc4000 { - compatible = "atmel,at91rm9200-ssc"; + compatible = "atmel,at91sam9rl-ssc"; reg = <0xfffc4000 0x4000>; interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; @@ -1059,6 +1059,27 @@ clocks = <&slow_rc_osc &slow_osc>; }; }; + + rtc@fffffeb0 { + compatible = "atmel,at91rm9200-rtc"; + reg = <0xfffffeb0 0x40>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + status = "disabled"; + }; + + rtc@fffffd20 { + compatible = "atmel,at91sam9260-rtt"; + reg = <0xfffffd20 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&clk32k>; + status = "disabled"; + }; + + gpbr: syscon@fffffd60 { + compatible = "atmel,at91sam9260-gpbr", "syscon"; + reg = <0xfffffd60 0x10>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/at91sam9x25.dtsi b/arch/arm/boot/dts/at91sam9x25.dtsi index c2554219f7a4..3c5fa3388997 100644 --- a/arch/arm/boot/dts/at91sam9x25.dtsi +++ b/arch/arm/boot/dts/at91sam9x25.dtsi @@ -10,6 +10,7 @@ #include "at91sam9x5_usart3.dtsi" #include "at91sam9x5_macb0.dtsi" #include "at91sam9x5_macb1.dtsi" +#include "at91sam9x5_can.dtsi" / { model = "Atmel AT91SAM9X25 SoC"; diff --git a/arch/arm/boot/dts/at91sam9x35.dtsi b/arch/arm/boot/dts/at91sam9x35.dtsi index 8eac66ce0ab7..499cdc81f4c0 100644 --- a/arch/arm/boot/dts/at91sam9x35.dtsi +++ b/arch/arm/boot/dts/at91sam9x35.dtsi @@ -8,6 +8,7 @@ #include "at91sam9x5.dtsi" #include "at91sam9x5_macb0.dtsi" +#include "at91sam9x5_can.dtsi" / { model = "Atmel AT91SAM9X35 SoC"; diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi index e1a5c70b885c..bbb3ba65165f 100644 --- a/arch/arm/boot/dts/at91sam9x5.dtsi +++ b/arch/arm/boot/dts/at91sam9x5.dtsi @@ -95,6 +95,8 @@ ramc0: ramc@ffffe800 { compatible = "atmel,at91sam9g45-ddramc"; reg = <0xffffe800 0x200>; + clocks = <&ddrck>; + clock-names = "ddrck"; }; pmc: pmc@fffffc00 { @@ -858,6 +860,9 @@ interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; + dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(8)>, + <&dma1 1 (AT91_DMA_CFG_PER_ID(9) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; clocks = <&mck>; clock-names = "usart"; status = "disabled"; @@ -869,6 +874,9 @@ interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0>; + dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(3)>, + <&dma0 1 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; clocks = <&usart0_clk>; clock-names = "usart"; status = "disabled"; @@ -880,6 +888,9 @@ interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1>; + dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(5)>, + <&dma0 1 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; clocks = <&usart1_clk>; clock-names = "usart"; status = "disabled"; @@ -891,6 +902,9 @@ interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2>; + dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(12)>, + <&dma1 1 (AT91_DMA_CFG_PER_ID(13) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; clocks = <&usart2_clk>; clock-names = "usart"; status = "disabled"; @@ -966,7 +980,7 @@ adc0: adc@f804c000 { #address-cells = <1>; #size-cells = <0>; - compatible = "atmel,at91sam9260-adc"; + compatible = "atmel,at91sam9x5-adc"; reg = <0xf804c000 0x100>; interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&adc_clk>, diff --git a/arch/arm/boot/dts/at91sam9x5_can.dtsi b/arch/arm/boot/dts/at91sam9x5_can.dtsi index f44ab7702a12..8eb2f9c1b978 100644 --- a/arch/arm/boot/dts/at91sam9x5_can.dtsi +++ b/arch/arm/boot/dts/at91sam9x5_can.dtsi @@ -1,5 +1,5 @@ /* - * at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1 + * at91sam9x5_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1 * Ethernet interface. * * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com> @@ -20,10 +20,50 @@ reg = <29>; }; - can1_clk: can1_clk { - #clock-cells = <0>; - reg = <30>; - }; + can1_clk: can1_clk { + #clock-cells = <0>; + reg = <30>; + }; + }; + }; + + can0: can@f8000000 { + compatible = "atmel,at91sam9x5-can"; + reg = <0xf8000000 0x300>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0_rx_tx>; + clocks = <&can0_clk>; + clock-names = "can_clk"; + status = "disabled"; + }; + + can1: can@f8004000 { + compatible = "atmel,at91sam9x5-can"; + reg = <0xf8004000 0x300>; + interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_rx_tx>; + clocks = <&can1_clk>; + clock-names = "can_clk"; + status = "disabled"; + }; + + pinctrl@fffff400 { + can0 { + pinctrl_can0_rx_tx: can0_rx_tx { + atmel,pins = + <AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANRX0, conflicts with DRXD */ + AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* CANTX0, conflicts with DTXD */ + }; + }; + + can1 { + pinctrl_can1_rx_tx: can1_rx_tx { + atmel,pins = + <AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANRX1, conflicts with RXD1 */ + AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* CANTX1, conflicts with TXD1 */ + }; }; }; }; diff --git a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi index 140217a54384..43bb5b51caa6 100644 --- a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi +++ b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi @@ -57,6 +57,9 @@ interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart3>; + dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(14)>, + <&dma1 1 (AT91_DMA_CFG_PER_ID(15) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; clocks = <&usart3_clk>; clock-names = "usart"; status = "disabled"; diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi index bb22842a0826..29598667420b 100644 --- a/arch/arm/boot/dts/atlas6.dtsi +++ b/arch/arm/boot/dts/atlas6.dtsi @@ -131,6 +131,7 @@ reg = <0x90020000 0x10000>; interrupts = <31>; clocks = <&clks 35>; + resets = <&rstc 6>; }; }; @@ -312,6 +313,7 @@ #address-cells = <1>; #size-cells = <0>; clocks = <&clks 19>; + resets = <&rstc 26>; status = "disabled"; }; @@ -327,6 +329,7 @@ #address-cells = <1>; #size-cells = <0>; clocks = <&clks 20>; + resets = <&rstc 27>; status = "disabled"; }; @@ -522,6 +525,18 @@ sirf,function = "sdmmc5"; }; }; + i2s_mclk_pins_a: i2s_mclk@0 { + i2s_mclk { + sirf,pins = "i2smclkgrp"; + sirf,function = "i2s_mclk"; + }; + }; + i2s_ext_clk_input_pins_a: i2s_ext_clk_input@0 { + i2s_ext_clk_input { + sirf,pins = "i2s_ext_clk_inputgrp"; + sirf,function = "i2s_ext_clk_input"; + }; + }; i2s_pins_a: i2s@0 { i2s { sirf,pins = "i2sgrp"; diff --git a/arch/arm/boot/dts/bcm-cygnus-clock.dtsi b/arch/arm/boot/dts/bcm-cygnus-clock.dtsi new file mode 100644 index 000000000000..60d8389fdb6c --- /dev/null +++ b/arch/arm/boot/dts/bcm-cygnus-clock.dtsi @@ -0,0 +1,91 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2014 Broadcom Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc: oscillator { + compatible = "fixed-clock"; + #clock-cells = <1>; + clock-frequency = <25000000>; + }; + + apb_clk: apb_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000000>; + }; + + periph_clk: periph_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <500000000>; + }; + + sdio_clk: lcpll_ch2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + axi81_clk: axi81_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + keypad_clk: keypad_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <31806>; + }; + + adc_clk: adc_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1562500>; + }; + + pwm_clk: pwm_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + }; + + lcd_clk: mipipll_ch1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; +}; diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi new file mode 100644 index 000000000000..5126f9e77a98 --- /dev/null +++ b/arch/arm/boot/dts/bcm-cygnus.dtsi @@ -0,0 +1,140 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2014 Broadcom Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + +#include "skeleton.dtsi" + +/ { + compatible = "brcm,cygnus"; + model = "Broadcom Cygnus SoC"; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x0>; + }; + }; + + /include/ "bcm-cygnus-clock.dtsi" + + amba { + #address-cells = <1>; + #size-cells = <1>; + compatible = "arm,amba-bus", "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + wdt@18009000 { + compatible = "arm,sp805" , "arm,primecell"; + reg = <0x18009000 0x1000>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&axi81_clk>; + clock-names = "apb_pclk"; + }; + }; + + uart0: serial@18020000 { + compatible = "snps,dw-apb-uart"; + reg = <0x18020000 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&axi81_clk>; + clock-frequency = <100000000>; + status = "disabled"; + }; + + uart1: serial@18021000 { + compatible = "snps,dw-apb-uart"; + reg = <0x18021000 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&axi81_clk>; + clock-frequency = <100000000>; + status = "disabled"; + }; + + uart2: serial@18022000 { + compatible = "snps,dw-apb-uart"; + reg = <0x18020000 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&axi81_clk>; + clock-frequency = <100000000>; + status = "disabled"; + }; + + uart3: serial@18023000 { + compatible = "snps,dw-apb-uart"; + reg = <0x18023000 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&axi81_clk>; + clock-frequency = <100000000>; + status = "disabled"; + }; + + gic: interrupt-controller@19021000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x19021000 0x1000>, + <0x19020100 0x100>; + }; + + L2: l2-cache { + compatible = "arm,pl310-cache"; + reg = <0x19022000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + timer@19020200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x19020200 0x100>; + interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&periph_clk>; + }; + +}; diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts new file mode 100644 index 000000000000..e479515099c3 --- /dev/null +++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts @@ -0,0 +1,30 @@ +/dts-v1/; +/include/ "bcm2835-rpi.dtsi" + +/ { + compatible = "raspberrypi,model-b-plus", "brcm,bcm2835"; + model = "Raspberry Pi Model B+"; + + leds { + act { + gpios = <&gpio 47 0>; + }; + + pwr { + label = "PWR"; + gpios = <&gpio 35 0>; + default-state = "keep"; + linux,default-trigger = "default-on"; + }; + }; +}; + +&gpio { + pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>; + + /* I2S interface */ + i2s_alt0: i2s_alt0 { + brcm,pins = <18 19 20 21>; + brcm,function = <4>; /* alt0 */ + }; +}; diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts index 2a3b1c1313a0..bafa46fc226a 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts @@ -1,57 +1,23 @@ /dts-v1/; -/include/ "bcm2835.dtsi" +/include/ "bcm2835-rpi.dtsi" / { compatible = "raspberrypi,model-b", "brcm,bcm2835"; model = "Raspberry Pi Model B"; - memory { - reg = <0 0x10000000>; - }; - leds { - compatible = "gpio-leds"; - act { - label = "ACT"; gpios = <&gpio 16 1>; - default-state = "keep"; - linux,default-trigger = "heartbeat"; }; }; }; &gpio { - pinctrl-names = "default"; - pinctrl-0 = <&gpioout &alt0 &alt3>; - - gpioout: gpioout { - brcm,pins = <6>; - brcm,function = <1>; /* GPIO out */ - }; - - alt0: alt0 { - brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 14 15 40 45>; - brcm,function = <4>; /* alt0 */ - }; + pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>; - alt3: alt3 { - brcm,pins = <48 49 50 51 52 53>; - brcm,function = <7>; /* alt3 */ + /* I2S interface */ + i2s_alt2: i2s_alt2 { + brcm,pins = <28 29 30 31>; + brcm,function = <6>; /* alt2 */ }; }; - -&i2c0 { - status = "okay"; - clock-frequency = <100000>; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <100000>; -}; - -&sdhci { - status = "okay"; - bus-width = <4>; -}; diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi new file mode 100644 index 000000000000..c7064487017d --- /dev/null +++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi @@ -0,0 +1,51 @@ +/include/ "bcm2835.dtsi" + +/ { + memory { + reg = <0 0x10000000>; + }; + + leds { + compatible = "gpio-leds"; + + act { + label = "ACT"; + default-state = "keep"; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&gpio { + pinctrl-names = "default"; + + gpioout: gpioout { + brcm,pins = <6>; + brcm,function = <1>; /* GPIO out */ + }; + + alt0: alt0 { + brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 14 15 40 45>; + brcm,function = <4>; /* alt0 */ + }; + + alt3: alt3 { + brcm,pins = <48 49 50 51 52 53>; + brcm,function = <7>; /* alt3 */ + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <100000>; +}; + +&sdhci { + status = "okay"; + bus-width = <4>; +}; diff --git a/arch/arm/boot/dts/bcm2835.dtsi b/arch/arm/boot/dts/bcm2835.dtsi index b8473c43e888..3342cb1407bc 100644 --- a/arch/arm/boot/dts/bcm2835.dtsi +++ b/arch/arm/boot/dts/bcm2835.dtsi @@ -99,6 +99,7 @@ dmas = <&dma 2>, <&dma 3>; dma-names = "tx", "rx"; + status = "disabled"; }; spi: spi@7e204000 { diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts new file mode 100644 index 000000000000..5fc0fae03092 --- /dev/null +++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts @@ -0,0 +1,64 @@ +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * DTS for Buffalo WZR-1750DHP + * + * Copyright (C) 2014 RafaÅ‚ MiÅ‚ecki <zajec5@gmail.com> + * + * Licensed under the GNU/GPL. See COPYING for details. + */ + +/dts-v1/; + +#include "bcm4708.dtsi" + +/ { + compatible = "buffalo,wzr-1750dhp", "brcm,bcm4708"; + model = "Buffalo WZR-1750DHP (BCM4708)"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory { + reg = <0x00000000 0x08000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <200>; + + restart { + label = "Reset"; + linux,code = <KEY_RESTART>; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + + aoss { + label = "AOSS"; + linux,code = <KEY_WPS_BUTTON>; + gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>; + }; + + /* Commit mode set by switch? */ + mode { + label = "Mode"; + linux,code = <KEY_SETUP>; + gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>; + }; + + /* Switch: AP mode */ + sw_ap { + label = "AP"; + linux,code = <BTN_0>; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + }; + + eject { + label = "USB eject"; + linux,code = <KEY_EJECTCD>; + gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts index 3b5259de5a38..4ed7de1058b7 100644 --- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts +++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts @@ -32,4 +32,63 @@ status = "okay"; }; }; + + leds { + compatible = "gpio-leds"; + + logo { + label = "bcm53xx:white:logo"; + gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + power0 { + label = "bcm53xx:green:power"; + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + power1 { + label = "bcm53xx:amber:power"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + usb { + label = "bcm53xx:blue:usb"; + gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + wireless { + label = "bcm53xx:blue:wireless"; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <200>; + + wps { + label = "WPS"; + linux,code = <KEY_WPS_BUTTON>; + gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; + }; + + rfkill { + label = "WiFi"; + linux,code = <KEY_RFKILL>; + gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; + }; + + restart { + label = "Reset"; + linux,code = <KEY_RESTART>; + gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; + }; + }; }; diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts new file mode 100644 index 000000000000..12fc2a01e6ab --- /dev/null +++ b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts @@ -0,0 +1,84 @@ +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * DTS for Netgear R6300 V2 + * + * Copyright (C) 2014 RafaÅ‚ MiÅ‚ecki <zajec5@gmail.com> + * + * Licensed under the GNU/GPL. See COPYING for details. + */ + +/dts-v1/; + +#include "bcm4708.dtsi" + +/ { + compatible = "netgear,r6300v2", "brcm,bcm4708"; + model = "Netgear R6300 V2 (BCM4708)"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory { + reg = <0x00000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + logo { + label = "bcm53xx:white:logo"; + gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + power0 { + label = "bcm53xx:green:power"; + gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + power1 { + label = "bcm53xx:amber:power"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + usb { + label = "bcm53xx:blue:usb"; + gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + wireless { + label = "bcm53xx:blue:wireless"; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <200>; + + wps { + label = "WPS"; + linux,code = <KEY_WPS_BUTTON>; + gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>; + }; + + rfkill { + label = "WiFi"; + linux,code = <KEY_RFKILL>; + gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>; + }; + + restart { + label = "Reset"; + linux,code = <KEY_RESTART>; + gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts new file mode 100644 index 000000000000..fb76378bd511 --- /dev/null +++ b/arch/arm/boot/dts/bcm47081-asus-rt-n18u.dts @@ -0,0 +1,78 @@ +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * DTS for Asus RT-N18U + * + * Copyright (C) 2014 RafaÅ‚ MiÅ‚ecki <zajec5@gmail.com> + * + * Licensed under the GNU/GPL. See COPYING for details. + */ + +/dts-v1/; + +#include "bcm47081.dtsi" + +/ { + compatible = "asus,rt-n18u", "brcm,bcm47081", "brcm,bcm4708"; + model = "Asus RT-N18U (BCM47081)"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory { + reg = <0x00000000 0x08000000>; + }; + + leds { + compatible = "gpio-leds"; + + power { + label = "bcm53xx:blue:power"; + gpios = <&chipcommon 0 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + usb2 { + label = "bcm53xx:blue:usb2"; + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + + wan { + label = "bcm53xx:blue:wan"; + gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + lan { + label = "bcm53xx:blue:lan"; + gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-on"; + }; + + usb3 { + label = "bcm53xx:blue:usb3"; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "default-off"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <200>; + + restart { + label = "Reset"; + linux,code = <KEY_RESTART>; + gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "WPS"; + linux,code = <KEY_WPS_BUTTON>; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts new file mode 100644 index 000000000000..bbb414fbad65 --- /dev/null +++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-600dhp2.dts @@ -0,0 +1,57 @@ +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * DTS for Buffalo WZR-600DHP2 + * + * Copyright (C) 2014 RafaÅ‚ MiÅ‚ecki <zajec5@gmail.com> + * + * Licensed under the GNU/GPL. See COPYING for details. + */ + +/dts-v1/; + +#include "bcm47081.dtsi" + +/ { + compatible = "buffalo,wzr-600dhp2", "brcm,bcm47081", "brcm,bcm4708"; + model = "Buffalo WZR-600DHP2 (BCM47081)"; + + chosen { + bootargs = "console=ttyS0,115200"; + }; + + memory { + reg = <0x00000000 0x08000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <200>; + + aoss { + label = "AOSS"; + linux,code = <KEY_WPS_BUTTON>; + gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>; + }; + + restart { + label = "Reset"; + linux,code = <KEY_RESTART>; + gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>; + }; + + /* Switch device mode? */ + mode { + label = "Mode"; + linux,code = <KEY_SETUP>; + gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>; + }; + + eject { + label = "USB eject"; + linux,code = <KEY_EJECTCD>; + gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm47081.dtsi b/arch/arm/boot/dts/bcm47081.dtsi new file mode 100644 index 000000000000..f720012ee5ed --- /dev/null +++ b/arch/arm/boot/dts/bcm47081.dtsi @@ -0,0 +1,26 @@ +/* + * Broadcom BCM470X / BCM5301X ARM platform code. + * DTS for BCM47081 SoC. + * + * Copyright © 2014 RafaÅ‚ MiÅ‚ecki <zajec5@gmail.com> + * + * Licensed under the GNU/GPL. See COPYING for details. + */ + +#include "bcm5301x.dtsi" + +/ { + compatible = "brcm,bcm47081"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi index 53c624f766b4..78aec6270c2f 100644 --- a/arch/arm/boot/dts/bcm5301x.dtsi +++ b/arch/arm/boot/dts/bcm5301x.dtsi @@ -8,6 +8,8 @@ * Licensed under the GNU/GPL. See COPYING for details. */ +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include "skeleton.dtsi" @@ -92,4 +94,53 @@ clock-frequency = <400000000>; }; }; + + axi@18000000 { + compatible = "brcm,bus-axi"; + reg = <0x18000000 0x1000>; + ranges = <0x00000000 0x18000000 0x00100000>; + #address-cells = <1>; + #size-cells = <1>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0x000fffff 0xffff>; + interrupt-map = + /* ChipCommon */ + <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + + /* USB 2.0 Controller */ + <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, + + /* USB 3.0 Controller */ + <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, + + /* Ethernet Controller 0 */ + <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + + /* Ethernet Controller 1 */ + <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + + /* Ethernet Controller 2 */ + <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + + /* Ethernet Controller 3 */ + <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + + /* NAND Controller */ + <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, + <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + + chipcommon: chipcommon@0 { + reg = <0x00000000 0x1000>; + + gpio-controller; + #gpio-cells = <2>; + }; + }; }; diff --git a/arch/arm/boot/dts/bcm63138.dtsi b/arch/arm/boot/dts/bcm63138.dtsi new file mode 100644 index 000000000000..d2d8e94e0aa2 --- /dev/null +++ b/arch/arm/boot/dts/bcm63138.dtsi @@ -0,0 +1,134 @@ +/* + * Broadcom BCM63138 DSL SoCs Device Tree + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + +#include "skeleton.dtsi" + +/ { + compatible = "brcm,bcm63138"; + model = "Broadcom BCM63138 DSL SoC"; + interrupt-parent = <&gic>; + + aliases { + uart0 = &serial0; + uart1 = &serial1; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <1>; + }; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + arm_timer_clk: arm_timer_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <500000000>; + }; + + periph_clk: periph_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + clock-output-names = "periph"; + }; + }; + + /* ARM bus */ + axi@80000000 { + compatible = "simple-bus"; + ranges = <0 0x80000000 0x784000>; + #address-cells = <1>; + #size-cells = <1>; + + L2: cache-controller@1d000 { + compatible = "arm,pl310-cache"; + reg = <0x1d000 0x1000>; + cache-unified; + cache-level = <2>; + cache-sets = <16>; + cache-size = <0x80000>; + interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>; + }; + + scu: scu@1e000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x1e000 0x100>; + }; + + gic: interrupt-controller@1e100 { + compatible = "arm,cortex-a9-gic"; + reg = <0x1f000 0x1000 + 0x1e100 0x100>; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + }; + + global_timer: timer@1e200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x1e200 0x20>; + interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&arm_timer_clk>; + }; + + local_timer: local-timer@1e600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x1e600 0x20>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&arm_timer_clk>; + }; + + twd_watchdog: watchdog@1e620 { + compatible = "arm,cortex-a9-twd-wdt"; + reg = <0x1e620 0x20>; + interrupts = <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + /* Legacy UBUS base */ + ubus@fffe8000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xfffe8000 0x8100>; + + serial0: serial@600 { + compatible = "brcm,bcm6345-uart"; + reg = <0x600 0x1b>; + interrupts = <GIC_SPI 32 0>; + clocks = <&periph_clk>; + clock-names = "periph"; + status = "disabled"; + }; + + serial1: serial@620 { + compatible = "brcm,bcm6345-uart"; + reg = <0x620 0x1b>; + interrupts = <GIC_SPI 33 0>; + clocks = <&periph_clk>; + clock-names = "periph"; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/bcm911360_entphn.dts b/arch/arm/boot/dts/bcm911360_entphn.dts new file mode 100644 index 000000000000..d2ee95280548 --- /dev/null +++ b/arch/arm/boot/dts/bcm911360_entphn.dts @@ -0,0 +1,53 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2014 Broadcom Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm-cygnus.dtsi" + +/ { + model = "Cygnus Enterprise Phone (BCM911360_ENTPHN)"; + compatible = "brcm,bcm11360", "brcm,cygnus"; + + aliases { + serial0 = &uart3; + }; + + chosen { + stdout-path = &uart3; + bootargs = "console=ttyS0,115200"; + }; + + uart3: serial@18023000 { + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/bcm911360k.dts b/arch/arm/boot/dts/bcm911360k.dts new file mode 100644 index 000000000000..9658d4f62d59 --- /dev/null +++ b/arch/arm/boot/dts/bcm911360k.dts @@ -0,0 +1,53 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2014 Broadcom Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm-cygnus.dtsi" + +/ { + model = "Cygnus SVK (BCM911360K)"; + compatible = "brcm,bcm11360", "brcm,cygnus"; + + aliases { + serial0 = &uart3; + }; + + chosen { + stdout-path = &uart3; + bootargs = "console=ttyS0,115200"; + }; + + uart3: serial@18023000 { + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/bcm958300k.dts b/arch/arm/boot/dts/bcm958300k.dts new file mode 100644 index 000000000000..f1bb36f3975c --- /dev/null +++ b/arch/arm/boot/dts/bcm958300k.dts @@ -0,0 +1,53 @@ +/* + * BSD LICENSE + * + * Copyright(c) 2014 Broadcom Corporation. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name of Broadcom Corporation nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +/dts-v1/; + +#include "bcm-cygnus.dtsi" + +/ { + model = "Cygnus SVK (BCM958300K)"; + compatible = "brcm,bcm58300", "brcm,cygnus"; + + aliases { + serial0 = &uart3; + }; + + chosen { + stdout-path = &uart3; + bootargs = "console=ttyS0,115200"; + }; + + uart3: serial@18023000 { + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/bcm963138dvt.dts b/arch/arm/boot/dts/bcm963138dvt.dts new file mode 100644 index 000000000000..69c93395ecd2 --- /dev/null +++ b/arch/arm/boot/dts/bcm963138dvt.dts @@ -0,0 +1,30 @@ +/* + * Broadcom BCM63138 Reference Board DTS + */ + +/dts-v1/; + +#include "bcm63138.dtsi" + +/ { + compatible = "brcm,BCM963138DVT", "brcm,bcm63138"; + model = "Broadcom BCM963138DVT"; + + chosen { + bootargs = "console=ttyS0,115200"; + stdout-path = &serial0; + }; + + memory { + reg = <0x0 0x08000000>; + }; + +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts b/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts index c72bfd468d10..86d85d8896a3 100644 --- a/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts +++ b/arch/arm/boot/dts/berlin2-sony-nsz-gs7.dts @@ -26,4 +26,20 @@ }; }; +&ahci { status = "okay"; }; + +ð1 { status = "okay"; }; + +/* Unpopulated SATA plug on solder side */ +&sata0 { status = "okay"; }; + +&sata_phy { status = "okay"; }; + +/* Samsung M8G2FA 8GB eMMC */ +&sdhci2 { + non-removable; + bus-width = <8>; + status = "okay"; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi index 9d7c810ebd0b..015a06c67c91 100644 --- a/arch/arm/boot/dts/berlin2.dtsi +++ b/arch/arm/boot/dts/berlin2.dtsi @@ -53,6 +53,35 @@ ranges = <0 0xf7000000 0x1000000>; + sdhci0: sdhci@ab0000 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xab0000 0x200>; + clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>; + clock-names = "io", "core"; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + sdhci1: sdhci@ab0800 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xab0800 0x200>; + clocks = <&chip CLKID_SDIO1XIN>, <&chip CLKID_SDIO1>; + clock-names = "io", "core"; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + sdhci2: sdhci@ab1000 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xab1000 0x200>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&chip CLKID_NFC_ECC>, <&chip CLKID_NFC>; + clock-names = "io", "core"; + pinctrl-0 = <&emmc_pmux>; + pinctrl-names = "default"; + status = "disabled"; + }; + l2: l2-cache-controller@ac0000 { compatible = "marvell,tauros3-cache", "arm,pl310-cache"; reg = <0xac0000 0x1000>; @@ -79,11 +108,47 @@ clocks = <&chip CLKID_TWD>; }; + eth1: ethernet@b90000 { + compatible = "marvell,pxa168-eth"; + reg = <0xb90000 0x10000>; + clocks = <&chip CLKID_GETH1>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + /* set by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + #address-cells = <1>; + #size-cells = <0>; + phy-connection-type = "mii"; + phy-handle = <ðphy1>; + status = "disabled"; + + ethphy1: ethernet-phy@0 { + reg = <0>; + }; + }; + cpu-ctrl@dd0000 { compatible = "marvell,berlin-cpu-ctrl"; reg = <0xdd0000 0x10000>; }; + eth0: ethernet@e50000 { + compatible = "marvell,pxa168-eth"; + reg = <0xe50000 0x10000>; + clocks = <&chip CLKID_GETH0>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + /* set by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + #address-cells = <1>; + #size-cells = <0>; + phy-connection-type = "mii"; + phy-handle = <ðphy0>; + status = "disabled"; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + }; + apb@e80000 { compatible = "simple-bus"; #address-cells = <1>; @@ -246,12 +311,57 @@ }; }; + ahci: sata@e90000 { + compatible = "marvell,berlin2-ahci", "generic-ahci"; + reg = <0xe90000 0x1000>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&chip CLKID_SATA>; + #address-cells = <1>; + #size-cells = <0>; + + sata0: sata-port@0 { + reg = <0>; + phys = <&sata_phy 0>; + status = "disabled"; + }; + + sata1: sata-port@1 { + reg = <1>; + phys = <&sata_phy 1>; + status = "disabled"; + }; + }; + + sata_phy: phy@e900a0 { + compatible = "marvell,berlin2-sata-phy"; + reg = <0xe900a0 0x200>; + clocks = <&chip CLKID_SATA>; + #address-cells = <1>; + #size-cells = <0>; + #phy-cells = <1>; + status = "disabled"; + + sata-phy@0 { + reg = <0>; + }; + + sata-phy@1 { + reg = <1>; + }; + }; + chip: chip-control@ea0000 { compatible = "marvell,berlin2-chip-ctrl"; #clock-cells = <1>; + #reset-cells = <2>; reg = <0xea0000 0x400>; clocks = <&refclk>; clock-names = "refclk"; + + emmc_pmux: emmc-pmux { + groups = "G26"; + function = "emmc"; + }; }; apb@fc0000 { diff --git a/arch/arm/boot/dts/berlin2cd-google-chromecast.dts b/arch/arm/boot/dts/berlin2cd-google-chromecast.dts index bcd81ffc495d..30270be4d0c9 100644 --- a/arch/arm/boot/dts/berlin2cd-google-chromecast.dts +++ b/arch/arm/boot/dts/berlin2cd-google-chromecast.dts @@ -11,6 +11,7 @@ /dts-v1/; #include "berlin2cd.dtsi" +#include <dt-bindings/gpio/gpio.h> / { model = "Google Chromecast"; @@ -24,6 +25,35 @@ device_type = "memory"; reg = <0x00000000 0x20000000>; /* 512 MB */ }; + + leds { + compatible = "gpio-leds"; + + white { + label = "white"; + gpios = <&portc 1 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + + red { + label = "red"; + gpios = <&portc 2 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + }; +}; + +/* + * AzureWave AW-NH387 (Marvell 88W8787) + * 802.11b/g/n + Bluetooth 2.1 + */ +&sdhci0 { + non-removable; + status = "okay"; }; &uart0 { status = "okay"; }; + +&usb_phy1 { status = "okay"; }; + +&usb1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi index cc1df65da504..230df3b1770e 100644 --- a/arch/arm/boot/dts/berlin2cd.dtsi +++ b/arch/arm/boot/dts/berlin2cd.dtsi @@ -45,6 +45,15 @@ ranges = <0 0xf7000000 0x1000000>; + sdhci0: sdhci@ab0000 { + compatible = "mrvl,pxav3-mmc"; + reg = <0xab0000 0x200>; + clocks = <&chip CLKID_SDIO0XIN>, <&chip CLKID_SDIO0>; + clock-names = "io", "core"; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + l2: l2-cache-controller@ac0000 { compatible = "arm,pl310-cache"; reg = <0xac0000 0x1000>; @@ -66,6 +75,58 @@ clocks = <&chip CLKID_TWD>; }; + usb_phy0: usb-phy@b74000 { + compatible = "marvell,berlin2cd-usb-phy"; + reg = <0xb74000 0x128>; + #phy-cells = <0>; + resets = <&chip 0x178 23>; + status = "disabled"; + }; + + usb_phy1: usb-phy@b78000 { + compatible = "marvell,berlin2cd-usb-phy"; + reg = <0xb78000 0x128>; + #phy-cells = <0>; + resets = <&chip 0x178 24>; + status = "disabled"; + }; + + eth1: ethernet@b90000 { + compatible = "marvell,pxa168-eth"; + reg = <0xb90000 0x10000>; + clocks = <&chip CLKID_GETH1>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + /* set by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + #address-cells = <1>; + #size-cells = <0>; + phy-connection-type = "mii"; + phy-handle = <ðphy1>; + status = "disabled"; + + ethphy1: ethernet-phy@0 { + reg = <0>; + }; + }; + + eth0: ethernet@e50000 { + compatible = "marvell,pxa168-eth"; + reg = <0xe50000 0x10000>; + clocks = <&chip CLKID_GETH0>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + /* set by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + #address-cells = <1>; + #size-cells = <0>; + phy-connection-type = "mii"; + phy-handle = <ðphy0>; + status = "disabled"; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + }; + apb@e80000 { compatible = "simple-bus"; #address-cells = <1>; @@ -231,6 +292,7 @@ chip: chip-control@ea0000 { compatible = "marvell,berlin2cd-chip-ctrl"; #clock-cells = <1>; + #reset-cells = <2>; reg = <0xea0000 0x400>; clocks = <&refclk>; clock-names = "refclk"; @@ -241,6 +303,26 @@ }; }; + usb0: usb@ed0000 { + compatible = "chipidea,usb2"; + reg = <0xed0000 0x200>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&chip CLKID_USB0>; + phys = <&usb_phy0>; + phy-names = "usb-phy"; + status = "disabled"; + }; + + usb1: usb@ee0000 { + compatible = "chipidea,usb2"; + reg = <0xee0000 0x200>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&chip CLKID_USB1>; + phys = <&usb_phy1>; + phy-names = "usb-phy"; + status = "disabled"; + }; + apb@fc0000 { compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts index a357ce02a64e..28e7e2060c33 100644 --- a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts +++ b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts @@ -7,6 +7,8 @@ */ /dts-v1/; + +#include <dt-bindings/gpio/gpio.h> #include "berlin2q.dtsi" / { @@ -21,6 +23,39 @@ choosen { bootargs = "console=ttyS0,115200 earlyprintk"; }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_usb0_vbus: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "usb0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&portb 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb1_vbus: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&portb 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb2_vbus: regulator@2 { + compatible = "regulator-fixed"; + regulator-name = "usb2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&portb 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + }; }; &sdhci1 { @@ -45,3 +80,33 @@ &uart0 { status = "okay"; }; + +&usb_phy0 { + status = "okay"; +}; + +&usb_phy2 { + status = "okay"; +}; + +&usb0 { + vbus-supply = <®_usb0_vbus>; + status = "okay"; +}; + +&usb2 { + vbus-supply = <®_usb2_vbus>; + status = "okay"; +}; + +ð0 { + status = "okay"; +}; + +&sata0 { + status = "okay"; +}; + +&sata_phy { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi index 400c40fceccc..35253c947a7c 100644 --- a/arch/arm/boot/dts/berlin2q.dtsi +++ b/arch/arm/boot/dts/berlin2q.dtsi @@ -114,6 +114,58 @@ #interrupt-cells = <3>; }; + usb_phy2: phy@a2f400 { + compatible = "marvell,berlin2-usb-phy"; + reg = <0xa2f400 0x128>; + #phy-cells = <0>; + resets = <&chip 0x104 14>; + status = "disabled"; + }; + + usb2: usb@a30000 { + compatible = "chipidea,usb2"; + reg = <0xa30000 0x10000>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&chip CLKID_USB2>; + phys = <&usb_phy2>; + phy-names = "usb-phy"; + status = "disabled"; + }; + + usb_phy0: phy@b74000 { + compatible = "marvell,berlin2-usb-phy"; + reg = <0xb74000 0x128>; + #phy-cells = <0>; + resets = <&chip 0x104 12>; + status = "disabled"; + }; + + usb_phy1: phy@b78000 { + compatible = "marvell,berlin2-usb-phy"; + reg = <0xb78000 0x128>; + #phy-cells = <0>; + resets = <&chip 0x104 13>; + status = "disabled"; + }; + + eth0: ethernet@b90000 { + compatible = "marvell,pxa168-eth"; + reg = <0xb90000 0x10000>; + clocks = <&chip CLKID_GETH0>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + /* set by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + #address-cells = <1>; + #size-cells = <0>; + phy-connection-type = "mii"; + phy-handle = <ðphy0>; + status = "disabled"; + + ethphy0: ethernet-phy@0 { + reg = <0>; + }; + }; + cpu-ctrl@dd0000 { compatible = "marvell,berlin-cpu-ctrl"; reg = <0xdd0000 0x10000>; @@ -238,7 +290,6 @@ reg = <0x2c14 0x14>; clocks = <&chip CLKID_CFG>; clock-names = "timer"; - status = "disabled"; }; timer2: timer@2c28 { @@ -332,6 +383,7 @@ chip: chip-control@ea0000 { compatible = "marvell,berlin2q-chip-ctrl"; #clock-cells = <1>; + #reset-cells = <2>; reg = <0xea0000 0x400>, <0xdd0170 0x10>; clocks = <&refclk>; clock-names = "refclk"; @@ -347,6 +399,65 @@ }; }; + ahci: sata@e90000 { + compatible = "marvell,berlin2q-ahci", "generic-ahci"; + reg = <0xe90000 0x1000>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&chip CLKID_SATA>; + #address-cells = <1>; + #size-cells = <0>; + + sata0: sata-port@0 { + reg = <0>; + phys = <&sata_phy 0>; + status = "disabled"; + }; + + sata1: sata-port@1 { + reg = <1>; + phys = <&sata_phy 1>; + status = "disabled"; + }; + }; + + sata_phy: phy@e900a0 { + compatible = "marvell,berlin2q-sata-phy"; + reg = <0xe900a0 0x200>; + clocks = <&chip CLKID_SATA>; + #address-cells = <1>; + #size-cells = <0>; + #phy-cells = <1>; + status = "disabled"; + + sata-phy@0 { + reg = <0>; + }; + + sata-phy@1 { + reg = <1>; + }; + }; + + usb0: usb@ed0000 { + compatible = "chipidea,usb2"; + reg = <0xed0000 0x10000>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&chip CLKID_USB0>; + phys = <&usb_phy0>; + phy-names = "usb-phy"; + status = "disabled"; + }; + + usb1: usb@ee0000 { + compatible = "chipidea,usb2"; + reg = <0xee0000 0x10000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&chip CLKID_USB1>; + phys = <&usb_phy1>; + phy-names = "usb-phy"; + status = "disabled"; + }; + apb@fc0000 { compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/cros-adc-thermistors.dtsi b/arch/arm/boot/dts/cros-adc-thermistors.dtsi new file mode 100644 index 000000000000..acd4fe1833f2 --- /dev/null +++ b/arch/arm/boot/dts/cros-adc-thermistors.dtsi @@ -0,0 +1,44 @@ +/* + * Thermistor dts fragment for devices that use Thermistors as + * children of the IIO based ADC. + * + * Currently, used by Exynos5420 based Peach PIT and + * Exynos5800 based Peach PI. + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +&adc { + ncp15wb473@3 { + compatible = "murata,ncp15wb473"; + pullup-uv = <1800000>; + pullup-ohm = <47000>; + pulldown-ohm = <0>; + io-channels = <&adc 3>; + }; + ncp15wb473@4 { + compatible = "murata,ncp15wb473"; + pullup-uv = <1800000>; + pullup-ohm = <47000>; + pulldown-ohm = <0>; + io-channels = <&adc 4>; + }; + ncp15wb473@5 { + compatible = "murata,ncp15wb473"; + pullup-uv = <1800000>; + pullup-ohm = <47000>; + pulldown-ohm = <0>; + io-channels = <&adc 5>; + }; + ncp15wb473@6 { + compatible = "murata,ncp15wb473"; + pullup-uv = <1800000>; + pullup-ohm = <47000>; + pulldown-ohm = <0>; + io-channels = <&adc 6>; + }; +}; diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts index 1e11e5a5f723..4f935ad9f27b 100644 --- a/arch/arm/boot/dts/da850-evm.dts +++ b/arch/arm/boot/dts/da850-evm.dts @@ -17,6 +17,18 @@ soc { pmx_core: pinmux@1c14120 { status = "okay"; + + mcasp0_pins: pinmux_mcasp0_pins { + pinctrl-single,bits = < + /* + * AHCLKX, ACLKX, AFSX, AHCLKR, ACLKR, + * AFSR, AMUTE + */ + 0x00 0x11111111 0xffffffff + /* AXR11, AXR12 */ + 0x04 0x00011000 0x000ff000 + >; + }; }; serial0: serial@1c42000 { status = "okay"; @@ -39,6 +51,20 @@ tps: tps@48 { reg = <0x48>; }; + tlv320aic3106: tlv320aic3106@18 { + #sound-dai-cells = <0>; + compatible = "ti,tlv320aic3106"; + reg = <0x18>; + status = "okay"; + + /* Regulators */ + IOVDD-supply = <&vdcdc2_reg>; + /* Derived from VBAT: Baseboard 3.3V / 1.8V */ + AVDD-supply = <&vbat>; + DRVDD-supply = <&vbat>; + DVDD-supply = <&vbat>; + }; + }; wdt: wdt@1c21000 { status = "okay"; @@ -117,6 +143,33 @@ regulator-max-microvolt = <5000000>; regulator-boot-on; }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "DA850/OMAP-L138 EVM"; + simple-audio-card,widgets = + "Line", "Line In", + "Line", "Line Out"; + simple-audio-card,routing = + "LINE1L", "Line In", + "LINE1R", "Line In", + "Line Out", "LLOUT", + "Line Out", "RLOUT"; + simple-audio-card,format = "dsp_b"; + simple-audio-card,bitclock-master = <&link0_codec>; + simple-audio-card,frame-master = <&link0_codec>; + simple-audio-card,bitclock-inversion; + + simple-audio-card,cpu { + sound-dai = <&mcasp0>; + system-clock-frequency = <24576000>; + }; + + link0_codec: simple-audio-card,codec { + sound-dai = <&tlv320aic3106>; + system-clock-frequency = <24576000>; + }; + }; }; /include/ "tps6507x.dtsi" @@ -170,3 +223,22 @@ }; }; }; + +&mcasp0 { + #sound-dai-cells = <0>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcasp0_pins>; + + op-mode = <0>; /* MCASP_IIS_MODE */ + tdm-slots = <2>; + /* 4 serializer */ + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 0 0 + 0 0 0 0 + 0 0 0 1 + 2 0 0 0 + >; + tx-num-evt = <32>; + rx-num-evt = <32>; +}; diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index b695548dbb4e..0bd98cd00816 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi @@ -150,6 +150,12 @@ }; }; + edma0: edma@01c00000 { + compatible = "ti,edma3"; + reg = <0x0 0x10000>; + interrupts = <11 13 12>; + #dma-cells = <1>; + }; serial0: serial@1c42000 { compatible = "ns16550a"; reg = <0x42000 0x100>; @@ -270,6 +276,19 @@ ti,davinci-gpio-unbanked = <0>; status = "disabled"; }; + + mcasp0: mcasp@01d00000 { + compatible = "ti,da830-mcasp-audio"; + reg = <0x100000 0x2000>, + <0x102000 0x400000>; + reg-names = "mpu", "dat"; + interrupts = <54>; + interrupt-names = "common"; + status = "disabled"; + dmas = <&edma0 1>, + <&edma0 0>; + dma-names = "tx", "rx"; + }; }; nand_cs3@62000000 { compatible = "ti,davinci-nand"; diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts index b40cdadb1f87..10b725c7bfc0 100644 --- a/arch/arm/boot/dts/dra7-evm.dts +++ b/arch/arm/boot/dts/dra7-evm.dts @@ -171,6 +171,101 @@ 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle */ >; }; + + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 1 */ + 0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txc.rgmii0_txc */ + 0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txctl.rgmii0_txctl */ + 0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_td3.rgmii0_txd3 */ + 0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd2.rgmii0_txd2 */ + 0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd1.rgmii0_txd1 */ + 0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii0_txd0.rgmii0_txd0 */ + 0x268 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxc.rgmii0_rxc */ + 0x26c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxctl.rgmii0_rxctl */ + 0x270 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd3.rgmii0_rxd3 */ + 0x274 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd2.rgmii0_rxd2 */ + 0x278 (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd1.rgmii0_rxd1 */ + 0x27c (PIN_INPUT | MUX_MODE0) /* rgmii0_rxd0.rgmii0_rxd0 */ + + /* Slave 2 */ + 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */ + 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */ + 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */ + 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */ + 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */ + 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */ + 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */ + 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */ + 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */ + 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */ + 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */ + 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ + >; + + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 1 */ + 0x250 (MUX_MODE15) + 0x254 (MUX_MODE15) + 0x258 (MUX_MODE15) + 0x25c (MUX_MODE15) + 0x260 (MUX_MODE15) + 0x264 (MUX_MODE15) + 0x268 (MUX_MODE15) + 0x26c (MUX_MODE15) + 0x270 (MUX_MODE15) + 0x274 (MUX_MODE15) + 0x278 (MUX_MODE15) + 0x27c (MUX_MODE15) + + /* Slave 2 */ + 0x198 (MUX_MODE15) + 0x19c (MUX_MODE15) + 0x1a0 (MUX_MODE15) + 0x1a4 (MUX_MODE15) + 0x1a8 (MUX_MODE15) + 0x1ac (MUX_MODE15) + 0x1b0 (MUX_MODE15) + 0x1b4 (MUX_MODE15) + 0x1b8 (MUX_MODE15) + 0x1bc (MUX_MODE15) + 0x1c0 (MUX_MODE15) + 0x1c4 (MUX_MODE15) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */ + 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + 0x23c (MUX_MODE15) + 0x240 (MUX_MODE15) + >; + }; + + dcan1_pins_default: dcan1_pins_default { + pinctrl-single,pins = < + 0x3d0 (PIN_OUTPUT | MUX_MODE0) /* dcan1_tx */ + 0x3d4 (MUX_MODE15) /* dcan1_rx.off */ + 0x418 (PULL_DIS | MUX_MODE1) /* wakeup0.dcan1_rx */ + >; + }; + + dcan1_pins_sleep: dcan1_pins_sleep { + pinctrl-single,pins = < + 0x3d0 (MUX_MODE15) /* dcan1_tx.off */ + 0x3d4 (MUX_MODE15) /* dcan1_rx.off */ + 0x418 (MUX_MODE15) /* wakeup0.off */ + >; + }; }; &i2c1 { @@ -201,6 +296,7 @@ regulator-name = "smps45"; regulator-min-microvolt = < 850000>; regulator-max-microvolt = <1150000>; + regulator-always-on; regulator-boot-on; }; @@ -208,7 +304,8 @@ /* VDD_GPU - over VDD_SMPS6 */ regulator-name = "smps6"; regulator-min-microvolt = <850000>; - regulator-max-microvolt = <12500000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; regulator-boot-on; }; @@ -216,7 +313,7 @@ /* CORE_VDD */ regulator-name = "smps7"; regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1030000>; + regulator-max-microvolt = <1060000>; regulator-always-on; regulator-boot-on; }; @@ -226,6 +323,7 @@ regulator-name = "smps8"; regulator-min-microvolt = < 850000>; regulator-max-microvolt = <1250000>; + regulator-always-on; regulator-boot-on; }; @@ -252,6 +350,7 @@ regulator-name = "ldo2"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + regulator-always-on; regulator-boot-on; }; @@ -269,6 +368,7 @@ regulator-name = "ldo9"; regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; + regulator-always-on; regulator-boot-on; }; @@ -323,6 +423,8 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&uart1_pins>; + interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <&dra7_pmx_core 0x3e0>; }; &uart2 { @@ -526,3 +628,36 @@ ti,no-reset-on-init; ti,no-idle-on-init; }; + +&mac { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; + dual_emac; +}; + +&cpsw_emac0 { + phy_id = <&davinci_mdio>, <2>; + phy-mode = "rgmii"; + dual_emac_res_vlan = <1>; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <3>; + phy-mode = "rgmii"; + dual_emac_res_vlan = <2>; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; +}; + +&dcan1 { + status = "ok"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&dcan1_pins_default>; + pinctrl-1 = <&dcan1_pins_sleep>; +}; diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index d678152db4cb..22771bc1643a 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -34,6 +34,14 @@ serial3 = &uart4; serial4 = &uart5; serial5 = &uart6; + serial6 = &uart7; + serial7 = &uart8; + serial8 = &uart9; + serial9 = &uart10; + ethernet0 = &cpsw_emac0; + ethernet1 = &cpsw_emac1; + d_can0 = &dcan1; + d_can1 = &dcan2; }; timer { @@ -89,6 +97,7 @@ prm: prm@4ae06000 { compatible = "ti,dra7-prm"; reg = <0x4ae06000 0x3000>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; prm_clocks: clocks { #address-cells = <1>; @@ -200,6 +209,11 @@ ti,hwmods = "counter_32k"; }; + dra7_ctrl_core: ctrl_core@4a002000 { + compatible = "syscon"; + reg = <0x4a002000 0x6d0>; + }; + dra7_ctrl_general: tisyscon@4a002e00 { compatible = "syscon"; reg = <0x4a002e00 0x7c>; @@ -217,10 +231,12 @@ }; dra7_pmx_core: pinmux@4a003400 { - compatible = "pinctrl-single"; + compatible = "ti,dra7-padconf", "pinctrl-single"; reg = <0x4a003400 0x0464>; #address-cells = <1>; #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; pinctrl-single,register-width = <32>; pinctrl-single,function-mask = <0x3fffffff>; }; @@ -328,61 +344,73 @@ uart1: serial@4806a000 { compatible = "ti,omap4-uart"; reg = <0x4806a000 0x100>; - interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart1"; clock-frequency = <48000000>; status = "disabled"; + dmas = <&sdma 49>, <&sdma 50>; + dma-names = "tx", "rx"; }; uart2: serial@4806c000 { compatible = "ti,omap4-uart"; reg = <0x4806c000 0x100>; - interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart2"; clock-frequency = <48000000>; status = "disabled"; + dmas = <&sdma 51>, <&sdma 52>; + dma-names = "tx", "rx"; }; uart3: serial@48020000 { compatible = "ti,omap4-uart"; reg = <0x48020000 0x100>; - interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart3"; clock-frequency = <48000000>; status = "disabled"; + dmas = <&sdma 53>, <&sdma 54>; + dma-names = "tx", "rx"; }; uart4: serial@4806e000 { compatible = "ti,omap4-uart"; reg = <0x4806e000 0x100>; - interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart4"; clock-frequency = <48000000>; status = "disabled"; + dmas = <&sdma 55>, <&sdma 56>; + dma-names = "tx", "rx"; }; uart5: serial@48066000 { compatible = "ti,omap4-uart"; reg = <0x48066000 0x100>; - interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart5"; clock-frequency = <48000000>; status = "disabled"; + dmas = <&sdma 63>, <&sdma 64>; + dma-names = "tx", "rx"; }; uart6: serial@48068000 { compatible = "ti,omap4-uart"; reg = <0x48068000 0x100>; - interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart6"; clock-frequency = <48000000>; status = "disabled"; + dmas = <&sdma 79>, <&sdma 80>; + dma-names = "tx", "rx"; }; uart7: serial@48420000 { compatible = "ti,omap4-uart"; reg = <0x48420000 0x100>; - interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&gic GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart7"; clock-frequency = <48000000>; status = "disabled"; @@ -391,7 +419,7 @@ uart8: serial@48422000 { compatible = "ti,omap4-uart"; reg = <0x48422000 0x100>; - interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&gic GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart8"; clock-frequency = <48000000>; status = "disabled"; @@ -400,7 +428,7 @@ uart9: serial@48424000 { compatible = "ti,omap4-uart"; reg = <0x48424000 0x100>; - interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&gic GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart9"; clock-frequency = <48000000>; status = "disabled"; @@ -409,7 +437,7 @@ uart10: serial@4ae2b000 { compatible = "ti,omap4-uart"; reg = <0x4ae2b000 0x100>; - interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&gic GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart10"; clock-frequency = <48000000>; status = "disabled"; @@ -418,7 +446,11 @@ mailbox1: mailbox@4a0f4000 { compatible = "ti,omap4-mailbox"; reg = <0x4a0f4000 0x200>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "mailbox1"; + #mbox-cells = <1>; ti,mbox-num-users = <3>; ti,mbox-num-fifos = <8>; status = "disabled"; @@ -427,7 +459,12 @@ mailbox2: mailbox@4883a000 { compatible = "ti,omap4-mailbox"; reg = <0x4883a000 0x200>; + interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "mailbox2"; + #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; status = "disabled"; @@ -436,7 +473,12 @@ mailbox3: mailbox@4883c000 { compatible = "ti,omap4-mailbox"; reg = <0x4883c000 0x200>; + interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "mailbox3"; + #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; status = "disabled"; @@ -445,7 +487,12 @@ mailbox4: mailbox@4883e000 { compatible = "ti,omap4-mailbox"; reg = <0x4883e000 0x200>; + interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "mailbox4"; + #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; status = "disabled"; @@ -454,7 +501,12 @@ mailbox5: mailbox@48840000 { compatible = "ti,omap4-mailbox"; reg = <0x48840000 0x200>; + interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "mailbox5"; + #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; status = "disabled"; @@ -463,7 +515,12 @@ mailbox6: mailbox@48842000 { compatible = "ti,omap4-mailbox"; reg = <0x48842000 0x200>; + interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "mailbox6"; + #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; status = "disabled"; @@ -472,7 +529,12 @@ mailbox7: mailbox@48844000 { compatible = "ti,omap4-mailbox"; reg = <0x48844000 0x200>; + interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "mailbox7"; + #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; status = "disabled"; @@ -481,7 +543,12 @@ mailbox8: mailbox@48846000 { compatible = "ti,omap4-mailbox"; reg = <0x48846000 0x200>; + interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "mailbox8"; + #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; status = "disabled"; @@ -490,7 +557,12 @@ mailbox9: mailbox@4885e000 { compatible = "ti,omap4-mailbox"; reg = <0x4885e000 0x200>; + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "mailbox9"; + #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; status = "disabled"; @@ -499,7 +571,12 @@ mailbox10: mailbox@48860000 { compatible = "ti,omap4-mailbox"; reg = <0x48860000 0x200>; + interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "mailbox10"; + #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; status = "disabled"; @@ -508,7 +585,12 @@ mailbox11: mailbox@48862000 { compatible = "ti,omap4-mailbox"; reg = <0x48862000 0x200>; + interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "mailbox11"; + #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; status = "disabled"; @@ -517,7 +599,12 @@ mailbox12: mailbox@48864000 { compatible = "ti,omap4-mailbox"; reg = <0x48864000 0x200>; + interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "mailbox12"; + #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; status = "disabled"; @@ -526,7 +613,12 @@ mailbox13: mailbox@48802000 { compatible = "ti,omap4-mailbox"; reg = <0x48802000 0x200>; + interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "mailbox13"; + #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <12>; status = "disabled"; @@ -650,7 +742,7 @@ }; wdt2: wdt@4ae14000 { - compatible = "ti,omap4-wdt"; + compatible = "ti,omap3-wdt"; reg = <0x4ae14000 0x80>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "wd_timer2"; @@ -1072,6 +1164,15 @@ status = "disabled"; }; + rtc@48838000 { + compatible = "ti,am3352-rtc"; + reg = <0x48838000 0x100>; + interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "rtcss"; + clocks = <&sys_32k_ck>; + }; + omap_control_usb2phy1: control-phy@4a002300 { compatible = "ti,control-phy-usb2"; reg = <0x4a002300 0x4>; @@ -1138,7 +1239,7 @@ }; }; - omap_dwc3_1@48880000 { + omap_dwc3_1: omap_dwc3_1@48880000 { compatible = "ti,dwc3"; ti,hwmods = "usb_otg_ss1"; reg = <0x48880000 0x10000>; @@ -1159,7 +1260,7 @@ }; }; - omap_dwc3_2@488c0000 { + omap_dwc3_2: omap_dwc3_2@488c0000 { compatible = "ti,dwc3"; ti,hwmods = "usb_otg_ss2"; reg = <0x488c0000 0x10000>; @@ -1181,7 +1282,7 @@ }; /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ - omap_dwc3_3@48900000 { + omap_dwc3_3: omap_dwc3_3@48900000 { compatible = "ti,dwc3"; ti,hwmods = "usb_otg_ss3"; reg = <0x48900000 0x10000>; @@ -1201,26 +1302,6 @@ }; }; - omap_dwc3_4@48940000 { - compatible = "ti,dwc3"; - ti,hwmods = "usb_otg_ss4"; - reg = <0x48940000 0x10000>; - interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <1>; - utmi-mode = <2>; - ranges; - status = "disabled"; - usb4: usb@48950000 { - compatible = "snps,dwc3"; - reg = <0x48950000 0x17000>; - interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; - tx-fifo-resize; - maximum-speed = "high-speed"; - dr_mode = "otg"; - }; - }; - elm: elm@48078000 { compatible = "ti,am3352-elm"; reg = <0x48078000 0xfc0>; /* device IO registers */ @@ -1262,6 +1343,84 @@ ti,irqs-skip = <10 133 139 140>; ti,irqs-safe-map = <0>; }; + + mac: ethernet@4a100000 { + compatible = "ti,cpsw"; + ti,hwmods = "gmac"; + clocks = <&dpll_gmac_ck>, <&gmac_gmii_ref_clk_div>; + clock-names = "fck", "cpts"; + cpdma_channels = <8>; + ale_entries = <1024>; + bd_ram_size = <0x2000>; + no_bd_ram = <0>; + rx_descs = <64>; + mac_control = <0x20>; + slaves = <2>; + active_slave = <0>; + cpts_clock_mult = <0x80000000>; + cpts_clock_shift = <29>; + reg = <0x48484000 0x1000 + 0x48485200 0x2E00>; + #address-cells = <1>; + #size-cells = <1>; + /* + * rx_thresh_pend + * rx_pend + * tx_pend + * misc_pend + */ + interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; + ranges; + status = "disabled"; + + davinci_mdio: mdio@48485000 { + compatible = "ti,davinci_mdio"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "davinci_mdio"; + bus_freq = <1000000>; + reg = <0x48485000 0x100>; + }; + + cpsw_emac0: slave@48480200 { + /* Filled in by U-Boot */ + mac-address = [ 00 00 00 00 00 00 ]; + }; + + cpsw_emac1: slave@48480300 { + /* Filled in by U-Boot */ + mac-address = [ 00 00 00 00 00 00 ]; + }; + + phy_sel: cpsw-phy-sel@4a002554 { + compatible = "ti,dra7xx-cpsw-phy-sel"; + reg= <0x4a002554 0x4>; + reg-names = "gmii-sel"; + }; + }; + + dcan1: can@481cc000 { + compatible = "ti,dra7-d_can"; + ti,hwmods = "dcan1"; + reg = <0x4ae3c000 0x2000>; + syscon-raminit = <&dra7_ctrl_core 0x558 0>; + interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&dcan1_sys_clk_mux>; + status = "disabled"; + }; + + dcan2: can@481d0000 { + compatible = "ti,dra7-d_can"; + ti,hwmods = "dcan2"; + reg = <0x48480000 0x2000>; + syscon-raminit = <&dra7_ctrl_core 0x558 1>; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sys_clkin1>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts index 514702348818..89085d066c65 100644 --- a/arch/arm/boot/dts/dra72-evm.dts +++ b/arch/arm/boot/dts/dra72-evm.dts @@ -17,8 +17,447 @@ device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1024 MB */ }; + + evm_3v3: fixedregulator-evm_3v3 { + compatible = "regulator-fixed"; + regulator-name = "evm_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&dra7_pmx_core { + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ + 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ + >; + }; + + nand_default: nand_default { + pinctrl-single,pins = < + 0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0 */ + 0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1 */ + 0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2 */ + 0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3 */ + 0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4 */ + 0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5 */ + 0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6 */ + 0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7 */ + 0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad8 */ + 0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad9 */ + 0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad10 */ + 0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad11 */ + 0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad12 */ + 0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad13 */ + 0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad14 */ + 0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad15 */ + 0xb4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_cs0 */ + 0xc4 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale */ + 0xcc (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen */ + 0xc8 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren */ + 0xd0 (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0 */ + 0xd8 (PIN_INPUT | MUX_MODE0) /* gpmc_wait0 */ + >; + }; + + usb1_pins: pinmux_usb1_pins { + pinctrl-single,pins = < + 0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */ + >; + }; + + usb2_pins: pinmux_usb2_pins { + pinctrl-single,pins = < + 0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */ + >; + }; + + tps65917_pins_default: tps65917_pins_default { + pinctrl-single,pins = < + 0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */ + >; + }; + + mmc1_pins_default: mmc1_pins_default { + pinctrl-single,pins = < + 0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ + 0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ + 0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + 0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + 0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + 0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + 0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; + + mmc2_pins_default: mmc2_pins_default { + pinctrl-single,pins = < + 0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ + 0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ + 0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ + 0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ + 0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ + 0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ + 0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ + 0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ + 0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ + 0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ + >; + }; + + dcan1_pins_default: dcan1_pins_default { + pinctrl-single,pins = < + 0x3d0 (PIN_OUTPUT | MUX_MODE0) /* dcan1_tx */ + 0x3d4 (MUX_MODE15) /* dcan1_rx.off */ + 0x418 (PULL_DIS | MUX_MODE1) /* wakeup0.dcan1_rx */ + >; + }; + + dcan1_pins_sleep: dcan1_pins_sleep { + pinctrl-single,pins = < + 0x3d0 (MUX_MODE15) /* dcan1_tx.off */ + 0x3d4 (MUX_MODE15) /* dcan1_rx.off */ + 0x418 (MUX_MODE15) /* wakeup0.off */ + >; + }; +}; + +&i2c1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <400000>; + + tps65917: tps65917@58 { + compatible = "ti,tps65917"; + reg = <0x58>; + + pinctrl-names = "default"; + pinctrl-0 = <&tps65917_pins_default>; + + interrupts = <GIC_SPI 2 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */ + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <2>; + + ti,system-power-controller; + + tps65917_pmic { + compatible = "ti,tps65917-pmic"; + + regulators { + smps1_reg: smps1 { + /* VDD_MPU */ + regulator-name = "smps1"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-boot-on; + }; + + smps2_reg: smps2 { + /* VDD_CORE */ + regulator-name = "smps2"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1060000>; + regulator-boot-on; + regulator-always-on; + }; + + smps3_reg: smps3 { + /* VDD_GPU IVA DSPEVE */ + regulator-name = "smps3"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-boot-on; + regulator-always-on; + }; + + smps4_reg: smps4 { + /* VDDS1V8 */ + regulator-name = "smps4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + smps5_reg: smps5 { + /* VDD_DDR */ + regulator-name = "smps5"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo1_reg: ldo1 { + /* LDO1_OUT --> SDIO */ + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + + ldo2_reg: ldo2 { + /* LDO2_OUT --> TP1017 (UNUSED) */ + regulator-name = "ldo2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo3_reg: ldo3 { + /* VDDA_1V8_PHY */ + regulator-name = "ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo5_reg: ldo5 { + /* VDDA_1V8_PLL */ + regulator-name = "ldo5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo4_reg: ldo4 { + /* VDDA_3V_USB: VDDA_USBHS33 */ + regulator-name = "ldo4"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + }; + }; + }; + + tps65917_power_button { + compatible = "ti,palmas-pwrbutton"; + interrupt-parent = <&tps65917>; + interrupts = <1 IRQ_TYPE_NONE>; + wakeup-source; + ti,palmas-long-press-seconds = <6>; + }; + }; }; &uart1 { status = "okay"; }; + +&elm { + status = "okay"; +}; + +&gpmc { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&nand_default>; + ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */ + nand@0,0 { + /* To use NAND, DIP switch SW5 must be set like so: + * SW5.1 (NAND_SELn) = ON (LOW) + * SW5.9 (GPMC_WPN) = OFF (HIGH) + */ + reg = <0 0 4>; /* device IO registers */ + ti,nand-ecc-opt = "bch8"; + ti,elm-id = <&elm>; + nand-bus-width = <16>; + gpmc,device-width = <2>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <80>; + gpmc,cs-wr-off-ns = <80>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <60>; + gpmc,adv-wr-off-ns = <60>; + gpmc,we-on-ns = <10>; + gpmc,we-off-ns = <50>; + gpmc,oe-on-ns = <4>; + gpmc,oe-off-ns = <40>; + gpmc,access-ns = <40>; + gpmc,wr-access-ns = <80>; + gpmc,rd-cycle-ns = <80>; + gpmc,wr-cycle-ns = <80>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,wr-data-mux-bus-ns = <0>; + /* MTD partition table */ + /* All SPL-* partitions are sized to minimal length + * which can be independently programmable. For + * NAND flash this is equal to size of erase-block */ + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "NAND.SPL"; + reg = <0x00000000 0x000020000>; + }; + partition@1 { + label = "NAND.SPL.backup1"; + reg = <0x00020000 0x00020000>; + }; + partition@2 { + label = "NAND.SPL.backup2"; + reg = <0x00040000 0x00020000>; + }; + partition@3 { + label = "NAND.SPL.backup3"; + reg = <0x00060000 0x00020000>; + }; + partition@4 { + label = "NAND.u-boot-spl-os"; + reg = <0x00080000 0x00040000>; + }; + partition@5 { + label = "NAND.u-boot"; + reg = <0x000c0000 0x00100000>; + }; + partition@6 { + label = "NAND.u-boot-env"; + reg = <0x001c0000 0x00020000>; + }; + partition@7 { + label = "NAND.u-boot-env.backup1"; + reg = <0x001e0000 0x00020000>; + }; + partition@8 { + label = "NAND.kernel"; + reg = <0x00200000 0x00800000>; + }; + partition@9 { + label = "NAND.file-system"; + reg = <0x00a00000 0x0f600000>; + }; + }; +}; + +&usb2_phy1 { + phy-supply = <&ldo4_reg>; +}; + +&usb2_phy2 { + phy-supply = <&ldo4_reg>; +}; + +&usb1 { + dr_mode = "peripheral"; + pinctrl-names = "default"; + pinctrl-0 = <&usb1_pins>; +}; + +&usb2 { + dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&usb2_pins>; +}; + +&mmc1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins_default>; + + vmmc-supply = <&ldo1_reg>; + bus-width = <4>; + /* + * SDCD signal is not being used here - using the fact that GPIO mode + * is a viable alternative + */ + cd-gpios = <&gpio6 27 0>; +}; + +&mmc2 { + /* SW5-3 in ON position */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins_default>; + + vmmc-supply = <&evm_3v3>; + bus-width = <8>; + ti,non-removable; +}; + +&dra7_pmx_core { + cpsw_default: cpsw_default { + pinctrl-single,pins = < + /* Slave 2 */ + 0x198 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d12.rgmii1_txc */ + 0x19c (PIN_OUTPUT | MUX_MODE3) /* vin2a_d13.rgmii1_tctl */ + 0x1a0 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d14.rgmii1_td3 */ + 0x1a4 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d15.rgmii1_td2 */ + 0x1a8 (PIN_OUTPUT | MUX_MODE3) /* vin2a_d16.rgmii1_td1 */ + 0x1ac (PIN_OUTPUT | MUX_MODE3) /* vin2a_d17.rgmii1_td0 */ + 0x1b0 (PIN_INPUT | MUX_MODE3) /* vin2a_d18.rgmii1_rclk */ + 0x1b4 (PIN_INPUT | MUX_MODE3) /* vin2a_d19.rgmii1_rctl */ + 0x1b8 (PIN_INPUT | MUX_MODE3) /* vin2a_d20.rgmii1_rd3 */ + 0x1bc (PIN_INPUT | MUX_MODE3) /* vin2a_d21.rgmii1_rd2 */ + 0x1c0 (PIN_INPUT | MUX_MODE3) /* vin2a_d22.rgmii1_rd1 */ + 0x1c4 (PIN_INPUT | MUX_MODE3) /* vin2a_d23.rgmii1_rd0 */ + >; + + }; + + cpsw_sleep: cpsw_sleep { + pinctrl-single,pins = < + /* Slave 2 */ + 0x198 (MUX_MODE15) + 0x19c (MUX_MODE15) + 0x1a0 (MUX_MODE15) + 0x1a4 (MUX_MODE15) + 0x1a8 (MUX_MODE15) + 0x1ac (MUX_MODE15) + 0x1b0 (MUX_MODE15) + 0x1b4 (MUX_MODE15) + 0x1b8 (MUX_MODE15) + 0x1bc (MUX_MODE15) + 0x1c0 (MUX_MODE15) + 0x1c4 (MUX_MODE15) + >; + }; + + davinci_mdio_default: davinci_mdio_default { + pinctrl-single,pins = < + /* MDIO */ + 0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_d.mdio_d */ + 0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ + >; + }; + + davinci_mdio_sleep: davinci_mdio_sleep { + pinctrl-single,pins = < + 0x23c (MUX_MODE15) + 0x240 (MUX_MODE15) + >; + }; +}; + +&mac { + status = "okay"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&cpsw_default>; + pinctrl-1 = <&cpsw_sleep>; +}; + +&cpsw_emac1 { + phy_id = <&davinci_mdio>, <3>; + phy-mode = "rgmii"; +}; + +&davinci_mdio { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&davinci_mdio_default>; + pinctrl-1 = <&davinci_mdio_sleep>; + active_slave = <1>; +}; + +&dcan1 { + status = "ok"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&dcan1_pins_default>; + pinctrl-1 = <&dcan1_pins_sleep>; +}; diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi index f1ec22f6ebf4..e5a3d23a3df1 100644 --- a/arch/arm/boot/dts/dra72x.dtsi +++ b/arch/arm/boot/dts/dra72x.dtsi @@ -22,4 +22,9 @@ reg = <0>; }; }; + + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>; + }; }; diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi index a4e8bb9f95c0..10173fab1a15 100644 --- a/arch/arm/boot/dts/dra74x.dtsi +++ b/arch/arm/boot/dts/dra74x.dtsi @@ -38,4 +38,32 @@ reg = <1>; }; }; + + pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = <GIC_SPI DIRECT_IRQ(131) IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI DIRECT_IRQ(132) IRQ_TYPE_LEVEL_HIGH>; + }; + + ocp { + omap_dwc3_4: omap_dwc3_4@48940000 { + compatible = "ti,dwc3"; + ti,hwmods = "usb_otg_ss4"; + reg = <0x48940000 0x10000>; + interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <1>; + utmi-mode = <2>; + ranges; + status = "disabled"; + usb4: usb@48950000 { + compatible = "snps,dwc3"; + reg = <0x48950000 0x17000>; + interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; + tx-fifo-resize; + maximum-speed = "high-speed"; + dr_mode = "otg"; + }; + }; + }; }; diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index 2c05b3f017fa..4bdcbd61ce47 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1042,7 +1042,7 @@ #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&sys_clkin2>; - reg = <0x01a4>; + reg = <0x0164>; }; mlb_clk: mlb_clk { @@ -1084,14 +1084,14 @@ #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&sys_clkin2>; - reg = <0x01d0>; + reg = <0x0168>; }; video2_dpll_clk_mux: video2_dpll_clk_mux { #clock-cells = <0>; compatible = "ti,mux-clock"; clocks = <&sys_clkin1>, <&sys_clkin2>; - reg = <0x01d4>; + reg = <0x016c>; }; wkupaon_iclk_mux: wkupaon_iclk_mux { diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts index 50ccd151091e..667d323e80a3 100644 --- a/arch/arm/boot/dts/emev2-kzm9d.dts +++ b/arch/arm/boot/dts/emev2-kzm9d.dts @@ -25,37 +25,7 @@ chosen { bootargs = "console=ttyS1,115200n81 ignore_loglevel root=/dev/nfs ip=dhcp"; - }; - - reg_1p8v: regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "fixed-1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - - reg_3p3v: regulator@1 { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - lan9220@20000000 { - compatible = "smsc,lan9220", "smsc,lan9115"; - reg = <0x20000000 0x10000>; - phy-mode = "mii"; - interrupt-parent = <&gpio0>; - interrupts = <1 IRQ_TYPE_EDGE_RISING>; - reg-io-width = <4>; - smsc,irq-active-high; - smsc,irq-push-pull; - vddvario-supply = <®_1p8v>; - vdd33a-supply = <®_3p3v>; + stdout-path = &uart1; }; gpio_keys { @@ -92,4 +62,35 @@ gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; }; }; + + reg_1p8v: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_3p3v: regulator@1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + lan9220@20000000 { + compatible = "smsc,lan9220", "smsc,lan9115"; + reg = <0x20000000 0x10000>; + phy-mode = "mii"; + interrupt-parent = <&gpio0>; + interrupts = <1 IRQ_TYPE_EDGE_RISING>; + reg-io-width = <4>; + smsc,irq-active-high; + smsc,irq-push-pull; + vddvario-supply = <®_1p8v>; + vdd33a-supply = <®_3p3v>; + }; }; diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi index 00eeed3721b6..cc7bfe0ba40a 100644 --- a/arch/arm/boot/dts/emev2.dtsi +++ b/arch/arm/boot/dts/emev2.dtsi @@ -55,7 +55,7 @@ <0 121 IRQ_TYPE_LEVEL_HIGH>; }; - smu@e0110000 { + clocks@e0110000 { compatible = "renesas,emev2-smu"; reg = <0xe0110000 0x10000>; #address-cells = <2>; @@ -129,7 +129,7 @@ }; }; - sti@e0180000 { + timer@e0180000 { compatible = "renesas,em-sti"; reg = <0xe0180000 0x54>; interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; @@ -137,7 +137,7 @@ clock-names = "sclk"; }; - uart@e1020000 { + uart0: serial@e1020000 { compatible = "renesas,em-uart"; reg = <0xe1020000 0x38>; interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; @@ -145,7 +145,7 @@ clock-names = "sclk"; }; - uart@e1030000 { + uart1: serial@e1030000 { compatible = "renesas,em-uart"; reg = <0xe1030000 0x38>; interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; @@ -153,7 +153,7 @@ clock-names = "sclk"; }; - uart@e1040000 { + uart2: serial@e1040000 { compatible = "renesas,em-uart"; reg = <0xe1040000 0x38>; interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; @@ -161,7 +161,7 @@ clock-names = "sclk"; }; - uart@e1050000 { + uart3: serial@e1050000 { compatible = "renesas,em-uart"; reg = <0xe1050000 0x38>; interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts new file mode 100644 index 000000000000..24822aa98057 --- /dev/null +++ b/arch/arm/boot/dts/exynos3250-monk.dts @@ -0,0 +1,579 @@ +/* + * Samsung's Exynos3250 based Monk board device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Device tree source file for Samsung's Monk board which is based on + * Samsung Exynos3250 SoC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; +#include "exynos3250.dtsi" +#include <dt-bindings/input/input.h> + +/ { + model = "Samsung Monk board"; + compatible = "samsung,monk", "samsung,exynos3250", "samsung,exynos3"; + + aliases { + i2c7 = &i2c_max77836; + }; + + memory { + reg = <0x40000000 0x1ff00000>; + }; + + firmware@0205F000 { + compatible = "samsung,secure-firmware"; + reg = <0x0205F000 0x1000>; + }; + + gpio_keys { + compatible = "gpio-keys"; + + power_key { + interrupt-parent = <&gpx2>; + interrupts = <7 0>; + gpios = <&gpx2 7 1>; + linux,code = <KEY_POWER>; + label = "power key"; + debounce-interval = <10>; + gpio-key,wakeup; + }; + }; + + vemmc_reg: voltage-regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "V_EMMC_2.8V-fixed"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + gpio = <&gpk0 2 0>; + enable-active-high; + }; + + i2c_max77836: i2c-gpio-0 { + compatible = "i2c-gpio"; + gpios = <&gpd0 2 0>, <&gpd0 3 0>; + #address-cells = <1>; + #size-cells = <0>; + + max77836: subpmic@25 { + compatible = "maxim,max77836"; + interrupt-parent = <&gpx1>; + interrupts = <5 0>; + reg = <0x25>; + wakeup; + + muic: max77836-muic { + compatible = "maxim,max77836-muic"; + }; + + regulators { + compatible = "maxim,max77836-regulator"; + safeout_reg: SAFEOUT { + regulator-name = "SAFEOUT"; + }; + + charger_reg: CHARGER { + regulator-name = "CHARGER"; + regulator-min-microamp = <45000>; + regulator-max-microamp = <475000>; + regulator-boot-on; + }; + + motor_reg: LDO1 { + regulator-name = "MOT_2.7V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <2700000>; + }; + + LDO2 { + regulator-name = "UNUSED_LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + }; + + charger { + compatible = "maxim,max77836-charger"; + + maxim,constant-uvolt = <4350000>; + maxim,fast-charge-uamp = <225000>; + maxim,eoc-uamp = <7500>; + maxim,ovp-uvolt = <6500000>; + }; + }; + }; +}; + +&adc { + vdd-supply = <&ldo3_reg>; + status = "okay"; + assigned-clocks = <&cmu CLK_SCLK_TSADC>; + assigned-clock-rates = <6000000>; + + thermistor-ap { + compatible = "ntc,ncp15wb473"; + pullup-uv = <1800000>; + pullup-ohm = <100000>; + pulldown-ohm = <100000>; + io-channels = <&adc 0>; + }; + + thermistor-battery { + compatible = "ntc,ncp15wb473"; + pullup-uv = <1800000>; + pullup-ohm = <100000>; + pulldown-ohm = <100000>; + io-channels = <&adc 1>; + }; +}; + +&i2c_0 { + #address-cells = <1>; + #size-cells = <0>; + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + status = "okay"; + + s2mps14_pmic@66 { + compatible = "samsung,s2mps14-pmic"; + interrupt-parent = <&gpx0>; + interrupts = <7 0>; + reg = <0x66>; + wakeup; + + s2mps14_osc: clocks { + compatible = "samsung,s2mps14-clk"; + #clock-cells = <1>; + clock-output-names = "s2mps14_ap", "unused", + "s2mps14_bt"; + }; + + regulators { + ldo1_reg: LDO1 { + regulator-name = "VAP_ALIVE_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "VAP_M1_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo3_reg: LDO3 { + regulator-name = "VCC_AP_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo4_reg: LDO4 { + regulator-name = "VAP_AVDD_PLL1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo5_reg: LDO5 { + regulator-name = "VAP_PLL_ISO_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "VAP_MIPI_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + ldo7_reg: LDO7 { + regulator-name = "VAP_AVDD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo8_reg: LDO8 { + regulator-name = "VAP_USB_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + ldo9_reg: LDO9 { + regulator-name = "V_LPDDR_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "UNUSED_LDO10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + ldo11_reg: LDO11 { + regulator-name = "V_EMMC_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + samsung,ext-control-gpios = <&gpk0 2 0>; + }; + + ldo12_reg: LDO12 { + regulator-name = "V_EMMC_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + samsung,ext-control-gpios = <&gpk0 2 0>; + }; + + ldo13_reg: LDO13 { + regulator-name = "VSENSOR_2.85V"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + }; + + ldo14_reg: LDO14 { + regulator-name = "UNUSED_LDO14"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo15_reg: LDO15 { + regulator-name = "TSP_AVDD_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo16_reg: LDO16 { + regulator-name = "LCD_VDD_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo17_reg: LDO17 { + regulator-name = "UNUSED_LDO17"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo18_reg: LDO18 { + regulator-name = "UNUSED_LDO18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo19_reg: LDO19 { + regulator-name = "TSP_VDD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo20_reg: LDO20 { + regulator-name = "LCD_VDD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo21_reg: LDO21 { + regulator-name = "UNUSED_LDO21"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + ldo22_reg: LDO22 { + regulator-name = "UNUSED_LDO22"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + ldo23_reg: LDO23 { + regulator-name = "UNUSED_LDO23"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo24_reg: LDO24 { + regulator-name = "UNUSED_LDO24"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo25_reg: LDO25 { + regulator-name = "UNUSED_LDO25"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + buck1_reg: BUCK1 { + regulator-name = "VAP_MIF_1.0V"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + }; + + buck2_reg: BUCK2 { + regulator-name = "VAP_ARM_1.0V"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + }; + + buck3_reg: BUCK3 { + regulator-name = "VAP_INT3D_1.0V"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "VCC_SUB_1.95V"; + regulator-min-microvolt = <1950000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + }; + + buck5_reg: BUCK5 { + regulator-name = "VCC_SUB_1.35V"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + }; + }; +}; + +&i2c_1 { + #address-cells = <1>; + #size-cells = <0>; + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <400000>; + status = "okay"; + + fuelgauge@36 { + compatible = "maxim,max77836-battery"; + interrupt-parent = <&gpx1>; + interrupts = <2 8>; + reg = <0x36>; + }; +}; + +&i2s2 { + status = "okay"; +}; + +&mshc_0 { + #address-cells = <1>; + #size-cells = <0>; + num-slots = <1>; + broken-cd; + non-removable; + cap-mmc-highspeed; + desc-num = <4>; + mmc-hs200-1_8v; + card-detect-delay = <200>; + vmmc-supply = <&vemmc_reg>; + clock-frequency = <100000000>; + clock-freq-min-max = <400000 100000000>; + samsung,dw-mshc-ciu-div = <1>; + samsung,dw-mshc-sdr-timing = <0 1>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; + bus-width = <8>; + status = "okay"; +}; + +&serial_0 { + assigned-clocks = <&cmu CLK_SCLK_UART0>; + assigned-clock-rates = <100000000>; + status = "okay"; +}; + +&serial_1 { + status = "okay"; +}; + +&tmu { + vtmu-supply = <&ldo7_reg>; + status = "okay"; +}; + +&rtc { + clocks = <&cmu CLK_RTC>, <&s2mps14_osc 0>; + clock-names = "rtc", "rtc_src"; + status = "okay"; +}; + +&xusbxti { + clock-frequency = <24000000>; +}; + +&pinctrl_0 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep0>; + + sleep0: sleep-state { + PIN_SLP(gpa0-0, INPUT, DOWN); + PIN_SLP(gpa0-1, INPUT, DOWN); + PIN_SLP(gpa0-2, INPUT, DOWN); + PIN_SLP(gpa0-3, INPUT, DOWN); + PIN_SLP(gpa0-4, INPUT, DOWN); + PIN_SLP(gpa0-5, INPUT, DOWN); + PIN_SLP(gpa0-6, INPUT, DOWN); + PIN_SLP(gpa0-7, INPUT, DOWN); + + PIN_SLP(gpa1-0, INPUT, DOWN); + PIN_SLP(gpa1-1, INPUT, DOWN); + PIN_SLP(gpa1-2, INPUT, DOWN); + PIN_SLP(gpa1-3, INPUT, DOWN); + PIN_SLP(gpa1-4, INPUT, DOWN); + PIN_SLP(gpa1-5, INPUT, DOWN); + + PIN_SLP(gpb-0, PREV, NONE); + PIN_SLP(gpb-1, PREV, NONE); + PIN_SLP(gpb-2, PREV, NONE); + PIN_SLP(gpb-3, PREV, NONE); + PIN_SLP(gpb-4, INPUT, DOWN); + PIN_SLP(gpb-5, INPUT, DOWN); + PIN_SLP(gpb-6, INPUT, DOWN); + PIN_SLP(gpb-7, INPUT, DOWN); + + PIN_SLP(gpc0-0, INPUT, DOWN); + PIN_SLP(gpc0-1, INPUT, DOWN); + PIN_SLP(gpc0-2, INPUT, DOWN); + PIN_SLP(gpc0-3, INPUT, DOWN); + PIN_SLP(gpc0-4, INPUT, DOWN); + + PIN_SLP(gpc1-0, INPUT, DOWN); + PIN_SLP(gpc1-1, INPUT, DOWN); + PIN_SLP(gpc1-2, INPUT, DOWN); + PIN_SLP(gpc1-3, INPUT, DOWN); + PIN_SLP(gpc1-4, INPUT, DOWN); + + PIN_SLP(gpd0-0, INPUT, DOWN); + PIN_SLP(gpd0-1, INPUT, DOWN); + PIN_SLP(gpd0-2, INPUT, NONE); + PIN_SLP(gpd0-3, INPUT, NONE); + + PIN_SLP(gpd1-0, INPUT, NONE); + PIN_SLP(gpd1-1, INPUT, NONE); + PIN_SLP(gpd1-2, INPUT, NONE); + PIN_SLP(gpd1-3, INPUT, NONE); + }; +}; + +&pinctrl_1 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep1>; + + sleep1: sleep-state { + PIN_SLP(gpe0-0, PREV, NONE); + PIN_SLP(gpe0-1, PREV, NONE); + PIN_SLP(gpe0-2, INPUT, DOWN); + PIN_SLP(gpe0-3, INPUT, DOWN); + PIN_SLP(gpe0-4, PREV, NONE); + PIN_SLP(gpe0-5, INPUT, DOWN); + PIN_SLP(gpe0-6, INPUT, DOWN); + PIN_SLP(gpe0-7, INPUT, DOWN); + + PIN_SLP(gpe1-0, INPUT, DOWN); + PIN_SLP(gpe1-1, PREV, NONE); + PIN_SLP(gpe1-2, INPUT, DOWN); + PIN_SLP(gpe1-3, INPUT, DOWN); + PIN_SLP(gpe1-4, INPUT, DOWN); + PIN_SLP(gpe1-5, INPUT, DOWN); + PIN_SLP(gpe1-6, INPUT, DOWN); + PIN_SLP(gpe1-7, INPUT, NONE); + + PIN_SLP(gpe2-0, INPUT, NONE); + PIN_SLP(gpe2-1, INPUT, NONE); + PIN_SLP(gpe2-2, INPUT, NONE); + + PIN_SLP(gpk0-0, INPUT, DOWN); + PIN_SLP(gpk0-1, INPUT, DOWN); + PIN_SLP(gpk0-2, OUT0, NONE); + PIN_SLP(gpk0-3, INPUT, DOWN); + PIN_SLP(gpk0-4, INPUT, DOWN); + PIN_SLP(gpk0-5, INPUT, DOWN); + PIN_SLP(gpk0-6, INPUT, DOWN); + PIN_SLP(gpk0-7, INPUT, DOWN); + + PIN_SLP(gpk1-0, PREV, NONE); + PIN_SLP(gpk1-1, PREV, NONE); + PIN_SLP(gpk1-2, INPUT, DOWN); + PIN_SLP(gpk1-3, PREV, NONE); + PIN_SLP(gpk1-4, PREV, NONE); + PIN_SLP(gpk1-5, PREV, NONE); + PIN_SLP(gpk1-6, PREV, NONE); + + PIN_SLP(gpk2-0, INPUT, DOWN); + PIN_SLP(gpk2-1, INPUT, DOWN); + PIN_SLP(gpk2-2, INPUT, DOWN); + PIN_SLP(gpk2-3, INPUT, DOWN); + PIN_SLP(gpk2-4, INPUT, DOWN); + PIN_SLP(gpk2-5, INPUT, DOWN); + PIN_SLP(gpk2-6, INPUT, DOWN); + + PIN_SLP(gpl0-0, INPUT, DOWN); + PIN_SLP(gpl0-1, INPUT, DOWN); + PIN_SLP(gpl0-2, INPUT, DOWN); + PIN_SLP(gpl0-3, INPUT, DOWN); + + PIN_SLP(gpm0-0, INPUT, DOWN); + PIN_SLP(gpm0-1, INPUT, DOWN); + PIN_SLP(gpm0-2, INPUT, DOWN); + PIN_SLP(gpm0-3, INPUT, DOWN); + PIN_SLP(gpm0-4, INPUT, DOWN); + PIN_SLP(gpm0-5, INPUT, DOWN); + PIN_SLP(gpm0-6, INPUT, DOWN); + PIN_SLP(gpm0-7, INPUT, DOWN); + + PIN_SLP(gpm1-0, INPUT, DOWN); + PIN_SLP(gpm1-1, INPUT, DOWN); + PIN_SLP(gpm1-2, INPUT, DOWN); + PIN_SLP(gpm1-3, INPUT, DOWN); + PIN_SLP(gpm1-4, INPUT, DOWN); + PIN_SLP(gpm1-5, INPUT, DOWN); + PIN_SLP(gpm1-6, INPUT, DOWN); + + PIN_SLP(gpm2-0, INPUT, DOWN); + PIN_SLP(gpm2-1, INPUT, DOWN); + PIN_SLP(gpm2-2, INPUT, DOWN); + PIN_SLP(gpm2-3, INPUT, DOWN); + PIN_SLP(gpm2-4, INPUT, DOWN); + + PIN_SLP(gpm3-0, INPUT, DOWN); + PIN_SLP(gpm3-1, INPUT, DOWN); + PIN_SLP(gpm3-2, INPUT, DOWN); + PIN_SLP(gpm3-3, INPUT, DOWN); + PIN_SLP(gpm3-4, INPUT, DOWN); + PIN_SLP(gpm3-5, INPUT, DOWN); + PIN_SLP(gpm3-6, INPUT, DOWN); + PIN_SLP(gpm3-7, INPUT, DOWN); + + PIN_SLP(gpm4-0, INPUT, DOWN); + PIN_SLP(gpm4-1, INPUT, DOWN); + PIN_SLP(gpm4-2, INPUT, DOWN); + PIN_SLP(gpm4-3, INPUT, DOWN); + PIN_SLP(gpm4-4, INPUT, DOWN); + PIN_SLP(gpm4-5, INPUT, DOWN); + PIN_SLP(gpm4-6, INPUT, DOWN); + PIN_SLP(gpm4-7, INPUT, DOWN); + }; +}; diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi index 47b92c150f4e..5ab81c39e2c9 100644 --- a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi @@ -12,6 +12,22 @@ * published by the Free Software Foundation. */ +#define PIN_PULL_NONE 0 +#define PIN_PULL_DOWN 1 +#define PIN_PULL_UP 3 + +#define PIN_PDN_OUT0 0 +#define PIN_PDN_OUT1 1 +#define PIN_PDN_INPUT 2 +#define PIN_PDN_PREV 3 + +#define PIN_SLP(_pin, _mode, _pull) \ + _pin { \ + samsung,pins = #_pin; \ + samsung,pin-con-pdn = <PIN_PDN_ ##_mode>; \ + samsung,pin-pud-pdn = <PIN_PULL_ ##_pull>; \ + } + &pinctrl_0 { gpa0: gpa0 { gpio-controller; diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts new file mode 100644 index 000000000000..80aa8b4c4a3d --- /dev/null +++ b/arch/arm/boot/dts/exynos3250-rinato.dts @@ -0,0 +1,682 @@ +/* + * Samsung's Exynos3250 based Rinato board device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Device tree source file for Samsung's Rinato board which is based on + * Samsung Exynos3250 SoC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; +#include "exynos3250.dtsi" +#include <dt-bindings/input/input.h> + +/ { + model = "Samsung Rinato board"; + compatible = "samsung,rinato", "samsung,exynos3250", "samsung,exynos3"; + + aliases { + i2c7 = &i2c_max77836; + }; + + memory { + reg = <0x40000000 0x1ff00000>; + }; + + firmware@0205F000 { + compatible = "samsung,secure-firmware"; + reg = <0x0205F000 0x1000>; + }; + + gpio_keys { + compatible = "gpio-keys"; + + power_key { + interrupt-parent = <&gpx2>; + interrupts = <7 0>; + gpios = <&gpx2 7 1>; + linux,code = <KEY_POWER>; + label = "power key"; + debounce-interval = <10>; + gpio-key,wakeup; + }; + }; + + i2c_max77836: i2c-gpio-0 { + compatible = "i2c-gpio"; + gpios = <&gpd0 2 0>, <&gpd0 3 0>; + #address-cells = <1>; + #size-cells = <0>; + + max77836: subpmic@25 { + compatible = "maxim,max77836"; + interrupt-parent = <&gpx1>; + interrupts = <5 0>; + reg = <0x25>; + wakeup; + + muic: max77836-muic { + compatible = "maxim,max77836-muic"; + }; + + regulators { + compatible = "maxim,max77836-regulator"; + safeout_reg: SAFEOUT { + regulator-name = "SAFEOUT"; + }; + + charger_reg: CHARGER { + regulator-name = "CHARGER"; + regulator-min-microamp = <45000>; + regulator-max-microamp = <475000>; + regulator-boot-on; + }; + + motor_reg: LDO1 { + regulator-name = "MOT_2.7V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <2700000>; + }; + + LDO2 { + regulator-name = "UNUSED_LDO2"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + }; + + charger { + compatible = "maxim,max77836-charger"; + + maxim,constant-uvolt = <4350000>; + maxim,fast-charge-uamp = <225000>; + maxim,eoc-uamp = <7500>; + maxim,ovp-uvolt = <6500000>; + }; + }; + }; +}; + +&adc { + vdd-supply = <&ldo3_reg>; + status = "okay"; + assigned-clocks = <&cmu CLK_SCLK_TSADC>; + assigned-clock-rates = <6000000>; + + thermistor-ap { + compatible = "ntc,ncp15wb473"; + pullup-uv = <1800000>; + pullup-ohm = <100000>; + pulldown-ohm = <100000>; + io-channels = <&adc 0>; + }; + + thermistor-battery { + compatible = "ntc,ncp15wb473"; + pullup-uv = <1800000>; + pullup-ohm = <100000>; + pulldown-ohm = <100000>; + io-channels = <&adc 1>; + }; +}; + +&i2c_0 { + #address-cells = <1>; + #size-cells = <0>; + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + status = "okay"; + + s2mps14_pmic@66 { + compatible = "samsung,s2mps14-pmic"; + interrupt-parent = <&gpx0>; + interrupts = <7 0>; + reg = <0x66>; + wakeup; + + s2mps14_osc: clocks { + compatible = "samsung,s2mps14-clk"; + #clock-cells = <1>; + clock-output-names = "s2mps14_ap", "unused", + "s2mps14_bt"; + }; + + regulators { + ldo1_reg: LDO1 { + regulator-name = "VAP_ALIVE_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo2_reg: LDO2 { + regulator-name = "VAP_M1_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo3_reg: LDO3 { + regulator-name = "VCC_AP_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo4_reg: LDO4 { + regulator-name = "VAP_AVDD_PLL1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo5_reg: LDO5 { + regulator-name = "VAP_PLL_ISO_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo6_reg: LDO6 { + regulator-name = "VAP_VMIPI_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo7_reg: LDO7 { + regulator-name = "VAP_AVDD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo8_reg: LDO8 { + regulator-name = "VAP_USB_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo9_reg: LDO9 { + regulator-name = "V_LPDDR_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo10_reg: LDO10 { + regulator-name = "UNUSED_LDO10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo11_reg: LDO11 { + regulator-name = "V_EMMC_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + samsung,ext-control-gpios = <&gpk0 2 0>; + }; + + ldo12_reg: LDO12 { + regulator-name = "V_EMMC_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + samsung,ext-control-gpios = <&gpk0 2 0>; + }; + + ldo13_reg: LDO13 { + regulator-name = "CAM_AVDD_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo14_reg: LDO14 { + regulator-name = "UNUSED_LDO14"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo15_reg: LDO15 { + regulator-name = "TSP_AVDD_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo16_reg: LDO16 { + regulator-name = "LCD_VDD_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo17_reg: LDO17 { + regulator-name = "V_IRLED_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo18_reg: LDO18 { + regulator-name = "CAM_AF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo19_reg: LDO19 { + regulator-name = "TSP_VDD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo20_reg: LDO20 { + regulator-name = "LCD_VDD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo21_reg: LDO21 { + regulator-name = "CAM_IO_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo22_reg: LDO22 { + regulator-name = "CAM_DVDD_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo23_reg: LDO23 { + regulator-name = "HRM_VCC_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo24_reg: LDO24 { + regulator-name = "HRM_VCC_3.3V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo25_reg: LDO25 { + regulator-name = "UNUSED_LDO25"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck1_reg: BUCK1 { + regulator-name = "VAP_MIF_1.0V"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck2_reg: BUCK2 { + regulator-name = "VAP_ARM_1.0V"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1150000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck3_reg: BUCK3 { + regulator-name = "VAP_INT3D_1.0V"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck4_reg: BUCK4 { + regulator-name = "VCC_SUB_1.95V"; + regulator-min-microvolt = <1950000>; + regulator-max-microvolt = <1950000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + buck5_reg: BUCK5 { + regulator-name = "VCC_SUB_1.35V"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + }; + }; +}; + +&i2c_1 { + #address-cells = <1>; + #size-cells = <0>; + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <400000>; + status = "okay"; + + fuelgauge@36 { + compatible = "maxim,max77836-battery"; + interrupt-parent = <&gpx1>; + interrupts = <2 8>; + reg = <0x36>; + }; +}; + +&i2s2 { + status = "okay"; +}; + +&mfc { + status = "okay"; +}; + +&mshc_0 { + #address-cells = <1>; + #size-cells = <0>; + num-slots = <1>; + broken-cd; + non-removable; + cap-mmc-highspeed; + desc-num = <4>; + mmc-hs200-1_8v; + card-detect-delay = <200>; + vmmc-supply = <&ldo12_reg>; + clock-frequency = <100000000>; + clock-freq-min-max = <400000 100000000>; + samsung,dw-mshc-ciu-div = <1>; + samsung,dw-mshc-sdr-timing = <0 1>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; + bus-width = <8>; + status = "okay"; +}; + +&serial_0 { + assigned-clocks = <&cmu CLK_SCLK_UART0>; + assigned-clock-rates = <100000000>; + status = "okay"; +}; + +&serial_1 { + status = "okay"; +}; + +&tmu { + vtmu-supply = <&ldo7_reg>; + status = "okay"; +}; + +&rtc { + clocks = <&cmu CLK_RTC>, <&s2mps14_osc 0>; + clock-names = "rtc", "rtc_src"; + status = "okay"; +}; + +&xusbxti { + clock-frequency = <24000000>; +}; + +&pinctrl_0 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep0>; + + sleep0: sleep-state { + PIN_SLP(gpa0-0, INPUT, DOWN); + PIN_SLP(gpa0-1, INPUT, DOWN); + PIN_SLP(gpa0-2, INPUT, DOWN); + PIN_SLP(gpa0-3, INPUT, DOWN); + PIN_SLP(gpa0-4, INPUT, DOWN); + PIN_SLP(gpa0-5, INPUT, DOWN); + PIN_SLP(gpa0-6, INPUT, DOWN); + PIN_SLP(gpa0-7, INPUT, DOWN); + + PIN_SLP(gpa1-0, INPUT, DOWN); + PIN_SLP(gpa1-1, INPUT, DOWN); + PIN_SLP(gpa1-2, INPUT, DOWN); + PIN_SLP(gpa1-3, INPUT, DOWN); + PIN_SLP(gpa1-4, INPUT, DOWN); + PIN_SLP(gpa1-5, INPUT, DOWN); + + PIN_SLP(gpb-0, PREV, NONE); + PIN_SLP(gpb-1, PREV, NONE); + PIN_SLP(gpb-2, PREV, NONE); + PIN_SLP(gpb-3, PREV, NONE); + PIN_SLP(gpb-4, INPUT, DOWN); + PIN_SLP(gpb-5, INPUT, DOWN); + PIN_SLP(gpb-6, INPUT, DOWN); + PIN_SLP(gpb-7, INPUT, DOWN); + + PIN_SLP(gpc0-0, INPUT, DOWN); + PIN_SLP(gpc0-1, INPUT, DOWN); + PIN_SLP(gpc0-2, INPUT, DOWN); + PIN_SLP(gpc0-3, INPUT, DOWN); + PIN_SLP(gpc0-4, INPUT, DOWN); + + PIN_SLP(gpc1-0, INPUT, DOWN); + PIN_SLP(gpc1-1, INPUT, DOWN); + PIN_SLP(gpc1-2, INPUT, DOWN); + PIN_SLP(gpc1-3, INPUT, DOWN); + PIN_SLP(gpc1-4, INPUT, DOWN); + + PIN_SLP(gpd0-0, INPUT, DOWN); + PIN_SLP(gpd0-1, INPUT, DOWN); + PIN_SLP(gpd0-2, INPUT, NONE); + PIN_SLP(gpd0-3, INPUT, NONE); + + PIN_SLP(gpd1-0, INPUT, NONE); + PIN_SLP(gpd1-1, INPUT, NONE); + PIN_SLP(gpd1-2, INPUT, NONE); + PIN_SLP(gpd1-3, INPUT, NONE); + }; +}; + +&pinctrl_1 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep1>; + + sleep1: sleep-state { + PIN_SLP(gpe0-0, PREV, NONE); + PIN_SLP(gpe0-1, PREV, NONE); + PIN_SLP(gpe0-2, INPUT, DOWN); + PIN_SLP(gpe0-3, INPUT, UP); + PIN_SLP(gpe0-4, INPUT, DOWN); + PIN_SLP(gpe0-5, INPUT, DOWN); + PIN_SLP(gpe0-6, INPUT, DOWN); + PIN_SLP(gpe0-7, INPUT, DOWN); + + PIN_SLP(gpe1-0, INPUT, DOWN); + PIN_SLP(gpe1-1, PREV, NONE); + PIN_SLP(gpe1-2, INPUT, DOWN); + PIN_SLP(gpe1-3, INPUT, DOWN); + PIN_SLP(gpe1-4, INPUT, DOWN); + PIN_SLP(gpe1-5, INPUT, DOWN); + PIN_SLP(gpe1-6, INPUT, DOWN); + PIN_SLP(gpe1-7, INPUT, NONE); + + PIN_SLP(gpe2-0, INPUT, NONE); + PIN_SLP(gpe2-1, INPUT, NONE); + PIN_SLP(gpe2-2, INPUT, NONE); + + PIN_SLP(gpk0-0, INPUT, DOWN); + PIN_SLP(gpk0-1, INPUT, DOWN); + PIN_SLP(gpk0-2, OUT0, NONE); + PIN_SLP(gpk0-3, INPUT, DOWN); + PIN_SLP(gpk0-4, INPUT, DOWN); + PIN_SLP(gpk0-5, INPUT, DOWN); + PIN_SLP(gpk0-6, INPUT, DOWN); + PIN_SLP(gpk0-7, INPUT, DOWN); + + PIN_SLP(gpk1-0, INPUT, DOWN); + PIN_SLP(gpk1-1, INPUT, DOWN); + PIN_SLP(gpk1-2, INPUT, DOWN); + PIN_SLP(gpk1-3, INPUT, DOWN); + PIN_SLP(gpk1-4, INPUT, DOWN); + PIN_SLP(gpk1-5, INPUT, DOWN); + PIN_SLP(gpk1-6, INPUT, DOWN); + + PIN_SLP(gpk2-0, INPUT, DOWN); + PIN_SLP(gpk2-1, INPUT, DOWN); + PIN_SLP(gpk2-2, INPUT, DOWN); + PIN_SLP(gpk2-3, INPUT, DOWN); + PIN_SLP(gpk2-4, INPUT, DOWN); + PIN_SLP(gpk2-5, INPUT, DOWN); + PIN_SLP(gpk2-6, INPUT, DOWN); + + PIN_SLP(gpl0-0, INPUT, DOWN); + PIN_SLP(gpl0-1, INPUT, DOWN); + PIN_SLP(gpl0-2, INPUT, DOWN); + PIN_SLP(gpl0-3, INPUT, DOWN); + + PIN_SLP(gpm0-0, INPUT, DOWN); + PIN_SLP(gpm0-1, INPUT, DOWN); + PIN_SLP(gpm0-2, INPUT, DOWN); + PIN_SLP(gpm0-3, INPUT, DOWN); + PIN_SLP(gpm0-4, INPUT, DOWN); + PIN_SLP(gpm0-5, INPUT, DOWN); + PIN_SLP(gpm0-6, INPUT, DOWN); + PIN_SLP(gpm0-7, INPUT, DOWN); + + PIN_SLP(gpm1-0, INPUT, DOWN); + PIN_SLP(gpm1-1, INPUT, DOWN); + PIN_SLP(gpm1-2, INPUT, DOWN); + PIN_SLP(gpm1-3, INPUT, DOWN); + PIN_SLP(gpm1-4, INPUT, DOWN); + PIN_SLP(gpm1-5, INPUT, DOWN); + PIN_SLP(gpm1-6, INPUT, DOWN); + + PIN_SLP(gpm2-0, INPUT, DOWN); + PIN_SLP(gpm2-1, INPUT, DOWN); + PIN_SLP(gpm2-2, INPUT, DOWN); + PIN_SLP(gpm2-3, INPUT, DOWN); + PIN_SLP(gpm2-4, INPUT, DOWN); + + PIN_SLP(gpm3-0, INPUT, DOWN); + PIN_SLP(gpm3-1, INPUT, DOWN); + PIN_SLP(gpm3-2, INPUT, DOWN); + PIN_SLP(gpm3-3, INPUT, DOWN); + PIN_SLP(gpm3-4, INPUT, DOWN); + PIN_SLP(gpm3-5, INPUT, DOWN); + PIN_SLP(gpm3-6, INPUT, DOWN); + PIN_SLP(gpm3-7, INPUT, DOWN); + + PIN_SLP(gpm4-0, INPUT, DOWN); + PIN_SLP(gpm4-1, INPUT, DOWN); + PIN_SLP(gpm4-2, INPUT, DOWN); + PIN_SLP(gpm4-3, INPUT, DOWN); + PIN_SLP(gpm4-4, INPUT, DOWN); + PIN_SLP(gpm4-5, INPUT, DOWN); + PIN_SLP(gpm4-6, INPUT, DOWN); + PIN_SLP(gpm4-7, INPUT, DOWN); + }; +}; diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index 1d52de6370d5..22465494b796 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -132,6 +132,12 @@ reg = <0x10020000 0x4000>; }; + mipi_phy: video-phy@10020710 { + compatible = "samsung,s5pv210-mipi-video-phy"; + reg = <0x10020710 8>; + #phy-cells = <1>; + }; + pd_cam: cam-power-domain@10023C00 { compatible = "samsung,exynos4210-pd"; reg = <0x10023C00 0x20>; @@ -163,8 +169,14 @@ #clock-cells = <1>; }; + cmu_dmc: clock-controller@105C0000 { + compatible = "samsung,exynos3250-cmu-dmc"; + reg = <0x105C0000 0x2000>; + #clock-cells = <1>; + }; + rtc: rtc@10070000 { - compatible = "samsung,s3c6410-rtc"; + compatible = "samsung,exynos3250-rtc"; reg = <0x10070000 0x100>; interrupts = <0 73 0>, <0 74 0>; status = "disabled"; @@ -216,6 +228,33 @@ interrupts = <0 240 0>; }; + fimd: fimd@11c00000 { + compatible = "samsung,exynos3250-fimd"; + reg = <0x11c00000 0x30000>; + interrupt-names = "fifo", "vsync", "lcd_sys"; + interrupts = <0 84 0>, <0 85 0>, <0 86 0>; + clocks = <&cmu CLK_SCLK_FIMD0>, <&cmu CLK_FIMD0>; + clock-names = "sclk_fimd", "fimd"; + samsung,power-domain = <&pd_lcd0>; + samsung,sysreg = <&sys_reg>; + status = "disabled"; + }; + + dsi_0: dsi@11C80000 { + compatible = "samsung,exynos3250-mipi-dsi"; + reg = <0x11C80000 0x10000>; + interrupts = <0 83 0>; + samsung,phy-type = <0>; + samsung,power-domain = <&pd_lcd0>; + phys = <&mipi_phy 1>; + phy-names = "dsim"; + clocks = <&cmu CLK_DSIM0>, <&cmu CLK_SCLK_MIPI0>; + clock-names = "bus_clk", "pll_clk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + mshc_0: mshc@12510000 { compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12510000 0x1000>; @@ -272,12 +311,23 @@ adc: adc@126C0000 { compatible = "samsung,exynos3250-adc", "samsung,exynos-adc-v2"; - reg = <0x126C0000 0x100>, <0x10020718 0x4>; + reg = <0x126C0000 0x100>; interrupts = <0 137 0>; clock-names = "adc", "sclk"; clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>; #io-channel-cells = <1>; io-channel-ranges; + samsung,syscon-phandle = <&pmu_system_controller>; + status = "disabled"; + }; + + mfc: codec@13400000 { + compatible = "samsung,mfc-v7"; + reg = <0x13400000 0x10000>; + interrupts = <0 102 0>; + clock-names = "mfc", "sclk_mfc"; + clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>; + samsung,power-domain = <&pd_mfc>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index e0278ecbc816..b8168f1f8139 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -392,8 +392,8 @@ reg = <0x13400000 0x10000>; interrupts = <0 94 0>; samsung,power-domain = <&pd_mfc>; - clocks = <&clock CLK_MFC>; - clock-names = "mfc"; + clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>; + clock-names = "mfc", "sclk_mfc"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts index f516da9e8b3a..720836205546 100644 --- a/arch/arm/boot/dts/exynos4210-trats.dts +++ b/arch/arm/boot/dts/exynos4210-trats.dts @@ -431,18 +431,34 @@ fimc_0: fimc@11800000 { status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC0>, + <&clock CLK_SCLK_FIMC0>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; }; fimc_1: fimc@11810000 { status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC1>, + <&clock CLK_SCLK_FIMC1>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; }; fimc_2: fimc@11820000 { status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC2>, + <&clock CLK_SCLK_FIMC2>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; }; fimc_3: fimc@11830000 { status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC3>, + <&clock CLK_SCLK_FIMC3>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; }; }; }; diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts index d50eb3aa708e..aaf0cae4f5e8 100644 --- a/arch/arm/boot/dts/exynos4210-universal_c210.dts +++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts @@ -473,18 +473,34 @@ fimc_0: fimc@11800000 { status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC0>, + <&clock CLK_SCLK_FIMC0>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; }; fimc_1: fimc@11810000 { status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC1>, + <&clock CLK_SCLK_FIMC1>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; }; fimc_2: fimc@11820000 { status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC2>, + <&clock CLK_SCLK_FIMC2>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; }; fimc_3: fimc@11830000 { status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC3>, + <&clock CLK_SCLK_FIMC3>; + assigned-clock-parents = <&clock CLK_SCLK_MPLL>; + assigned-clock-rates = <0>, <160000000>; }; }; }; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 807bb5bf91fc..bcc9e63c8070 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -31,6 +31,23 @@ pinctrl2 = &pinctrl_2; }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@900 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x900>; + }; + + cpu@901 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0x901>; + }; + }; + pmu_system_controller: system-controller@10020000 { clock-names = "clkout0", "clkout1", "clkout2", "clkout3", "clkout4", "clkout8", "clkout9"; diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi index 3c00e6ec9302..dd0a43ec56da 100644 --- a/arch/arm/boot/dts/exynos4212.dtsi +++ b/arch/arm/boot/dts/exynos4212.dtsi @@ -22,6 +22,23 @@ / { compatible = "samsung,exynos4212", "samsung,exynos4"; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@A00 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xA00>; + }; + + cpu@A01 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xA01>; + }; + }; + combiner: interrupt-controller@10440000 { samsung,combiner-nr = <18>; }; diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index adadaf97ac01..3fbf588682b9 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -45,6 +45,16 @@ compatible = "samsung,odroidx2-audio"; samsung,i2s-controller = <&i2s0>; samsung,audio-codec = <&max98090>; + assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>, + <&clock_audss EXYNOS_MOUT_I2S>, + <&clock_audss EXYNOS_DOUT_SRP>, + <&clock_audss EXYNOS_DOUT_AUD_BUS>; + assigned-clock-parents = <&clock CLK_FOUT_EPLL>, + <&clock_audss EXYNOS_MOUT_AUDSS>; + assigned-clock-rates = <0>, + <0>, + <192000000>, + <19200000>; }; mmc@12550000 { @@ -54,17 +64,13 @@ status = "okay"; num-slots = <1>; - supports-highspeed; broken-cd; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-ddr-timing = <1 2>; - - slot@0 { - reg = <0>; - bus-width = <8>; - }; + bus-width = <8>; + cap-mmc-highspeed; }; watchdog@10060000 { @@ -86,18 +92,34 @@ fimc_0: fimc@11800000 { status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC0>, + <&clock CLK_SCLK_FIMC0>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; }; fimc_1: fimc@11810000 { status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC1>, + <&clock CLK_SCLK_FIMC1>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; }; fimc_2: fimc@11820000 { status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC2>, + <&clock CLK_SCLK_FIMC2>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; }; fimc_3: fimc@11830000 { status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC3>, + <&clock CLK_SCLK_FIMC3>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; }; }; diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index e925c9fbfb07..de15114fd07c 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -137,17 +137,13 @@ status = "okay"; num-slots = <1>; - supports-highspeed; broken-cd; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-ddr-timing = <1 2>; - - slot@0 { - reg = <0>; - bus-width = <8>; - }; + bus-width = <8>; + cap-mmc-highspeed; }; codec@13400000 { diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts index 11967f4561e0..29231b452643 100644 --- a/arch/arm/boot/dts/exynos4412-trats2.dts +++ b/arch/arm/boot/dts/exynos4412-trats2.dts @@ -14,6 +14,7 @@ /dts-v1/; #include "exynos4412.dtsi" +#include <dt-bindings/gpio/gpio.h> / { model = "Samsung Trats 2 based on Exynos4412"; @@ -22,6 +23,7 @@ aliases { i2c9 = &i2c_ak8975; i2c10 = &i2c_cm36651; + i2c11 = &i2c_max77693; }; memory { @@ -399,8 +401,6 @@ regulator-name = "VMEM_VDD_2.8V"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-mem-off; }; ldo23_reg: ldo23 { @@ -503,8 +503,6 @@ regulator-name = "VMEM_VDDF_3.0V"; regulator-min-microvolt = <2850000>; regulator-max-microvolt = <2850000>; - regulator-always-on; - regulator-mem-off; }; buck9_reg: buck9 { @@ -518,9 +516,44 @@ }; }; + i2c_max77693: i2c-gpio-1 { + compatible = "i2c-gpio"; + gpios = <&gpm2 0 GPIO_ACTIVE_HIGH>, <&gpm2 1 GPIO_ACTIVE_HIGH>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + max77693@66 { + compatible = "maxim,max77693"; + interrupt-parent = <&gpx1>; + interrupts = <5 2>; + reg = <0x66>; + + regulators { + esafeout1_reg: ESAFEOUT1@1 { + regulator-name = "ESAFEOUT1"; + }; + esafeout2_reg: ESAFEOUT2@2 { + regulator-name = "ESAFEOUT2"; + }; + charger_reg: CHARGER@0 { + regulator-name = "CHARGER"; + regulator-min-microamp = <60000>; + regulator-max-microamp = <2580000>; + }; + }; + + max77693_haptic { + compatible = "maxim,max77693-haptic"; + haptic-supply = <&ldo26_reg>; + pwms = <&pwm 0 38022 0>; + }; + }; + }; + mmc@12550000 { num-slots = <1>; - supports-highspeed; broken-cd; non-removable; card-detect-delay = <200>; @@ -532,11 +565,18 @@ pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; pinctrl-names = "default"; status = "okay"; + bus-width = <8>; + cap-mmc-highspeed; + }; - slot@0 { - reg = <0>; - bus-width = <8>; - }; + sdhci@12530000 { + bus-width = <4>; + cd-gpios = <&gpx3 4 0>; + cd-inverted; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>; + pinctrl-names = "default"; + vmmc-supply = <&ldo21_reg>; + status = "okay"; }; serial@13800000 { @@ -555,6 +595,11 @@ status = "okay"; }; + tmu@100C0000 { + vtmu-supply = <&ldo10_reg>; + status = "okay"; + }; + i2c_ak8975: i2c-gpio-0 { compatible = "i2c-gpio"; gpios = <&gpy2 4 0>, <&gpy2 5 0>; @@ -602,6 +647,13 @@ }; }; + pwm: pwm@139D0000 { + pinctrl-0 = <&pwm0_out>; + pinctrl-names = "default"; + samsung,pwm-outputs = <0>; + status = "okay"; + }; + dsi_0: dsi@11C80000 { vddcore-supply = <&ldo8_reg>; vddio-supply = <&ldo10_reg>; @@ -667,28 +719,51 @@ pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>; pinctrl-names = "default"; status = "okay"; + assigned-clocks = <&clock CLK_MOUT_CAM0>, + <&clock CLK_MOUT_CAM1>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>, + <&clock CLK_MOUT_MPLL_USER_T>; fimc_0: fimc@11800000 { status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC0>, + <&clock CLK_SCLK_FIMC0>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; }; fimc_1: fimc@11810000 { status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC1>, + <&clock CLK_SCLK_FIMC1>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; }; fimc_2: fimc@11820000 { status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC2>, + <&clock CLK_SCLK_FIMC2>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; }; fimc_3: fimc@11830000 { status = "okay"; + assigned-clocks = <&clock CLK_MOUT_FIMC3>, + <&clock CLK_SCLK_FIMC3>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; }; csis_0: csis@11880000 { status = "okay"; vddcore-supply = <&ldo8_reg>; vddio-supply = <&ldo10_reg>; - clock-frequency = <176000000>; + assigned-clocks = <&clock CLK_MOUT_CSIS0>, + <&clock CLK_SCLK_CSIS0>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; /* Camera C (3) MIPI CSI-2 (CSIS0) */ port@3 { @@ -702,10 +777,13 @@ }; csis_1: csis@11890000 { + status = "okay"; vddcore-supply = <&ldo8_reg>; vddio-supply = <&ldo10_reg>; - clock-frequency = <160000000>; - status = "okay"; + assigned-clocks = <&clock CLK_MOUT_CSIS1>, + <&clock CLK_SCLK_CSIS1>; + assigned-clock-parents = <&clock CLK_MOUT_MPLL_USER_T>; + assigned-clock-rates = <0>, <176000000>; /* Camera D (4) MIPI CSI-2 (CSIS1) */ port@4 { @@ -786,3 +864,319 @@ io-channels = <&adc 2>; /* Battery temperature */ }; }; + +&pinctrl_0 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep0>; + + sleep0: sleep-states { + PIN_SLP(gpa0-0, INPUT, NONE); + PIN_SLP(gpa0-1, OUT0, NONE); + PIN_SLP(gpa0-2, INPUT, NONE); + PIN_SLP(gpa0-3, INPUT, UP); + PIN_SLP(gpa0-4, INPUT, NONE); + PIN_SLP(gpa0-5, INPUT, DOWN); + PIN_SLP(gpa0-6, INPUT, DOWN); + PIN_SLP(gpa0-7, INPUT, UP); + + PIN_SLP(gpa1-0, INPUT, DOWN); + PIN_SLP(gpa1-1, INPUT, DOWN); + PIN_SLP(gpa1-2, INPUT, DOWN); + PIN_SLP(gpa1-3, INPUT, DOWN); + PIN_SLP(gpa1-4, INPUT, DOWN); + PIN_SLP(gpa1-5, INPUT, DOWN); + + PIN_SLP(gpb-0, INPUT, NONE); + PIN_SLP(gpb-1, INPUT, NONE); + PIN_SLP(gpb-2, INPUT, NONE); + PIN_SLP(gpb-3, INPUT, NONE); + PIN_SLP(gpb-4, INPUT, DOWN); + PIN_SLP(gpb-5, INPUT, UP); + PIN_SLP(gpb-6, INPUT, DOWN); + PIN_SLP(gpb-7, INPUT, DOWN); + + PIN_SLP(gpc0-0, INPUT, DOWN); + PIN_SLP(gpc0-1, INPUT, DOWN); + PIN_SLP(gpc0-2, INPUT, DOWN); + PIN_SLP(gpc0-3, INPUT, DOWN); + PIN_SLP(gpc0-4, INPUT, DOWN); + + PIN_SLP(gpc1-0, INPUT, NONE); + PIN_SLP(gpc1-1, PREV, NONE); + PIN_SLP(gpc1-2, INPUT, NONE); + PIN_SLP(gpc1-3, INPUT, NONE); + PIN_SLP(gpc1-4, INPUT, NONE); + + PIN_SLP(gpd0-0, INPUT, DOWN); + PIN_SLP(gpd0-1, INPUT, DOWN); + PIN_SLP(gpd0-2, INPUT, NONE); + PIN_SLP(gpd0-3, INPUT, NONE); + + PIN_SLP(gpd1-0, INPUT, DOWN); + PIN_SLP(gpd1-1, INPUT, DOWN); + PIN_SLP(gpd1-2, INPUT, NONE); + PIN_SLP(gpd1-3, INPUT, NONE); + + PIN_SLP(gpf0-0, INPUT, NONE); + PIN_SLP(gpf0-1, INPUT, NONE); + PIN_SLP(gpf0-2, INPUT, DOWN); + PIN_SLP(gpf0-3, INPUT, DOWN); + PIN_SLP(gpf0-4, INPUT, NONE); + PIN_SLP(gpf0-5, INPUT, DOWN); + PIN_SLP(gpf0-6, INPUT, NONE); + PIN_SLP(gpf0-7, INPUT, DOWN); + + PIN_SLP(gpf1-0, INPUT, DOWN); + PIN_SLP(gpf1-1, INPUT, DOWN); + PIN_SLP(gpf1-2, INPUT, DOWN); + PIN_SLP(gpf1-3, INPUT, DOWN); + PIN_SLP(gpf1-4, INPUT, NONE); + PIN_SLP(gpf1-5, INPUT, NONE); + PIN_SLP(gpf1-6, INPUT, DOWN); + PIN_SLP(gpf1-7, PREV, NONE); + + PIN_SLP(gpf2-0, PREV, NONE); + PIN_SLP(gpf2-1, INPUT, DOWN); + PIN_SLP(gpf2-2, INPUT, DOWN); + PIN_SLP(gpf2-3, INPUT, DOWN); + PIN_SLP(gpf2-4, INPUT, DOWN); + PIN_SLP(gpf2-5, INPUT, DOWN); + PIN_SLP(gpf2-6, INPUT, NONE); + PIN_SLP(gpf2-7, INPUT, NONE); + + PIN_SLP(gpf3-0, INPUT, NONE); + PIN_SLP(gpf3-1, PREV, NONE); + PIN_SLP(gpf3-2, PREV, NONE); + PIN_SLP(gpf3-3, PREV, NONE); + PIN_SLP(gpf3-4, OUT1, NONE); + PIN_SLP(gpf3-5, INPUT, DOWN); + + PIN_SLP(gpj0-0, PREV, NONE); + PIN_SLP(gpj0-1, PREV, NONE); + PIN_SLP(gpj0-2, PREV, NONE); + PIN_SLP(gpj0-3, INPUT, DOWN); + PIN_SLP(gpj0-4, PREV, NONE); + PIN_SLP(gpj0-5, PREV, NONE); + PIN_SLP(gpj0-6, INPUT, DOWN); + PIN_SLP(gpj0-7, INPUT, DOWN); + + PIN_SLP(gpj1-0, INPUT, DOWN); + PIN_SLP(gpj1-1, PREV, NONE); + PIN_SLP(gpj1-2, PREV, NONE); + PIN_SLP(gpj1-3, INPUT, DOWN); + PIN_SLP(gpj1-4, INPUT, DOWN); + }; +}; + +&pinctrl_1 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep1>; + + sleep1: sleep-states { + PIN_SLP(gpk0-0, PREV, NONE); + PIN_SLP(gpk0-1, PREV, NONE); + PIN_SLP(gpk0-2, OUT0, NONE); + PIN_SLP(gpk0-3, PREV, NONE); + PIN_SLP(gpk0-4, PREV, NONE); + PIN_SLP(gpk0-5, PREV, NONE); + PIN_SLP(gpk0-6, PREV, NONE); + + PIN_SLP(gpk1-0, INPUT, DOWN); + PIN_SLP(gpk1-1, INPUT, DOWN); + PIN_SLP(gpk1-2, INPUT, DOWN); + PIN_SLP(gpk1-3, PREV, NONE); + PIN_SLP(gpk1-4, PREV, NONE); + PIN_SLP(gpk1-5, PREV, NONE); + PIN_SLP(gpk1-6, PREV, NONE); + + PIN_SLP(gpk2-0, INPUT, DOWN); + PIN_SLP(gpk2-1, INPUT, DOWN); + PIN_SLP(gpk2-2, INPUT, DOWN); + PIN_SLP(gpk2-3, INPUT, DOWN); + PIN_SLP(gpk2-4, INPUT, DOWN); + PIN_SLP(gpk2-5, INPUT, DOWN); + PIN_SLP(gpk2-6, INPUT, DOWN); + + PIN_SLP(gpk3-0, OUT0, NONE); + PIN_SLP(gpk3-1, INPUT, NONE); + PIN_SLP(gpk3-2, INPUT, DOWN); + PIN_SLP(gpk3-3, INPUT, NONE); + PIN_SLP(gpk3-4, INPUT, NONE); + PIN_SLP(gpk3-5, INPUT, NONE); + PIN_SLP(gpk3-6, INPUT, NONE); + + PIN_SLP(gpl0-0, INPUT, DOWN); + PIN_SLP(gpl0-1, INPUT, DOWN); + PIN_SLP(gpl0-2, INPUT, DOWN); + PIN_SLP(gpl0-3, INPUT, DOWN); + PIN_SLP(gpl0-4, PREV, NONE); + PIN_SLP(gpl0-6, PREV, NONE); + + PIN_SLP(gpl1-0, INPUT, DOWN); + PIN_SLP(gpl1-1, INPUT, DOWN); + PIN_SLP(gpl2-0, INPUT, DOWN); + PIN_SLP(gpl2-1, INPUT, DOWN); + PIN_SLP(gpl2-2, INPUT, DOWN); + PIN_SLP(gpl2-3, INPUT, DOWN); + PIN_SLP(gpl2-4, INPUT, DOWN); + PIN_SLP(gpl2-5, INPUT, DOWN); + PIN_SLP(gpl2-6, PREV, NONE); + PIN_SLP(gpl2-7, INPUT, DOWN); + + PIN_SLP(gpm0-0, INPUT, DOWN); + PIN_SLP(gpm0-1, INPUT, DOWN); + PIN_SLP(gpm0-2, INPUT, DOWN); + PIN_SLP(gpm0-3, INPUT, DOWN); + PIN_SLP(gpm0-4, INPUT, DOWN); + PIN_SLP(gpm0-5, INPUT, DOWN); + PIN_SLP(gpm0-6, INPUT, DOWN); + PIN_SLP(gpm0-7, INPUT, DOWN); + + PIN_SLP(gpm1-0, INPUT, DOWN); + PIN_SLP(gpm1-1, INPUT, DOWN); + PIN_SLP(gpm1-2, INPUT, NONE); + PIN_SLP(gpm1-3, INPUT, NONE); + PIN_SLP(gpm1-4, INPUT, NONE); + PIN_SLP(gpm1-5, INPUT, NONE); + PIN_SLP(gpm1-6, INPUT, DOWN); + + PIN_SLP(gpm2-0, INPUT, NONE); + PIN_SLP(gpm2-1, INPUT, NONE); + PIN_SLP(gpm2-2, INPUT, DOWN); + PIN_SLP(gpm2-3, INPUT, DOWN); + PIN_SLP(gpm2-4, INPUT, DOWN); + + PIN_SLP(gpm3-0, PREV, NONE); + PIN_SLP(gpm3-1, PREV, NONE); + PIN_SLP(gpm3-2, PREV, NONE); + PIN_SLP(gpm3-3, OUT1, NONE); + PIN_SLP(gpm3-4, INPUT, DOWN); + PIN_SLP(gpm3-5, INPUT, DOWN); + PIN_SLP(gpm3-6, INPUT, DOWN); + PIN_SLP(gpm3-7, INPUT, DOWN); + + PIN_SLP(gpm4-0, INPUT, DOWN); + PIN_SLP(gpm4-1, INPUT, DOWN); + PIN_SLP(gpm4-2, INPUT, DOWN); + PIN_SLP(gpm4-3, INPUT, DOWN); + PIN_SLP(gpm4-4, INPUT, DOWN); + PIN_SLP(gpm4-5, INPUT, DOWN); + PIN_SLP(gpm4-6, INPUT, DOWN); + PIN_SLP(gpm4-7, INPUT, DOWN); + + PIN_SLP(gpy0-0, INPUT, DOWN); + PIN_SLP(gpy0-1, INPUT, DOWN); + PIN_SLP(gpy0-2, INPUT, DOWN); + PIN_SLP(gpy0-3, INPUT, DOWN); + PIN_SLP(gpy0-4, INPUT, DOWN); + PIN_SLP(gpy0-5, INPUT, DOWN); + + PIN_SLP(gpy1-0, INPUT, DOWN); + PIN_SLP(gpy1-1, INPUT, DOWN); + PIN_SLP(gpy1-2, INPUT, DOWN); + PIN_SLP(gpy1-3, INPUT, DOWN); + + PIN_SLP(gpy2-0, PREV, NONE); + PIN_SLP(gpy2-1, INPUT, DOWN); + PIN_SLP(gpy2-2, INPUT, NONE); + PIN_SLP(gpy2-3, INPUT, NONE); + PIN_SLP(gpy2-4, INPUT, NONE); + PIN_SLP(gpy2-5, INPUT, NONE); + + PIN_SLP(gpy3-0, INPUT, DOWN); + PIN_SLP(gpy3-1, INPUT, DOWN); + PIN_SLP(gpy3-2, INPUT, DOWN); + PIN_SLP(gpy3-3, INPUT, DOWN); + PIN_SLP(gpy3-4, INPUT, DOWN); + PIN_SLP(gpy3-5, INPUT, DOWN); + PIN_SLP(gpy3-6, INPUT, DOWN); + PIN_SLP(gpy3-7, INPUT, DOWN); + + PIN_SLP(gpy4-0, INPUT, DOWN); + PIN_SLP(gpy4-1, INPUT, DOWN); + PIN_SLP(gpy4-2, INPUT, DOWN); + PIN_SLP(gpy4-3, INPUT, DOWN); + PIN_SLP(gpy4-4, INPUT, DOWN); + PIN_SLP(gpy4-5, INPUT, DOWN); + PIN_SLP(gpy4-6, INPUT, DOWN); + PIN_SLP(gpy4-7, INPUT, DOWN); + + PIN_SLP(gpy5-0, INPUT, DOWN); + PIN_SLP(gpy5-1, INPUT, DOWN); + PIN_SLP(gpy5-2, INPUT, DOWN); + PIN_SLP(gpy5-3, INPUT, DOWN); + PIN_SLP(gpy5-4, INPUT, DOWN); + PIN_SLP(gpy5-5, INPUT, DOWN); + PIN_SLP(gpy5-6, INPUT, DOWN); + PIN_SLP(gpy5-7, INPUT, DOWN); + + PIN_SLP(gpy6-0, INPUT, DOWN); + PIN_SLP(gpy6-1, INPUT, DOWN); + PIN_SLP(gpy6-2, INPUT, DOWN); + PIN_SLP(gpy6-3, INPUT, DOWN); + PIN_SLP(gpy6-4, INPUT, DOWN); + PIN_SLP(gpy6-5, INPUT, DOWN); + PIN_SLP(gpy6-6, INPUT, DOWN); + PIN_SLP(gpy6-7, INPUT, DOWN); + }; +}; + +&pinctrl_2 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep2>; + + sleep2: sleep-states { + PIN_SLP(gpz-0, INPUT, DOWN); + PIN_SLP(gpz-1, INPUT, DOWN); + PIN_SLP(gpz-2, INPUT, DOWN); + PIN_SLP(gpz-3, INPUT, DOWN); + PIN_SLP(gpz-4, INPUT, DOWN); + PIN_SLP(gpz-5, INPUT, DOWN); + PIN_SLP(gpz-6, INPUT, DOWN); + }; +}; + +&pinctrl_3 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep3>; + + sleep3: sleep-states { + PIN_SLP(gpv0-0, INPUT, DOWN); + PIN_SLP(gpv0-1, INPUT, DOWN); + PIN_SLP(gpv0-2, INPUT, DOWN); + PIN_SLP(gpv0-3, INPUT, DOWN); + PIN_SLP(gpv0-4, INPUT, DOWN); + PIN_SLP(gpv0-5, INPUT, DOWN); + PIN_SLP(gpv0-6, INPUT, DOWN); + PIN_SLP(gpv0-7, INPUT, DOWN); + + PIN_SLP(gpv1-0, INPUT, DOWN); + PIN_SLP(gpv1-1, INPUT, DOWN); + PIN_SLP(gpv1-2, INPUT, DOWN); + PIN_SLP(gpv1-3, INPUT, DOWN); + PIN_SLP(gpv1-4, INPUT, DOWN); + PIN_SLP(gpv1-5, INPUT, DOWN); + PIN_SLP(gpv1-6, INPUT, DOWN); + PIN_SLP(gpv1-7, INPUT, DOWN); + + PIN_SLP(gpv2-0, INPUT, DOWN); + PIN_SLP(gpv2-1, INPUT, DOWN); + PIN_SLP(gpv2-2, INPUT, DOWN); + PIN_SLP(gpv2-3, INPUT, DOWN); + PIN_SLP(gpv2-4, INPUT, DOWN); + PIN_SLP(gpv2-5, INPUT, DOWN); + PIN_SLP(gpv2-6, INPUT, DOWN); + PIN_SLP(gpv2-7, INPUT, DOWN); + + PIN_SLP(gpv3-0, INPUT, DOWN); + PIN_SLP(gpv3-1, INPUT, DOWN); + PIN_SLP(gpv3-2, INPUT, DOWN); + PIN_SLP(gpv3-3, INPUT, DOWN); + PIN_SLP(gpv3-4, INPUT, DOWN); + PIN_SLP(gpv3-5, INPUT, DOWN); + PIN_SLP(gpv3-6, INPUT, DOWN); + PIN_SLP(gpv3-7, INPUT, DOWN); + + PIN_SLP(gpv4-0, INPUT, DOWN); + }; +}; diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index d8bc059e172f..0f6ec93bb1d8 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -22,6 +22,35 @@ / { compatible = "samsung,exynos4412", "samsung,exynos4"; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@A00 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xA00>; + }; + + cpu@A01 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xA01>; + }; + + cpu@A02 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xA02>; + }; + + cpu@A03 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xA03>; + }; + }; + combiner: interrupt-controller@10440000 { samsung,combiner-nr = <20>; }; diff --git a/arch/arm/boot/dts/exynos4415-pinctrl.dtsi b/arch/arm/boot/dts/exynos4415-pinctrl.dtsi new file mode 100644 index 000000000000..75af9c56123e --- /dev/null +++ b/arch/arm/boot/dts/exynos4415-pinctrl.dtsi @@ -0,0 +1,573 @@ +/* + * Samsung's Exynos4415 SoCs pin-mux and pin-config device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * + * Samsung's Exynos4415 SoCs pin-mux and pin-config optiosn are listed as device + * tree nodes are listed in this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. +*/ + +&pinctrl_0 { + gpa0: gpa0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpa1: gpa1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpb: gpb { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc0: gpc0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpc1: gpc1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd0: gpd0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpd1: gpd1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf0: gpf0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf1: gpf1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpf2: gpf2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + uart0_data: uart0-data { + samsung,pins = "gpa0-0", "gpa0-1"; + samsung,pin-function = <0x2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart0_fctl: uart0-fctl { + samsung,pins = "gpa0-2", "gpa0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart1_data: uart1-data { + samsung,pins = "gpa0-4", "gpa0-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart1_fctl: uart1-fctl { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart2_data: uart2-data { + samsung,pins = "gpa1-0", "gpa1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart2_fctl: uart2-fctl { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + uart3_data: uart3-data { + samsung,pins = "gpa1-4", "gpa1-5"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c2_bus: i2c2-bus { + samsung,pins = "gpa0-6", "gpa0-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c3_bus: i2c3-bus { + samsung,pins = "gpa1-2", "gpa1-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi0_bus: spi0-bus { + samsung,pins = "gpb-0", "gpb-2", "gpb-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c4_bus: i2c4-bus { + samsung,pins = "gpb-0", "gpb-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi1_bus: spi1-bus { + samsung,pins = "gpb-4", "gpb-6", "gpb-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c5_bus: i2c5-bus { + samsung,pins = "gpb-2", "gpb-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2s1_bus: i2s1-bus { + samsung,pins = "gpc0-0", "gpc0-1", "gpc0-2", "gpc0-3", + "gpc0-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2s2_bus: i2s2-bus { + samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", + "gpc1-4"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pcm2_bus: pcm2-bus { + samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3", + "gpc1-4"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c6_bus: i2c6-bus { + samsung,pins = "gpc1-3", "gpc1-4"; + samsung,pin-function = <4>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + spi2_bus: spi2-bus { + samsung,pins = "gpc1-1", "gpc1-3", "gpc1-4"; + samsung,pin-function = <5>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + pwm0_out: pwm0-out { + samsung,pins = "gpd0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pwm1_out: pwm1-out { + samsung,pins = "gpd0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pwm2_out: pwm2-out { + samsung,pins = "gpd0-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pwm3_out: pwm3-out { + samsung,pins = "gpd0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + i2c7_bus: i2c7-bus { + samsung,pins = "gpd0-2", "gpd0-3"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c0_bus: i2c0-bus { + samsung,pins = "gpd1-0", "gpd1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + i2c1_bus: i2c1-bus { + samsung,pins = "gpd1-2", "gpd1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_1 { + gpk0: gpk0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk1: gpk1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk2: gpk2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpk3: gpk3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpl0: gpl0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm0: gpm0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm1: gpm1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm2: gpm2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm3: gpm3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpm4: gpm4 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx0: gpx0 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <0 32 0>, <0 33 0>, <0 34 0>, <0 35 0>, + <0 36 0>, <0 37 0>, <0 38 0>, <0 39 0>; + #interrupt-cells = <2>; + }; + + gpx1: gpx1 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + interrupt-parent = <&gic>; + interrupts = <0 40 0>, <0 41 0>, <0 42 0>, <0 43 0>, + <0 44 0>, <0 45 0>, <0 46 0>, <0 47 0>; + #interrupt-cells = <2>; + }; + + gpx2: gpx2 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpx3: gpx3 { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sd0_clk: sd0-clk { + samsung,pins = "gpk0-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_cmd: sd0-cmd { + samsung,pins = "gpk0-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_cd: sd0-cd { + samsung,pins = "gpk0-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_rdqs: sd0-rdqs { + samsung,pins = "gpk0-7"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd0_bus1: sd0-bus-width1 { + samsung,pins = "gpk0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus4: sd0-bus-width4 { + samsung,pins = "gpk0-4", "gpk0-5", "gpk0-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd0_bus8: sd0-bus-width8 { + samsung,pins = "gpl0-0", "gpl0-1", "gpl0-2", "gpl0-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_clk: sd1-clk { + samsung,pins = "gpk1-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd1_cmd: sd1-cmd { + samsung,pins = "gpk1-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + sd1_cd: sd1-cd { + samsung,pins = "gpk1-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_bus1: sd1-bus-width1 { + samsung,pins = "gpk1-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd1_bus4: sd1-bus-width4 { + samsung,pins = "gpk1-4", "gpk1-5", "gpk1-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_clk: sd2-clk { + samsung,pins = "gpk2-0"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <4>; + }; + + sd2_cmd: sd2-cmd { + samsung,pins = "gpk2-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <4>; + }; + + sd2_cd: sd2-cd { + samsung,pins = "gpk2-2"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <3>; + }; + + sd2_bus1: sd2-bus-width1 { + samsung,pins = "gpk2-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <4>; + }; + + sd2_bus4: sd2-bus-width4 { + samsung,pins = "gpk2-4", "gpk2-5", "gpk2-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <3>; + samsung,pin-drv = <4>; + }; + + cam_port_b_io: cam-port-b-io { + samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", + "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", + "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1"; + samsung,pin-function = <3>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + cam_port_b_clk_active: cam-port-b-clk-active { + samsung,pins = "gpm2-2"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <3>; + }; + + cam_port_b_clk_idle: cam-port-b-clk-idle { + samsung,pins = "gpm2-2"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_i2c0: fimc-is-i2c0 { + samsung,pins = "gpm4-0", "gpm4-1"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_i2c1: fimc-is-i2c1 { + samsung,pins = "gpm4-2", "gpm4-3"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + fimc_is_uart: fimc-is-uart { + samsung,pins = "gpm3-5", "gpm3-7"; + samsung,pin-function = <3>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_2 { + gpz: gpz { + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + i2s0_bus: i2s0-bus { + samsung,pins = "gpz-0", "gpz-1", "gpz-2", "gpz-3", + "gpz-4", "gpz-5", "gpz-6"; + samsung,pin-function = <2>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; +}; diff --git a/arch/arm/boot/dts/exynos4415.dtsi b/arch/arm/boot/dts/exynos4415.dtsi new file mode 100644 index 000000000000..c1c9b37340d9 --- /dev/null +++ b/arch/arm/boot/dts/exynos4415.dtsi @@ -0,0 +1,604 @@ +/* + * Samsung's Exynos4415 SoC device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * + * Samsung's Exynos4415 SoC device nodes are listed in this file. Exynos4415 + * based board files can include this file and provide values for board + * specific bindings. + * + * Note: This file does not include device nodes for all the controllers in + * Exynos4415 SoC. As device tree coverage for Exynos4415 increases, additional + * nodes can be added to this file. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "skeleton.dtsi" +#include <dt-bindings/clock/exynos4415.h> +#include <dt-bindings/clock/exynos-audss-clk.h> + +/ { + compatible = "samsung,exynos4415"; + interrupt-parent = <&gic>; + + aliases { + pinctrl0 = &pinctrl_0; + pinctrl1 = &pinctrl_1; + pinctrl2 = &pinctrl_2; + mshc0 = &mshc_0; + mshc1 = &mshc_1; + mshc2 = &mshc_2; + spi0 = &spi_0; + spi1 = &spi_1; + spi2 = &spi_2; + i2c0 = &i2c_0; + i2c1 = &i2c_1; + i2c2 = &i2c_2; + i2c3 = &i2c_3; + i2c4 = &i2c_4; + i2c5 = &i2c_5; + i2c6 = &i2c_6; + i2c7 = &i2c_7; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@a00 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xa00>; + clock-frequency = <1600000000>; + }; + + cpu1: cpu@a01 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xa01>; + clock-frequency = <1600000000>; + }; + + cpu2: cpu@a02 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xa02>; + clock-frequency = <1600000000>; + }; + + cpu3: cpu@a03 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xa03>; + clock-frequency = <1600000000>; + }; + }; + + soc: soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sysram@02020000 { + compatible = "mmio-sram"; + reg = <0x02020000 0x50000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x02020000 0x50000>; + + smp-sysram@0 { + compatible = "samsung,exynos4210-sysram"; + reg = <0x0 0x1000>; + }; + + smp-sysram@4f000 { + compatible = "samsung,exynos4210-sysram-ns"; + reg = <0x4f000 0x1000>; + }; + }; + + pinctrl_2: pinctrl@03860000 { + compatible = "samsung,exynos4415-pinctrl"; + reg = <0x03860000 0x1000>; + interrupts = <0 242 0>; + }; + + chipid@10000000 { + compatible = "samsung,exynos4210-chipid"; + reg = <0x10000000 0x100>; + }; + + sysreg_system_controller: syscon@10010000 { + compatible = "samsung,exynos4-sysreg", "syscon"; + reg = <0x10010000 0x400>; + }; + + pmu_system_controller: system-controller@10020000 { + compatible = "samsung,exynos4415-pmu", "syscon"; + reg = <0x10020000 0x4000>; + }; + + mipi_phy: video-phy@10020710 { + compatible = "samsung,s5pv210-mipi-video-phy"; + reg = <0x10020710 8>; + #phy-cells = <1>; + }; + + pd_cam: cam-power-domain@10024000 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10024000 0x20>; + }; + + pd_tv: tv-power-domain@10024020 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10024020 0x20>; + }; + + pd_mfc: mfc-power-domain@10024040 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10024040 0x20>; + }; + + pd_g3d: g3d-power-domain@10024060 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10024060 0x20>; + }; + + pd_lcd0: lcd0-power-domain@10024080 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10024080 0x20>; + }; + + pd_isp0: isp0-power-domain@100240A0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x100240A0 0x20>; + }; + + pd_isp1: isp1-power-domain@100240E0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x100240E0 0x20>; + }; + + cmu: clock-controller@10030000 { + compatible = "samsung,exynos4415-cmu"; + reg = <0x10030000 0x18000>; + #clock-cells = <1>; + }; + + rtc: rtc@10070000 { + compatible = "samsung,exynos3250-rtc"; + reg = <0x10070000 0x100>; + interrupts = <0 73 0>, <0 74 0>; + status = "disabled"; + }; + + mct@10050000 { + compatible = "samsung,exynos4210-mct"; + reg = <0x10050000 0x800>; + interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>, + <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>; + clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>; + clock-names = "fin_pll", "mct"; + }; + + gic: interrupt-controller@10481000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x10481000 0x1000>, + <0x10482000 0x1000>, + <0x10484000 0x2000>, + <0x10486000 0x2000>; + interrupts = <1 9 0xf04>; + }; + + l2c: l2-cache-controller@10502000 { + compatible = "arm,pl310-cache"; + reg = <0x10502000 0x1000>; + cache-unified; + cache-level = <2>; + arm,tag-latency = <2 2 1>; + arm,data-latency = <3 2 1>; + arm,double-linefill = <1>; + arm,double-linefill-incr = <0>; + arm,double-linefill-wrap = <1>; + arm,prefetch-drop = <1>; + arm,prefetch-offset = <7>; + }; + + cmu_dmc: clock-controller@105C0000 { + compatible = "samsung,exynos4415-cmu-dmc"; + reg = <0x105C0000 0x3000>; + #clock-cells = <1>; + }; + + pinctrl_1: pinctrl@11000000 { + compatible = "samsung,exynos4415-pinctrl"; + reg = <0x11000000 0x1000>; + interrupts = <0 225 0>; + + wakeup-interrupt-controller { + compatible = "samsung,exynos4210-wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = <0 48 0>; + }; + }; + + pinctrl_0: pinctrl@11400000 { + compatible = "samsung,exynos4415-pinctrl"; + reg = <0x11400000 0x1000>; + interrupts = <0 240 0>; + }; + + hsotg: hsotg@12480000 { + compatible = "samsung,s3c6400-hsotg"; + reg = <0x12480000 0x20000>; + interrupts = <0 141 0>; + clocks = <&cmu CLK_USBDEVICE>; + clock-names = "otg"; + phys = <&exynos_usbphy 0>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + mshc_0: mshc@12510000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12510000 0x1000>; + interrupts = <0 142 0>; + clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>; + clock-names = "biu", "ciu"; + fifo-depth = <0x80>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + mshc_1: mshc@12520000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12520000 0x1000>; + interrupts = <0 143 0>; + clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>; + clock-names = "biu", "ciu"; + fifo-depth = <0x80>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + mshc_2: mshc@12530000 { + compatible = "samsung,exynos5250-dw-mshc"; + reg = <0x12530000 0x1000>; + interrupts = <0 144 0>; + clocks = <&cmu CLK_SDMMC2>, <&cmu CLK_SCLK_MMC2>; + clock-names = "biu", "ciu"; + fifo-depth = <0x80>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ehci: ehci@12580000 { + compatible = "samsung,exynos4210-ehci"; + reg = <0x12580000 0x100>; + interrupts = <0 140 0>; + clocks = <&cmu CLK_USBHOST>; + clock-names = "usbhost"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + phys = <&exynos_usbphy 1>; + status = "disabled"; + }; + port@1 { + reg = <1>; + phys = <&exynos_usbphy 2>; + status = "disabled"; + }; + port@2 { + reg = <2>; + phys = <&exynos_usbphy 3>; + status = "disabled"; + }; + }; + + ohci: ohci@12590000 { + compatible = "samsung,exynos4210-ohci"; + reg = <0x12590000 0x100>; + interrupts = <0 140 0>; + clocks = <&cmu CLK_USBHOST>; + clock-names = "usbhost"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + phys = <&exynos_usbphy 1>; + status = "disabled"; + }; + }; + + exynos_usbphy: exynos-usbphy@125B0000 { + compatible = "samsung,exynos4x12-usb2-phy"; + reg = <0x125B0000 0x100>; + samsung,pmureg-phandle = <&pmu_system_controller>; + samsung,sysreg-phandle = <&sysreg_system_controller>; + clocks = <&cmu CLK_USBDEVICE>, <&xusbxti>; + clock-names = "phy", "ref"; + #phy-cells = <1>; + status = "disabled"; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + ranges; + + pdma0: pdma@12680000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x12680000 0x1000>; + interrupts = <0 138 0>; + clocks = <&cmu CLK_PDMA0>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + + pdma1: pdma@12690000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x12690000 0x1000>; + interrupts = <0 139 0>; + clocks = <&cmu CLK_PDMA1>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + }; + + adc: adc@126C0000 { + compatible = "samsung,exynos3250-adc", + "samsung,exynos-adc-v2"; + reg = <0x126C0000 0x100>, <0x10020718 0x4>; + interrupts = <0 137 0>; + clock-names = "adc", "sclk"; + clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>; + #io-channel-cells = <1>; + io-channel-ranges; + status = "disabled"; + }; + + serial_0: serial@13800000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13800000 0x100>; + interrupts = <0 109 0>; + clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + serial_1: serial@13810000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13810000 0x100>; + interrupts = <0 110 0>; + clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + serial_2: serial@13820000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13820000 0x100>; + interrupts = <0 111 0>; + clocks = <&cmu CLK_UART2>, <&cmu CLK_SCLK_UART2>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + serial_3: serial@13830000 { + compatible = "samsung,exynos4210-uart"; + reg = <0x13830000 0x100>; + interrupts = <0 112 0>; + clocks = <&cmu CLK_UART3>, <&cmu CLK_SCLK_UART3>; + clock-names = "uart", "clk_uart_baud0"; + status = "disabled"; + }; + + i2c_0: i2c@13860000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x13860000 0x100>; + interrupts = <0 113 0>; + clocks = <&cmu CLK_I2C0>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_bus>; + status = "disabled"; + }; + + i2c_1: i2c@13870000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x13870000 0x100>; + interrupts = <0 114 0>; + clocks = <&cmu CLK_I2C1>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_bus>; + status = "disabled"; + }; + + i2c_2: i2c@13880000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x13880000 0x100>; + interrupts = <0 115 0>; + clocks = <&cmu CLK_I2C2>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_bus>; + status = "disabled"; + }; + + i2c_3: i2c@13890000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x13890000 0x100>; + interrupts = <0 116 0>; + clocks = <&cmu CLK_I2C3>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_bus>; + status = "disabled"; + }; + + i2c_4: i2c@138A0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x138A0000 0x100>; + interrupts = <0 117 0>; + clocks = <&cmu CLK_I2C4>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_bus>; + status = "disabled"; + }; + + i2c_5: i2c@138B0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x138B0000 0x100>; + interrupts = <0 118 0>; + clocks = <&cmu CLK_I2C5>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_bus>; + status = "disabled"; + }; + + i2c_6: i2c@138C0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x138C0000 0x100>; + interrupts = <0 119 0>; + clocks = <&cmu CLK_I2C6>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_bus>; + status = "disabled"; + }; + + i2c_7: i2c@138D0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "samsung,s3c2440-i2c"; + reg = <0x138D0000 0x100>; + interrupts = <0 120 0>; + clocks = <&cmu CLK_I2C7>; + clock-names = "i2c"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_bus>; + status = "disabled"; + }; + + spi_0: spi@13920000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x13920000 0x100>; + interrupts = <0 121 0>; + dmas = <&pdma0 7>, <&pdma0 6>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_bus>; + status = "disabled"; + }; + + spi_1: spi@13930000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x13930000 0x100>; + interrupts = <0 122 0>; + dmas = <&pdma1 7>, <&pdma1 6>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_bus>; + status = "disabled"; + }; + + spi_2: spi@13940000 { + compatible = "samsung,exynos4210-spi"; + reg = <0x13940000 0x100>; + interrupts = <0 123 0>; + dmas = <&pdma0 9>, <&pdma0 8>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cmu CLK_SPI2>, <&cmu CLK_SCLK_SPI2>; + clock-names = "spi", "spi_busclk0"; + samsung,spi-src-clk = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_bus>; + status = "disabled"; + }; + + clock_audss: clock-controller@03810000 { + compatible = "samsung,exynos4210-audss-clock"; + reg = <0x03810000 0x0C>; + #clock-cells = <1>; + }; + + i2s0: i2s@3830000 { + compatible = "samsung,s5pv210-i2s"; + reg = <0x03830000 0x100>; + interrupts = <0 124 0>; + clocks = <&clock_audss EXYNOS_I2S_BUS>, + <&clock_audss EXYNOS_SCLK_I2S>; + clock-names = "iis", "i2s_opclk0"; + dmas = <&pdma1 10>, <&pdma1 9>, <&pdma1 8>; + dma-names = "tx", "rx", "tx-sec"; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_bus>; + samsung,idma-addr = <0x03000000>; + status = "disabled"; + }; + + pwm: pwm@139D0000 { + compatible = "samsung,exynos4210-pwm"; + reg = <0x139D0000 0x1000>; + interrupts = <0 104 0>, <0 105 0>, <0 106 0>, + <0 107 0>, <0 108 0>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 18 0>, <0 19 0>, <0 20 0>, <0 21 0>; + }; + }; +}; + +#include "exynos4415-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi index 99b26df8dbc7..c141931378e7 100644 --- a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi @@ -12,6 +12,22 @@ * published by the Free Software Foundation. */ +#define PIN_PULL_NONE 0 +#define PIN_PULL_DOWN 1 +#define PIN_PULL_UP 3 + +#define PIN_PDN_OUT0 0 +#define PIN_PDN_OUT1 1 +#define PIN_PDN_INPUT 2 +#define PIN_PDN_PREV 3 + +#define PIN_SLP(_pin, _mode, _pull) \ + _pin { \ + samsung,pins = #_pin; \ + samsung,pin-con-pdn = <PIN_PDN_ ##_mode>; \ + samsung,pin-pud-pdn = <PIN_PULL_ ##_pull>; \ + } + / { pinctrl@11400000 { gpa0: gpa0 { @@ -675,7 +691,7 @@ sd4_bus8: sd4-bus-width8 { samsung,pins = "gpk1-3", "gpk1-4", "gpk1-5", "gpk1-6"; samsung,pin-function = <4>; - samsung,pin-pud = <4>; + samsung,pin-pud = <3>; samsung,pin-drv = <3>; }; diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi index 861bb919f6d3..93b70402e943 100644 --- a/arch/arm/boot/dts/exynos4x12.dtsi +++ b/arch/arm/boot/dts/exynos4x12.dtsi @@ -108,13 +108,14 @@ adc: adc@126C0000 { compatible = "samsung,exynos-adc-v1"; - reg = <0x126C0000 0x100>, <0x10020718 0x4>; + reg = <0x126C0000 0x100>; interrupt-parent = <&combiner>; interrupts = <10 3>; clocks = <&clock CLK_TSADC>; clock-names = "adc"; #io-channel-cells = <1>; io-channel-ranges; + samsung,syscon-phandle = <&pmu_system_controller>; status = "disabled"; }; @@ -271,4 +272,14 @@ compatible = "samsung,exynos4x12-usb2-phy"; samsung,sysreg-phandle = <&sys_reg>; }; + + tmu@100C0000 { + compatible = "samsung,exynos4412-tmu"; + interrupt-parent = <&combiner>; + interrupts = <2 4>; + reg = <0x100C0000 0x100>; + clocks = <&clock 383>; + clock-names = "tmu_apbif"; + status = "disabled"; + }; }; diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index d0de1f50d15b..7e728a1b5559 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -7,12 +7,13 @@ * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. -*/ + */ /dts-v1/; -#include "exynos5250.dtsi" +#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/input/input.h> +#include "exynos5250.dtsi" / { model = "Insignal Arndale evaluation board based on EXYNOS5250"; @@ -26,473 +27,52 @@ bootargs = "console=ttySAC2,115200"; }; - rtc@101E0000 { - status = "okay"; - }; - - codec@11000000 { - samsung,mfc-r = <0x43000000 0x800000>; - samsung,mfc-l = <0x51000000 0x800000>; - }; - - i2c@12C60000 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <20000>; - samsung,i2c-slave-addr = <0x66>; - status = "okay"; - - s5m8767_pmic@66 { - compatible = "samsung,s5m8767-pmic"; - reg = <0x66>; - interrupt-parent = <&gpx3>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - - vinb1-supply = <&main_dc_reg>; - vinb2-supply = <&main_dc_reg>; - vinb3-supply = <&main_dc_reg>; - vinb4-supply = <&main_dc_reg>; - vinb5-supply = <&main_dc_reg>; - vinb6-supply = <&main_dc_reg>; - vinb7-supply = <&main_dc_reg>; - vinb8-supply = <&main_dc_reg>; - vinb9-supply = <&main_dc_reg>; - - vinl1-supply = <&buck7_reg>; - vinl2-supply = <&buck7_reg>; - vinl3-supply = <&buck7_reg>; - vinl4-supply = <&main_dc_reg>; - vinl5-supply = <&main_dc_reg>; - vinl6-supply = <&main_dc_reg>; - vinl7-supply = <&main_dc_reg>; - vinl8-supply = <&buck8_reg>; - vinl9-supply = <&buck8_reg>; - - s5m8767,pmic-buck2-dvs-voltage = <1300000>; - s5m8767,pmic-buck3-dvs-voltage = <1100000>; - s5m8767,pmic-buck4-dvs-voltage = <1200000>; - s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 0>, - <&gpd1 1 0>, - <&gpd1 2 0>; - s5m8767,pmic-buck-ds-gpios = <&gpx2 3 0>, - <&gpx2 4 0>, - <&gpx2 5 0>; - regulators { - ldo1_reg: LDO1 { - regulator-name = "VDD_ALIVE_1.0V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo2_reg: LDO2 { - regulator-name = "VDD_28IO_DP_1.35V"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo3_reg: LDO3 { - regulator-name = "VDD_COMMON1_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo4_reg: LDO4 { - regulator-name = "VDD_IOPERI_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - op_mode = <1>; - }; - - ldo5_reg: LDO5 { - regulator-name = "VDD_EXT_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo6_reg: LDO6 { - regulator-name = "VDD_MPLL_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo7_reg: LDO7 { - regulator-name = "VDD_XPLL_1.1V"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo8_reg: LDO8 { - regulator-name = "VDD_COMMON2_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo9_reg: LDO9 { - regulator-name = "VDD_33ON_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - op_mode = <1>; - }; - - ldo10_reg: LDO10 { - regulator-name = "VDD_COMMON3_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo11_reg: LDO11 { - regulator-name = "VDD_ABB2_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo12_reg: LDO12 { - regulator-name = "VDD_USB_3.0V"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo13_reg: LDO13 { - regulator-name = "VDDQ_C2C_W_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo14_reg: LDO14 { - regulator-name = "VDD18_ABB0_3_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo15_reg: LDO15 { - regulator-name = "VDD10_COMMON4_1.0V"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo16_reg: LDO16 { - regulator-name = "VDD18_HSIC_1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo17_reg: LDO17 { - regulator-name = "VDDQ_MMC2_3_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - ldo18_reg: LDO18 { - regulator-name = "VDD_33ON_2.8V"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - op_mode = <1>; - }; - - ldo22_reg: LDO22 { - regulator-name = "EXT_33_OFF"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - op_mode = <1>; - }; - - ldo23_reg: LDO23 { - regulator-name = "EXT_28_OFF"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - op_mode = <1>; - }; - - ldo25_reg: LDO25 { - regulator-name = "PVDD_LDO25"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - op_mode = <1>; - }; - - ldo26_reg: LDO26 { - regulator-name = "EXT_18_OFF"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - op_mode = <1>; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <912500>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - buck5_reg: BUCK5 { - regulator-name = "VDD_MEM_1.35V"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <1355000>; - regulator-always-on; - regulator-boot-on; - op_mode = <1>; - }; - - buck7_reg: BUCK7 { - regulator-name = "PVDD_BUCK7"; - regulator-always-on; - op_mode = <1>; - }; - - buck8_reg: BUCK8 { - regulator-name = "PVDD_BUCK8"; - regulator-always-on; - op_mode = <1>; - }; - - buck9_reg: BUCK9 { - regulator-name = "VDD_33_OFF_EXT1"; - regulator-min-microvolt = <750000>; - regulator-max-microvolt = <3000000>; - op_mode = <1>; - }; - }; - }; - }; - - i2c@12C80000 { - status = "okay"; - - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - samsung,i2c-slave-addr = <0x50>; - - hdmiddc@50 { - compatible = "samsung,exynos4210-hdmiddc"; - reg = <0x50>; - }; - }; - - i2c@12C90000 { - status = "okay"; - - wm1811a@1a { - - compatible = "wlf,wm1811"; - reg = <0x1a>; - - AVDD2-supply = <&main_dc_reg>; - CPVDD-supply = <&main_dc_reg>; - DBVDD1-supply = <&main_dc_reg>; - DBVDD2-supply = <&main_dc_reg>; - DBVDD3-supply = <&main_dc_reg>; - LDO1VDD-supply = <&main_dc_reg>; - SPKVDD1-supply = <&main_dc_reg>; - SPKVDD2-supply = <&main_dc_reg>; - - wlf,ldo1ena = <&gpb0 0 0>; - wlf,ldo2ena = <&gpb0 1 0>; - }; - }; - - i2c@12CE0000 { - status = "okay"; - - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - samsung,i2c-slave-addr = <0x38>; - - hdmiphy@38 { - compatible = "samsung,exynos4212-hdmiphy"; - reg = <0x38>; - }; - }; - - i2c@121D0000 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <40000>; - samsung,i2c-slave-addr = <0x38>; - - sata_phy_i2c:sata-phy@38 { - compatible = "samsung,exynos-sataphy-i2c"; - reg = <0x38>; - }; - }; - - sata@122F0000 { - status = "okay"; - }; - - sata-phy@12170000 { - status = "okay"; - samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>; - }; - - mmc_0: mmc@12200000 { - status = "okay"; - num-slots = <1>; - supports-highspeed; - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - vmmc-supply = <&mmc_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; - - slot@0 { - reg = <0>; - bus-width = <8>; - }; - }; - - mmc_2: mmc@12220000 { - status = "okay"; - num-slots = <1>; - supports-highspeed; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - vmmc-supply = <&mmc_reg>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - - slot@0 { - reg = <0>; - bus-width = <4>; - disable-wp; - }; - }; - - i2s0: i2s@03830000 { - status = "okay"; - }; - gpio_keys { compatible = "gpio-keys"; menu { label = "SW-TACT2"; - gpios = <&gpx1 4 1>; + gpios = <&gpx1 4 GPIO_ACTIVE_LOW>; linux,code = <KEY_MENU>; gpio-key,wakeup; }; home { label = "SW-TACT3"; - gpios = <&gpx1 5 1>; + gpios = <&gpx1 5 GPIO_ACTIVE_LOW>; linux,code = <KEY_HOME>; gpio-key,wakeup; }; up { label = "SW-TACT4"; - gpios = <&gpx1 6 1>; + gpios = <&gpx1 6 GPIO_ACTIVE_LOW>; linux,code = <KEY_UP>; gpio-key,wakeup; }; down { label = "SW-TACT5"; - gpios = <&gpx1 7 1>; + gpios = <&gpx1 7 GPIO_ACTIVE_LOW>; linux,code = <KEY_DOWN>; gpio-key,wakeup; }; back { label = "SW-TACT6"; - gpios = <&gpx2 0 1>; + gpios = <&gpx2 0 GPIO_ACTIVE_LOW>; linux,code = <KEY_BACK>; gpio-key,wakeup; }; wakeup { label = "SW-TACT7"; - gpios = <&gpx2 1 1>; + gpios = <&gpx2 1 GPIO_ACTIVE_LOW>; linux,code = <KEY_WAKEUP>; gpio-key,wakeup; }; }; - hdmi { - hpd-gpio = <&gpx3 7 2>; - vdd_osc-supply = <&ldo10_reg>; - vdd_pll-supply = <&ldo8_reg>; - vdd-supply = <&ldo8_reg>; - }; - regulators { compatible = "simple-bus"; #address-cells = <1>; @@ -510,7 +90,7 @@ regulator-name = "VDD_33ON_2.8V"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; - gpio = <&gpx1 1 1>; + gpio = <&gpx1 1 GPIO_ACTIVE_LOW>; enable-active-high; }; @@ -528,50 +108,455 @@ }; }; - dp-controller@145B0000 { - samsung,color-space = <0>; - samsung,dynamic-range = <0>; - samsung,ycbcr-coeff = <0>; - samsung,color-depth = <1>; - samsung,link-rate = <0x0a>; - samsung,lane-count = <4>; - status = "okay"; + // SMSC USB3503 connected in hardware only mode as a PHY + usb_hub: usb-hub { + compatible = "smsc,usb3503a"; + + reset-gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; + connect-gpios = <&gpd1 7 GPIO_ACTIVE_LOW>; }; +}; - fimd: fimd@14400000 { - status = "okay"; - display-timings { - native-mode = <&timing0>; - timing0: timing@0 { - /* 2560x1600 DP panel */ - clock-frequency = <50000>; - hactive = <2560>; - vactive = <1600>; - hfront-porch = <48>; - hback-porch = <80>; - hsync-len = <32>; - vback-porch = <16>; - vfront-porch = <8>; - vsync-len = <6>; - }; +&dp { + status = "okay"; + samsung,color-space = <0>; + samsung,dynamic-range = <0>; + samsung,ycbcr-coeff = <0>; + samsung,color-depth = <1>; + samsung,link-rate = <0x0a>; + samsung,lane-count = <4>; +}; + +&fimd { + status = "okay"; + + display-timings { + native-mode = <&timing0>; + + timing0: timing@0 { + /* 2560x1600 DP panel */ + clock-frequency = <50000>; + hactive = <2560>; + vactive = <1600>; + hfront-porch = <48>; + hback-porch = <80>; + hsync-len = <32>; + vback-porch = <16>; + vfront-porch = <8>; + vsync-len = <6>; }; }; +}; - usb_hub_bus { - compatible = "simple-bus"; - #address-cells = <1>; - #size-cells = <0>; +&hdmi { + hpd-gpio = <&gpx3 7 GPIO_ACTIVE_LOW>; + vdd_osc-supply = <&ldo10_reg>; + vdd_pll-supply = <&ldo8_reg>; + vdd-supply = <&ldo8_reg>; +}; + +&i2c_0 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <20000>; + samsung,i2c-slave-addr = <0x66>; + + s5m8767_pmic@66 { + compatible = "samsung,s5m8767-pmic"; + reg = <0x66>; + interrupt-parent = <&gpx3>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + + vinb1-supply = <&main_dc_reg>; + vinb2-supply = <&main_dc_reg>; + vinb3-supply = <&main_dc_reg>; + vinb4-supply = <&main_dc_reg>; + vinb5-supply = <&main_dc_reg>; + vinb6-supply = <&main_dc_reg>; + vinb7-supply = <&main_dc_reg>; + vinb8-supply = <&main_dc_reg>; + vinb9-supply = <&main_dc_reg>; + + vinl1-supply = <&buck7_reg>; + vinl2-supply = <&buck7_reg>; + vinl3-supply = <&buck7_reg>; + vinl4-supply = <&main_dc_reg>; + vinl5-supply = <&main_dc_reg>; + vinl6-supply = <&main_dc_reg>; + vinl7-supply = <&main_dc_reg>; + vinl8-supply = <&buck8_reg>; + vinl9-supply = <&buck8_reg>; + + s5m8767,pmic-buck2-dvs-voltage = <1300000>; + s5m8767,pmic-buck3-dvs-voltage = <1100000>; + s5m8767,pmic-buck4-dvs-voltage = <1200000>; + s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 GPIO_ACTIVE_HIGH>, + <&gpd1 1 GPIO_ACTIVE_HIGH>, + <&gpd1 2 GPIO_ACTIVE_HIGH>; + s5m8767,pmic-buck-ds-gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>, + <&gpx2 4 GPIO_ACTIVE_HIGH>, + <&gpx2 5 GPIO_ACTIVE_HIGH>; + + regulators { + ldo1_reg: LDO1 { + regulator-name = "VDD_ALIVE_1.0V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo2_reg: LDO2 { + regulator-name = "VDD_28IO_DP_1.35V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo3_reg: LDO3 { + regulator-name = "VDD_COMMON1_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo4_reg: LDO4 { + regulator-name = "VDD_IOPERI_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; + }; - // SMSC USB3503 connected in hardware only mode as a PHY - usb_hub: usb_hub { - compatible = "smsc,usb3503a"; + ldo5_reg: LDO5 { + regulator-name = "VDD_EXT_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo6_reg: LDO6 { + regulator-name = "VDD_MPLL_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo7_reg: LDO7 { + regulator-name = "VDD_XPLL_1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo8_reg: LDO8 { + regulator-name = "VDD_COMMON2_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo9_reg: LDO9 { + regulator-name = "VDD_33ON_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + op_mode = <1>; + }; - reset-gpios = <&gpx3 5 1>; - connect-gpios = <&gpd1 7 1>; + ldo10_reg: LDO10 { + regulator-name = "VDD_COMMON3_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo11_reg: LDO11 { + regulator-name = "VDD_ABB2_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo12_reg: LDO12 { + regulator-name = "VDD_USB_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo13_reg: LDO13 { + regulator-name = "VDDQ_C2C_W_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo14_reg: LDO14 { + regulator-name = "VDD18_ABB0_3_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo15_reg: LDO15 { + regulator-name = "VDD10_COMMON4_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo16_reg: LDO16 { + regulator-name = "VDD18_HSIC_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo17_reg: LDO17 { + regulator-name = "VDDQ_MMC2_3_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo18_reg: LDO18 { + regulator-name = "VDD_33ON_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + op_mode = <1>; + }; + + ldo22_reg: LDO22 { + regulator-name = "EXT_33_OFF"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + op_mode = <1>; + }; + + ldo23_reg: LDO23 { + regulator-name = "EXT_28_OFF"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + op_mode = <1>; + }; + + ldo25_reg: LDO25 { + regulator-name = "PVDD_LDO25"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + op_mode = <1>; + }; + + ldo26_reg: LDO26 { + regulator-name = "EXT_18_OFF"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + op_mode = <1>; + }; + + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <912500>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + buck3_reg: BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + buck5_reg: BUCK5 { + regulator-name = "VDD_MEM_1.35V"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1355000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + buck7_reg: BUCK7 { + regulator-name = "PVDD_BUCK7"; + regulator-always-on; + op_mode = <1>; + }; + + buck8_reg: BUCK8 { + regulator-name = "PVDD_BUCK8"; + regulator-always-on; + op_mode = <1>; + }; + + buck9_reg: BUCK9 { + regulator-name = "VDD_33_OFF_EXT1"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3000000>; + op_mode = <1>; + }; }; }; +}; + +&i2c_2 { + status = "okay"; + + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + samsung,i2c-slave-addr = <0x50>; + + hdmiddc@50 { + compatible = "samsung,exynos4210-hdmiddc"; + reg = <0x50>; + }; +}; + +&i2c_3 { + status = "okay"; + + wm1811a@1a { + compatible = "wlf,wm1811"; + reg = <0x1a>; + + AVDD2-supply = <&main_dc_reg>; + CPVDD-supply = <&main_dc_reg>; + DBVDD1-supply = <&main_dc_reg>; + DBVDD2-supply = <&main_dc_reg>; + DBVDD3-supply = <&main_dc_reg>; + LDO1VDD-supply = <&main_dc_reg>; + SPKVDD1-supply = <&main_dc_reg>; + SPKVDD2-supply = <&main_dc_reg>; + + wlf,ldo1ena = <&gpb0 0 GPIO_ACTIVE_HIGH>; + wlf,ldo2ena = <&gpb0 1 GPIO_ACTIVE_HIGH>; + }; +}; + +&i2c_8 { + status = "okay"; + + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + samsung,i2c-slave-addr = <0x38>; + + hdmiphy@38 { + compatible = "samsung,exynos4212-hdmiphy"; + reg = <0x38>; + }; +}; - usb@12110000 { - usb-phy = <&usb2_phy>; +&i2c_9 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <40000>; + samsung,i2c-slave-addr = <0x38>; + + sata_phy_i2c:sata-phy@38 { + compatible = "samsung,exynos-sataphy-i2c"; + reg = <0x38>; }; }; + +&i2s0 { + status = "okay"; +}; + +&mfc { + samsung,mfc-r = <0x43000000 0x800000>; + samsung,mfc-l = <0x51000000 0x800000>; +}; + +&mmc_0 { + status = "okay"; + num-slots = <1>; + broken-cd; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + vmmc-supply = <&mmc_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; + bus-width = <8>; + cap-mmc-highspeed; +}; + +&mmc_2 { + status = "okay"; + num-slots = <1>; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + vmmc-supply = <&mmc_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; +}; + +&rtc { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&sata_phy { + status = "okay"; + samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>; +}; diff --git a/arch/arm/boot/dts/exynos5250-cros-common.dtsi b/arch/arm/boot/dts/exynos5250-cros-common.dtsi deleted file mode 100644 index e603e9c70142..000000000000 --- a/arch/arm/boot/dts/exynos5250-cros-common.dtsi +++ /dev/null @@ -1,164 +0,0 @@ -/* - * Common device tree include for all Exynos 5250 boards based off of Daisy. - * - * Copyright (c) 2012 Google, Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -/ { - aliases { - }; - - memory { - reg = <0x40000000 0x80000000>; - }; - - chosen { - }; - - pinctrl@11400000 { - /* - * Disabled pullups since external part has its own pullups and - * double-pulling gets us out of spec in some cases. - */ - i2c2_bus: i2c2-bus { - samsung,pin-pud = <0>; - }; - }; - - i2c@12C60000 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <378000>; - }; - - i2c@12C70000 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <378000>; - }; - - i2c@12C80000 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - - hdmiddc@50 { - compatible = "samsung,exynos4210-hdmiddc"; - reg = <0x50>; - }; - }; - - i2c@12C90000 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - }; - - i2c@12CA0000 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - }; - - i2c@12CB0000 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - }; - - i2c@12CD0000 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - }; - - i2c@12CE0000 { - status = "okay"; - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <378000>; - - hdmiphy: hdmiphy@38 { - compatible = "samsung,exynos4212-hdmiphy"; - reg = <0x38>; - }; - }; - - mmc@12200000 { - num-slots = <1>; - supports-highspeed; - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>; - - slot@0 { - reg = <0>; - bus-width = <8>; - }; - }; - - mmc@12220000 { - num-slots = <1>; - supports-highspeed; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - - slot@0 { - reg = <0>; - bus-width = <4>; - wp-gpios = <&gpc2 1 0>; - }; - }; - - mmc@12230000 { - num-slots = <1>; - supports-highspeed; - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - /* See board-specific dts files for pin setup */ - - slot@0 { - reg = <0>; - bus-width = <4>; - }; - }; - - spi_1: spi@12d30000 { - status = "okay"; - samsung,spi-src-clk = <0>; - num-cs = <1>; - }; - - hdmi { - hpd-gpio = <&gpx3 7 0>; - pinctrl-names = "default"; - pinctrl-0 = <&hdmi_hpd_irq>; - phy = <&hdmiphy>; - ddc = <&i2c_2>; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power { - label = "Power"; - gpios = <&gpx1 3 1>; - linux,code = <116>; /* KEY_POWER */ - gpio-key,wakeup; - }; - }; -}; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index b4b35adae565..bc27cc2558fe 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -7,9 +7,11 @@ * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. -*/ + */ /dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> #include "exynos5250.dtsi" / { @@ -27,165 +29,6 @@ bootargs = "root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC2,115200 init=/linuxrc"; }; - rtc@101E0000 { - status = "okay"; - }; - - i2c@12C60000 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <20000>; - status = "okay"; - - eeprom@50 { - compatible = "samsung,s524ad0xd1"; - reg = <0x50>; - }; - - max77686@09 { - compatible = "maxim,max77686"; - reg = <0x09>; - interrupt-parent = <&gpx3>; - interrupts = <2 0>; - - voltage-regulators { - ldo1_reg: LDO1 { - regulator-name = "P1.0V_LDO_OUT1"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - ldo2_reg: LDO2 { - regulator-name = "P1.2V_LDO_OUT2"; - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - }; - - ldo3_reg: LDO3 { - regulator-name = "P1.8V_LDO_OUT3"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - ldo4_reg: LDO4 { - regulator-name = "P2.8V_LDO_OUT4"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <2800000>; - }; - - ldo5_reg: LDO5 { - regulator-name = "P1.8V_LDO_OUT5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo6_reg: LDO6 { - regulator-name = "P1.1V_LDO_OUT6"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo7_reg: LDO7 { - regulator-name = "P1.1V_LDO_OUT7"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1100000>; - regulator-always-on; - }; - - ldo8_reg: LDO8 { - regulator-name = "P1.0V_LDO_OUT8"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - ldo10_reg: LDO10 { - regulator-name = "P1.8V_LDO_OUT10"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo11_reg: LDO11 { - regulator-name = "P1.8V_LDO_OUT11"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo12_reg: LDO12 { - regulator-name = "P3.0V_LDO_OUT12"; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - - ldo13_reg: LDO13 { - regulator-name = "P1.8V_LDO_OUT13"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo14_reg: LDO14 { - regulator-name = "P1.8V_LDO_OUT14"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - ldo15_reg: LDO15 { - regulator-name = "P1.0V_LDO_OUT15"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - }; - - ldo16_reg: LDO16 { - regulator-name = "P1.8V_LDO_OUT16"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - buck1_reg: BUCK1 { - regulator-name = "vdd_mif"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck2_reg: BUCK2 { - regulator-name = "vdd_arm"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - regulator-boot-on; - }; - - buck3_reg: BUCK3 { - regulator-name = "vdd_int"; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1200000>; - regulator-always-on; - regulator-boot-on; - }; - - buck4_reg: BUCK4 { - regulator-name = "vdd_g3d"; - regulator-min-microvolt = <850000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - buck5_reg: BUCK5 { - regulator-name = "P1.8V_BUCK_OUT5"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - }; - }; - }; - }; - vdd: fixed-regulator@0 { compatible = "regulator-fixed"; regulator-name = "vdd-supply"; @@ -210,207 +53,360 @@ regulator-always-on; }; - i2c@12C70000 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <20000>; - status = "okay"; + sound { + compatible = "samsung,smdk-wm8994"; - eeprom@51 { - compatible = "samsung,s524ad0xd1"; - reg = <0x51>; + samsung,i2s-controller = <&i2s0>; + samsung,audio-codec = <&wm8994>; + }; + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti"; + clock-frequency = <24000000>; }; - wm8994: wm8994@1a { - compatible = "wlf,wm8994"; - reg = <0x1a>; + codec_mclk: codec-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16934000>; + }; + }; +}; - gpio-controller; - #gpio-cells = <2>; +&dp { + samsung,color-space = <0>; + samsung,dynamic-range = <0>; + samsung,ycbcr-coeff = <0>; + samsung,color-depth = <1>; + samsung,link-rate = <0x0a>; + samsung,lane-count = <4>; + + pinctrl-names = "default"; + pinctrl-0 = <&dp_hpd>; + status = "okay"; +}; - clocks = <&codec_mclk>; - clock-names = "MCLK1"; +&ehci { + samsung,vbus-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>; +}; - AVDD2-supply = <&vdd>; - CPVDD-supply = <&vdd>; - DBVDD-supply = <&dbvdd>; - SPKVDD1-supply = <&spkvdd>; - SPKVDD2-supply = <&spkvdd>; +&fimd { + status = "okay"; + + display-timings { + native-mode = <&timing0>; + + timing0: timing@0 { + /* 1280x800 */ + clock-frequency = <50000>; + hactive = <1280>; + vactive = <800>; + hfront-porch = <4>; + hback-porch = <4>; + hsync-len = <4>; + vback-porch = <4>; + vfront-porch = <4>; + vsync-len = <4>; }; }; +}; - i2c@121D0000 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <40000>; - samsung,i2c-slave-addr = <0x38>; - status = "okay"; +&hdmi { + hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; +}; - sata_phy_i2c:sata-phy@38 { - compatible = "samsung,exynos-sataphy-i2c"; - reg = <0x38>; - }; +&i2c_0 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <20000>; + + eeprom@50 { + compatible = "samsung,s524ad0xd1"; + reg = <0x50>; }; - i2c@12C80000 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - status = "okay"; + max77686@09 { + compatible = "maxim,max77686"; + reg = <0x09>; + interrupt-parent = <&gpx3>; + interrupts = <2 IRQ_TYPE_NONE>; + + voltage-regulators { + ldo1_reg: LDO1 { + regulator-name = "P1.0V_LDO_OUT1"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; - hdmiddc@50 { - compatible = "samsung,exynos4210-hdmiddc"; - reg = <0x50>; - }; - }; + ldo2_reg: LDO2 { + regulator-name = "P1.2V_LDO_OUT2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; - i2c@12CE0000 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <66000>; - status = "okay"; + ldo3_reg: LDO3 { + regulator-name = "P1.8V_LDO_OUT3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; - hdmiphy@38 { - compatible = "samsung,exynos4212-hdmiphy"; - reg = <0x38>; - }; - }; + ldo4_reg: LDO4 { + regulator-name = "P2.8V_LDO_OUT4"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; - sata@122F0000 { - status = "okay"; - }; + ldo5_reg: LDO5 { + regulator-name = "P1.8V_LDO_OUT5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; - sata-phy@12170000 { - status = "okay"; - samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>; - }; + ldo6_reg: LDO6 { + regulator-name = "P1.1V_LDO_OUT6"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; - mmc@12200000 { - status = "okay"; - num-slots = <1>; - supports-highspeed; - broken-cd; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; - - slot@0 { - reg = <0>; - bus-width = <8>; - }; - }; + ldo7_reg: LDO7 { + regulator-name = "P1.1V_LDO_OUT7"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; - mmc@12220000 { - status = "okay"; - num-slots = <1>; - supports-highspeed; - card-detect-delay = <200>; - samsung,dw-mshc-ciu-div = <3>; - samsung,dw-mshc-sdr-timing = <2 3>; - samsung,dw-mshc-ddr-timing = <1 2>; - pinctrl-names = "default"; - pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - - slot@0 { - reg = <0>; - bus-width = <4>; - disable-wp; - }; - }; + ldo8_reg: LDO8 { + regulator-name = "P1.0V_LDO_OUT8"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + ldo10_reg: LDO10 { + regulator-name = "P1.8V_LDO_OUT10"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; - spi_1: spi@12d30000 { - cs-gpios = <&gpa2 5 0>; - status = "okay"; + ldo11_reg: LDO11 { + regulator-name = "P1.8V_LDO_OUT11"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; - w25q80bw@0 { - #address-cells = <1>; - #size-cells = <1>; - compatible = "w25x80"; - reg = <0>; - spi-max-frequency = <1000000>; + ldo12_reg: LDO12 { + regulator-name = "P3.0V_LDO_OUT12"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; - controller-data { - samsung,spi-feedback-delay = <0>; + ldo13_reg: LDO13 { + regulator-name = "P1.8V_LDO_OUT13"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; }; - partition@0 { - label = "U-Boot"; - reg = <0x0 0x40000>; - read-only; + ldo14_reg: LDO14 { + regulator-name = "P1.8V_LDO_OUT14"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; }; - partition@40000 { - label = "Kernel"; - reg = <0x40000 0xc0000>; + ldo15_reg: LDO15 { + regulator-name = "P1.0V_LDO_OUT15"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + + ldo16_reg: LDO16 { + regulator-name = "P1.8V_LDO_OUT16"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + buck3_reg: BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + buck5_reg: BUCK5 { + regulator-name = "P1.8V_BUCK_OUT5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; }; }; }; +}; - hdmi { - hpd-gpio = <&gpx3 7 0>; - }; +&i2c_1 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <20000>; - codec@11000000 { - samsung,mfc-r = <0x43000000 0x800000>; - samsung,mfc-l = <0x51000000 0x800000>; + eeprom@51 { + compatible = "samsung,s524ad0xd1"; + reg = <0x51>; }; - i2s0: i2s@03830000 { - status = "okay"; + wm8994: wm8994@1a { + compatible = "wlf,wm8994"; + reg = <0x1a>; + + gpio-controller; + #gpio-cells = <2>; + + clocks = <&codec_mclk>; + clock-names = "MCLK1"; + + AVDD2-supply = <&vdd>; + CPVDD-supply = <&vdd>; + DBVDD-supply = <&dbvdd>; + SPKVDD1-supply = <&spkvdd>; + SPKVDD2-supply = <&spkvdd>; }; +}; - sound { - compatible = "samsung,smdk-wm8994"; +&i2c_2 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; - samsung,i2s-controller = <&i2s0>; - samsung,audio-codec = <&wm8994>; + hdmiddc@50 { + compatible = "samsung,exynos4210-hdmiddc"; + reg = <0x50>; }; +}; + +&i2c_8 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; - usb@12110000 { - samsung,vbus-gpio = <&gpx2 6 0>; + hdmiphy@38 { + compatible = "samsung,exynos4212-hdmiphy"; + reg = <0x38>; }; +}; + +&i2c_9 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <40000>; + samsung,i2c-slave-addr = <0x38>; - dp-controller@145B0000 { - samsung,color-space = <0>; - samsung,dynamic-range = <0>; - samsung,ycbcr-coeff = <0>; - samsung,color-depth = <1>; - samsung,link-rate = <0x0a>; - samsung,lane-count = <4>; - - pinctrl-names = "default"; - pinctrl-0 = <&dp_hpd>; - status = "okay"; + sata_phy_i2c: sata-phy@38 { + compatible = "samsung,exynos-sataphy-i2c"; + reg = <0x38>; }; +}; - fimd@14400000 { - status = "okay"; - display-timings { - native-mode = <&timing0>; - timing0: timing@0 { - /* 1280x800 */ - clock-frequency = <50000>; - hactive = <1280>; - vactive = <800>; - hfront-porch = <4>; - hback-porch = <4>; - hsync-len = <4>; - vback-porch = <4>; - vfront-porch = <4>; - vsync-len = <4>; - }; +&i2s0 { + status = "okay"; +}; + +&mfc { + samsung,mfc-r = <0x43000000 0x800000>; + samsung,mfc-l = <0x51000000 0x800000>; +}; + +&mmc_0 { + status = "okay"; + num-slots = <1>; + broken-cd; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; + bus-width = <8>; + cap-mmc-highspeed; +}; + +&mmc_2 { + status = "okay"; + num-slots = <1>; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; +}; + +&rtc { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&sata_phy { + status = "okay"; + samsung,exynos-sataphy-i2c-phandle = <&sata_phy_i2c>; +}; + +&spi_1 { + status = "okay"; + cs-gpios = <&gpa2 5 GPIO_ACTIVE_HIGH>; + + w25q80bw@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "w25x80"; + reg = <0>; + spi-max-frequency = <1000000>; + + controller-data { + samsung,spi-feedback-delay = <0>; }; - }; - fixed-rate-clocks { - xxti { - compatible = "samsung,clock-xxti"; - clock-frequency = <24000000>; + partition@0 { + label = "U-Boot"; + reg = <0x0 0x40000>; + read-only; }; - codec_mclk: codec-mclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <16934000>; + partition@40000 { + label = "Kernel"; + reg = <0x40000 0xc0000>; }; }; }; diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts index f2b8c4116541..effaf2af41bc 100644 --- a/arch/arm/boot/dts/exynos5250-snow.dts +++ b/arch/arm/boot/dts/exynos5250-snow.dts @@ -6,11 +6,14 @@ * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. -*/ + */ /dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/maxim,max77686.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/input/input.h> #include "exynos5250.dtsi" -#include "exynos5250-cros-common.dtsi" / { model = "Google Snow"; @@ -20,82 +23,27 @@ i2c104 = &i2c_104; }; - rtc@101E0000 { - status = "okay"; + memory { + reg = <0x40000000 0x80000000>; }; - pinctrl@11400000 { - ec_irq: ec-irq { - samsung,pins = "gpx1-6"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - sd3_clk: sd3-clk { - samsung,pin-drv = <0>; - }; - - sd3_cmd: sd3-cmd { - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - sd3_bus4: sd3-bus-width4 { - samsung,pin-drv = <0>; - }; - - max98095_en: max98095-en { - samsung,pins = "gpx1-7"; - samsung,pin-function = <0>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - tps65090_irq: tps65090-irq { - samsung,pins = "gpx2-6"; - samsung,pin-function = <0>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - usb3_vbus_en: usb3-vbus-en { - samsung,pins = "gpx2-7"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; - - hdmi_hpd_irq: hdmi-hpd-irq { - samsung,pins = "gpx3-7"; - samsung,pin-function = <0>; - samsung,pin-pud = <1>; - samsung,pin-drv = <0>; - }; - }; - - pinctrl@13400000 { - arb_their_claim: arb-their-claim { - samsung,pins = "gpe0-4"; - samsung,pin-function = <0>; - samsung,pin-pud = <3>; - samsung,pin-drv = <0>; - }; - - arb_our_claim: arb-our-claim { - samsung,pins = "gpf0-3"; - samsung,pin-function = <1>; - samsung,pin-pud = <0>; - samsung,pin-drv = <0>; - }; + chosen { + bootargs = "console=tty1"; }; gpio-keys { compatible = "gpio-keys"; + power { + label = "Power"; + gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + gpio-key,wakeup; + }; + lid-switch { label = "Lid"; - gpios = <&gpx3 5 1>; + gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; linux,input-type = <5>; /* EV_SW */ linux,code = <0>; /* SW_LID */ debounce-interval = <1>; @@ -116,8 +64,8 @@ i2c-parent = <&{/i2c@12CA0000}>; - our-claim-gpio = <&gpf0 3 1>; - their-claim-gpios = <&gpe0 4 1>; + our-claim-gpio = <&gpf0 3 GPIO_ACTIVE_LOW>; + their-claim-gpios = <&gpe0 4 GPIO_ACTIVE_LOW>; slew-delay-us = <10>; wait-retry-us = <3000>; wait-free-us = <50000>; @@ -140,7 +88,7 @@ cros_ec: embedded-controller { compatible = "google,cros-ec-i2c"; reg = <0x1e>; - interrupts = <6 0>; + interrupts = <6 IRQ_TYPE_NONE>; interrupt-parent = <&gpx1>; pinctrl-names = "default"; pinctrl-0 = <&ec_irq>; @@ -181,7 +129,7 @@ dcdc3 { ti,enable-ext-control; }; - fet1 { + fet1: fet1 { regulator-name = "vcd_led"; ti,overcurrent-wait = <3>; }; @@ -204,7 +152,7 @@ regulator-always-on; ti,overcurrent-wait = <3>; }; - fet6 { + fet6: fet6 { regulator-name = "lcd_vdd"; ti,overcurrent-wait = <3>; }; @@ -226,39 +174,17 @@ }; }; - mmc@12200000 { - status = "okay"; - }; - - mmc@12220000 { - status = "okay"; - }; - - /* - * On Snow we've got SIP WiFi and so can keep drive strengths low to - * reduce EMI. - */ - mmc@12230000 { - status = "okay"; - slot@0 { - pinctrl-names = "default"; - pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>; - }; - }; - i2c@12CD0000 { - max98095: codec@11 { - compatible = "maxim,max98095"; - reg = <0x11>; - pinctrl-0 = <&max98095_en>; - pinctrl-names = "default"; + ptn3460: lvds-bridge@20 { + compatible = "nxp,ptn3460"; + reg = <0x20>; + powerdown-gpios = <&gpy2 5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpx1 5 GPIO_ACTIVE_HIGH>; + edid-emulation = <5>; + panel = <&panel>; }; }; - i2s0: i2s@03830000 { - status = "okay"; - }; - sound { compatible = "google,snow-audio-max98095"; @@ -272,20 +198,12 @@ regulator-name = "P5.0V_USB3CON"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpx2 7 0>; + gpio = <&gpx2 7 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&usb3_vbus_en>; enable-active-high; }; - phy@12100000 { - vbus-supply = <&usb3_vbus_reg>; - }; - - usb@12110000 { - samsung,vbus-gpio = <&gpx1 1 0>; - }; - fixed-rate-clocks { xxti { compatible = "samsung,clock-xxti"; @@ -293,62 +211,68 @@ }; }; - hdmi { - hdmi-en-supply = <&tps65090_fet7>; - vdd-supply = <&ldo8_reg>; - vdd_osc-supply = <&ldo10_reg>; - vdd_pll-supply = <&ldo8_reg>; - }; - - backlight { + backlight: backlight { compatible = "pwm-backlight"; pwms = <&pwm 0 1000000 0>; brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; default-brightness-level = <7>; + enable-gpios = <&gpx3 0 GPIO_ACTIVE_HIGH>; + power-supply = <&fet1>; pinctrl-0 = <&pwm0_out>; pinctrl-names = "default"; }; - fimd@14400000 { - status = "okay"; - samsung,invert-vclk; + panel: panel { + compatible = "auo,b116xw03"; + power-supply = <&fet6>; + backlight = <&backlight>; }; +}; - dp-controller@145B0000 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&dp_hpd>; - samsung,color-space = <0>; - samsung,dynamic-range = <0>; - samsung,ycbcr-coeff = <0>; - samsung,color-depth = <1>; - samsung,link-rate = <0x0a>; - samsung,lane-count = <2>; - samsung,hpd-gpio = <&gpx0 7 0>; - - display-timings { - native-mode = <&timing1>; - - timing1: timing@1 { - clock-frequency = <70589280>; - hactive = <1366>; - vactive = <768>; - hfront-porch = <40>; - hback-porch = <40>; - hsync-len = <32>; - vback-porch = <10>; - vfront-porch = <12>; - vsync-len = <6>; - }; - }; - }; +&dp { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dp_hpd>; + samsung,color-space = <0>; + samsung,dynamic-range = <0>; + samsung,ycbcr-coeff = <0>; + samsung,color-depth = <1>; + samsung,link-rate = <0x0a>; + samsung,lane-count = <2>; + samsung,hpd-gpio = <&gpx0 7 GPIO_ACTIVE_HIGH>; + bridge = <&ptn3460>; +}; + +&ehci { + samsung,vbus-gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; +}; + +&fimd { + status = "okay"; + samsung,invert-vclk; +}; + +&hdmi { + hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_hpd_irq>; + phy = <&hdmiphy>; + ddc = <&i2c_2>; + hdmi-en-supply = <&tps65090_fet7>; + vdd-supply = <&ldo8_reg>; + vdd_osc-supply = <&ldo10_reg>; + vdd_pll-supply = <&ldo8_reg>; }; &i2c_0 { - max77686@09 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <378000>; + + max77686: max77686@09 { compatible = "maxim,max77686"; interrupt-parent = <&gpx3>; - interrupts = <2 0>; + interrupts = <2 IRQ_TYPE_NONE>; pinctrl-names = "default"; pinctrl-0 = <&max77686_irq>; wakeup-source; @@ -491,22 +415,221 @@ }; &i2c_1 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <378000>; + trackpad { reg = <0x67>; compatible = "cypress,cyapa"; - interrupts = <2 0>; + interrupts = <2 IRQ_TYPE_NONE>; interrupt-parent = <&gpx1>; wakeup-source; }; }; +/* + * Disabled pullups since external part has its own pullups and + * double-pulling gets us out of spec in some cases. + */ +&i2c2_bus { + samsung,pin-pud = <0>; +}; + +&i2c_2 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + + hdmiddc@50 { + compatible = "samsung,exynos4210-hdmiddc"; + reg = <0x50>; + }; +}; + +&i2c_3 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; +}; + +&i2c_4 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; +}; + +&i2c_5 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; +}; + +&i2c_7 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + + max98095: codec@11 { + compatible = "maxim,max98095"; + reg = <0x11>; + pinctrl-0 = <&max98095_en>; + pinctrl-names = "default"; + }; +}; + +&i2c_8 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <378000>; + + hdmiphy: hdmiphy@38 { + compatible = "samsung,exynos4212-hdmiphy"; + reg = <0x38>; + }; +}; + +&i2s0 { + status = "okay"; +}; + +&mmc_0 { + status = "okay"; + num-slots = <1>; + broken-cd; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>; + bus-width = <8>; + cap-mmc-highspeed; +}; + +&mmc_2 { + status = "okay"; + num-slots = <1>; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; + bus-width = <4>; + wp-gpios = <&gpc2 1 GPIO_ACTIVE_HIGH>; + cap-sd-highspeed; +}; + +/* + * On Snow we've got SIP WiFi and so can keep drive strengths low to + * reduce EMI. + */ +&mmc_3 { + status = "okay"; + num-slots = <1>; + broken-cd; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>; + bus-width = <4>; + cap-sd-highspeed; +}; + &pinctrl_0 { + ec_irq: ec-irq { + samsung,pins = "gpx1-6"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + max98095_en: max98095-en { + samsung,pins = "gpx1-7"; + samsung,pin-function = <0>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + tps65090_irq: tps65090-irq { + samsung,pins = "gpx2-6"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + usb3_vbus_en: usb3-vbus-en { + samsung,pins = "gpx2-7"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + max77686_irq: max77686-irq { samsung,pins = "gpx3-2"; samsung,pin-function = <0>; samsung,pin-pud = <0>; samsung,pin-drv = <0>; }; + + hdmi_hpd_irq: hdmi-hpd-irq { + samsung,pins = "gpx3-7"; + samsung,pin-function = <0>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_1 { + arb_their_claim: arb-their-claim { + samsung,pins = "gpe0-4"; + samsung,pin-function = <0>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + arb_our_claim: arb-our-claim { + samsung,pins = "gpf0-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; +}; + +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>; + clock-names = "rtc", "rtc_src"; +}; + +&sd3_bus4 { + samsung,pin-drv = <0>; +}; + +&sd3_clk { + samsung,pin-drv = <0>; +}; + +&sd3_cmd { + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; +}; + +&spi_1 { + status = "okay"; + samsung,spi-src-clk = <0>; + num-cs = <1>; +}; + +&usbdrd_dwc3 { + dr_mode = "host"; +}; + +&usbdrd_phy { + vbus-supply = <&usb3_vbus_reg>; }; #include "cros-ec-keyboard.dtsi" diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts new file mode 100644 index 000000000000..f02775487cd4 --- /dev/null +++ b/arch/arm/boot/dts/exynos5250-spring.dts @@ -0,0 +1,566 @@ +/* + * Google Spring board device tree source + * + * Copyright (c) 2013 Google, Inc + * Copyright (c) 2014 SUSE LINUX Products GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/input/input.h> +#include "exynos5250.dtsi" + +/ { + model = "Google Spring"; + compatible = "google,spring", "samsung,exynos5250", "samsung,exynos5"; + + memory { + reg = <0x40000000 0x80000000>; + }; + + chosen { + bootargs = "console=tty1"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&power_key_irq>, <&lid_irq>; + + power { + label = "Power"; + gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + gpio-key,wakeup; + }; + + lid-switch { + label = "Lid"; + gpios = <&gpx3 5 GPIO_ACTIVE_LOW>; + linux,input-type = <5>; /* EV_SW */ + linux,code = <0>; /* SW_LID */ + debounce-interval = <1>; + gpio-key,wakeup; + }; + }; + + usb-hub { + compatible = "smsc,usb3503a"; + reset-gpios = <&gpe1 0 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&hsic_reset>; + }; + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti"; + clock-frequency = <24000000>; + }; + }; +}; + +&dp { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&dp_hpd_gpio>; + samsung,color-space = <0>; + samsung,dynamic-range = <0>; + samsung,ycbcr-coeff = <0>; + samsung,color-depth = <1>; + samsung,link-rate = <0x0a>; + samsung,lane-count = <1>; + samsung,hpd-gpio = <&gpc3 0 GPIO_ACTIVE_HIGH>; +}; + +&ehci { + samsung,vbus-gpio = <&gpx1 1 GPIO_ACTIVE_HIGH>; +}; + +&fimd { + status = "okay"; + samsung,invert-vclk; +}; + +&hdmi { + hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_hpd_irq>; + phy = <&hdmiphy>; + ddc = <&i2c_2>; + hdmi-en-supply = <&ldo8_reg>; + vdd-supply = <&ldo8_reg>; + vdd_osc-supply = <&ldo10_reg>; + vdd_pll-supply = <&ldo8_reg>; +}; + +&i2c_0 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <378000>; + + s5m8767-pmic@66 { + compatible = "samsung,s5m8767-pmic"; + reg = <0x66>; + interrupt-parent = <&gpx3>; + interrupts = <2 IRQ_TYPE_NONE>; + pinctrl-names = "default"; + pinctrl-0 = <&s5m8767_irq &s5m8767_dvs &s5m8767_ds>; + wakeup-source; + + s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>, /* DVS1 */ + <&gpd1 1 GPIO_ACTIVE_LOW>, /* DVS2 */ + <&gpd1 2 GPIO_ACTIVE_LOW>; /* DVS3 */ + + s5m8767,pmic-buck-ds-gpios = <&gpx2 3 GPIO_ACTIVE_LOW>, /* SET1 */ + <&gpx2 4 GPIO_ACTIVE_LOW>, /* SET2 */ + <&gpx2 5 GPIO_ACTIVE_LOW>; /* SET3 */ + + /* + * The following arrays of DVS voltages are not used, since we are + * not using GPIOs to control PMIC bucks, but they must be defined + * to please the driver. + */ + s5m8767,pmic-buck2-dvs-voltage = <1350000>, <1300000>, + <1250000>, <1200000>, + <1150000>, <1100000>, + <1000000>, <950000>; + + s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>, + <1100000>, <1100000>, + <1000000>, <1000000>, + <1000000>, <1000000>; + + s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>, + <1200000>, <1200000>; + + clocks { + compatible = "samsung,s5m8767-clk"; + #clock-cells = <1>; + clock-output-names = "en32khz_ap", + "en32khz_cp", + "en32khz_bt"; + }; + + regulators { + ldo4_reg: LDO4 { + regulator-name = "P1.0V_LDO_OUT4"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + op_mode = <0>; + }; + + ldo5_reg: LDO5 { + regulator-name = "P1.0V_LDO_OUT5"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + op_mode = <0>; + }; + + ldo6_reg: LDO6 { + regulator-name = "vdd_mydp"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + op_mode = <3>; + }; + + ldo7_reg: LDO7 { + regulator-name = "P1.1V_LDO_OUT7"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + op_mode = <3>; + }; + + ldo8_reg: LDO8 { + regulator-name = "P1.0V_LDO_OUT8"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + op_mode = <3>; + }; + + ldo10_reg: LDO10 { + regulator-name = "P1.8V_LDO_OUT10"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <3>; + }; + + ldo11_reg: LDO11 { + regulator-name = "P1.8V_LDO_OUT11"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <0>; + }; + + ldo12_reg: LDO12 { + regulator-name = "P3.0V_LDO_OUT12"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + op_mode = <3>; + }; + + ldo13_reg: LDO13 { + regulator-name = "P1.8V_LDO_OUT13"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <0>; + }; + + ldo14_reg: LDO14 { + regulator-name = "P1.8V_LDO_OUT14"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <3>; + }; + + ldo15_reg: LDO15 { + regulator-name = "P1.0V_LDO_OUT15"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + op_mode = <3>; + }; + + ldo16_reg: LDO16 { + regulator-name = "P1.8V_LDO_OUT16"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <3>; + }; + + ldo17_reg: LDO17 { + regulator-name = "P2.8V_LDO_OUT17"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + op_mode = <0>; + }; + + ldo25_reg: LDO25 { + regulator-name = "vdd_bridge"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + op_mode = <1>; + }; + + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + op_mode = <3>; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + op_mode = <3>; + }; + + buck3_reg: BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + op_mode = <3>; + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + regulator-boot-on; + op_mode = <3>; + }; + + buck5_reg: BUCK5 { + regulator-name = "P1.8V_BUCK_OUT5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + buck6_reg: BUCK6 { + regulator-name = "P1.2V_BUCK_OUT6"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + op_mode = <0>; + }; + + buck9_reg: BUCK9 { + regulator-name = "vdd_ummc"; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + op_mode = <3>; + }; + }; + }; +}; + +&i2c_1 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <378000>; + + trackpad@4b { + compatible = "atmel,maxtouch"; + reg = <0x4b>; + interrupt-parent = <&gpx1>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_irq>; + linux,gpio-keymap = <KEY_RESERVED + KEY_RESERVED + KEY_RESERVED + KEY_RESERVED + KEY_RESERVED + BTN_LEFT>; + wakeup-source; + }; +}; + +/* + * Disabled pullups since external part has its own pullups and + * double-pulling gets us out of spec in some cases. + */ +&i2c2_bus { + samsung,pin-pud = <0>; +}; + +&i2c_2 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + + hdmiddc@50 { + compatible = "samsung,exynos4210-hdmiddc"; + reg = <0x50>; + }; +}; + +&i2c_3 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; +}; + +&i2c_4 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + + cros_ec: embedded-controller { + compatible = "google,cros-ec-i2c"; + reg = <0x1e>; + interrupts = <6 IRQ_TYPE_NONE>; + interrupt-parent = <&gpx1>; + wakeup-source; + pinctrl-names = "default"; + pinctrl-0 = <&ec_irq>; + }; +}; + +&i2c_5 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; +}; + +&i2c_7 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <66000>; + + temperature-sensor@4c { + compatible = "gmt,g781"; + reg = <0x4c>; + }; +}; + +&i2c_8 { + status = "okay"; + samsung,i2c-sda-delay = <100>; + samsung,i2c-max-bus-freq = <378000>; + + hdmiphy: hdmiphy@38 { + compatible = "samsung,exynos4212-hdmiphy"; + reg = <0x38>; + }; +}; + +&i2s0 { + status = "okay"; +}; + +&mfc { + samsung,mfc-r = <0x43000000 0x800000>; + samsung,mfc-l = <0x51000000 0x800000>; +}; + +&mmc_0 { + status = "okay"; + num-slots = <1>; + supports-highspeed; + broken-cd; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4 &sd0_bus8>; + + slot@0 { + reg = <0>; + bus-width = <8>; + }; +}; + +/* + * On Spring we've got SIP WiFi and so can keep drive strengths low to + * reduce EMI. + */ +&mmc_1 { + status = "okay"; + num-slots = <1>; + supports-highspeed; + broken-cd; + card-detect-delay = <200>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-names = "default"; + pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; +}; + +&pinctrl_0 { + s5m8767_dvs: s5m8767-dvs { + samsung,pins = "gpd1-0", "gpd1-1", "gpd1-2"; + samsung,pin-function = <0>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; + + dp_hpd_gpio: dp-hpd-gpio { + samsung,pins = "gpc3-0"; + samsung,pin-function = <0>; + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; + }; + + trackpad_irq: trackpad-irq { + samsung,pins = "gpx1-2"; + samsung,pin-function = <0xf>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + power_key_irq: power-key-irq { + samsung,pins = "gpx1-3"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + ec_irq: ec-irq { + samsung,pins = "gpx1-6"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + s5m8767_ds: s5m8767-ds { + samsung,pins = "gpx2-3", "gpx2-4", "gpx2-5"; + samsung,pin-function = <0>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; + + s5m8767_irq: s5m8767-irq { + samsung,pins = "gpx3-2"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + lid_irq: lid-irq { + samsung,pins = "gpx3-5"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + hdmi_hpd_irq: hdmi-hpd-irq { + samsung,pins = "gpx3-7"; + samsung,pin-function = <0>; + samsung,pin-pud = <1>; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_1 { + hsic_reset: hsic-reset { + samsung,pins = "gpe1-0"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; +}; + +&sd1_bus4 { + samsung,pin-drv = <0>; +}; + +&sd1_cd { + samsung,pin-drv = <0>; +}; + +&sd1_clk { + samsung,pin-drv = <0>; +}; + +&sd1_cmd { + samsung,pin-pud = <3>; + samsung,pin-drv = <0>; +}; + +&spi_1 { + status = "okay"; + samsung,spi-src-clk = <0>; + num-cs = <1>; +}; + +#include "cros-ec-keyboard.dtsi" diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 492e1eff37bd..0a229fcd7acf 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -218,7 +218,7 @@ clock-names = "fimg2d"; }; - codec@11000000 { + mfc: codec@11000000 { compatible = "samsung,mfc-v6"; reg = <0x11000000 0x10000>; interrupts = <0 96 0>; @@ -227,7 +227,7 @@ clock-names = "mfc"; }; - rtc@101E0000 { + rtc: rtc@101E0000 { clocks = <&clock CLK_RTC>; clock-names = "rtc"; status = "disabled"; @@ -261,7 +261,7 @@ clock-names = "uart", "clk_uart_baud0"; }; - sata@122F0000 { + sata: sata@122F0000 { compatible = "snps,dwc-ahci"; samsung,sata-freq = <66>; reg = <0x122F0000 0x1ff>; @@ -293,6 +293,7 @@ clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c0_bus>; + samsung,sysreg-phandle = <&sysreg_system_controller>; status = "disabled"; }; @@ -306,6 +307,7 @@ clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c1_bus>; + samsung,sysreg-phandle = <&sysreg_system_controller>; status = "disabled"; }; @@ -319,6 +321,7 @@ clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c2_bus>; + samsung,sysreg-phandle = <&sysreg_system_controller>; status = "disabled"; }; @@ -332,6 +335,7 @@ clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c3_bus>; + samsung,sysreg-phandle = <&sysreg_system_controller>; status = "disabled"; }; @@ -555,7 +559,7 @@ #size-cells = <1>; ranges; - dwc3 { + usbdrd_dwc3: dwc3 { compatible = "synopsys,dwc3"; reg = <0x12000000 0x10000>; interrupts = <0 72 0>; @@ -573,7 +577,7 @@ #phy-cells = <1>; }; - usb@12110000 { + ehci: usb@12110000 { compatible = "samsung,exynos4210-ehci"; reg = <0x12110000 0x100>; interrupts = <0 71 0>; @@ -588,7 +592,7 @@ }; }; - usb@12120000 { + ohci: usb@12120000 { compatible = "samsung,exynos4210-ohci"; reg = <0x12120000 0x100>; interrupts = <0 71 0>; @@ -603,21 +607,6 @@ }; }; - usb2_phy: usbphy@12130000 { - compatible = "samsung,exynos5250-usb2phy"; - reg = <0x12130000 0x100>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_USB2>; - clock-names = "ext_xtal", "usbhost"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - usbphy-sys { - reg = <0x10040704 0x8>, - <0x10050230 0x4>; - }; - }; - usb2_phy_gen: phy@12130000 { compatible = "samsung,exynos5250-usb2-phy"; reg = <0x12130000 0x100>; @@ -725,7 +714,7 @@ clock-names = "gscl"; }; - hdmi { + hdmi: hdmi { compatible = "samsung,exynos4212-hdmi"; reg = <0x14530000 0x70000>; interrupts = <0 95 0>; @@ -751,26 +740,27 @@ #phy-cells = <0>; }; - dp-controller@145B0000 { + dp: dp-controller@145B0000 { clocks = <&clock CLK_DP>; clock-names = "dp"; phys = <&dp_phy>; phy-names = "dp"; }; - fimd@14400000 { + fimd: fimd@14400000 { clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; clock-names = "sclk_fimd", "fimd"; }; adc: adc@12D10000 { compatible = "samsung,exynos-adc-v1"; - reg = <0x12D10000 0x100>, <0x10040718 0x4>; + reg = <0x12D10000 0x100>; interrupts = <0 106 0>; clocks = <&clock CLK_ADC>; clock-names = "adc"; #io-channel-cells = <1>; io-channel-ranges; + samsung,syscon-phandle = <&pmu_system_controller>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/exynos5260-xyref5260.dts b/arch/arm/boot/dts/exynos5260-xyref5260.dts index 8c84ab27c19b..a803b605051b 100644 --- a/arch/arm/boot/dts/exynos5260-xyref5260.dts +++ b/arch/arm/boot/dts/exynos5260-xyref5260.dts @@ -69,7 +69,7 @@ num-slots = <1>; broken-cd; bypass-smu; - supports-highspeed; + cap-mmc-highspeed; supports-hs200-mode; /* 200 Mhz */ card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; @@ -77,27 +77,19 @@ samsung,dw-mshc-ddr-timing = <0 2>; pinctrl-names = "default"; pinctrl-0 = <&sd0_rdqs &sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>; - - slot@0 { - reg = <0>; - bus-width = <8>; - }; + bus-width = <8>; }; &mmc_2 { status = "okay"; num-slots = <1>; - supports-highspeed; + cap-sd-highspeed; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; - - slot@0 { - reg = <0>; - bus-width = <4>; - disable-wp; - }; + bus-width = <4>; + disable-wp; }; diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts index 7275bbd6fc4b..be3e02530b42 100644 --- a/arch/arm/boot/dts/exynos5410-smdk5410.dts +++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts @@ -40,33 +40,25 @@ &mmc_0 { status = "okay"; num-slots = <1>; - supports-highspeed; + cap-mmc-highspeed; broken-cd; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-ddr-timing = <1 2>; - - slot@0 { - reg = <0>; - bus-width = <8>; - }; + bus-width = <8>; }; &mmc_2 { status = "okay"; num-slots = <1>; - supports-highspeed; + cap-sd-highspeed; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-ddr-timing = <1 2>; - - slot@0 { - reg = <0>; - bus-width = <4>; - disable-wp; - }; + bus-width = <4>; + disable-wp; }; &uart0 { diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts index 434fd9d3e09d..aa7a7d727a7e 100644 --- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts +++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts @@ -50,7 +50,6 @@ mmc@12200000 { status = "okay"; broken-cd; - supports-highspeed; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; @@ -58,28 +57,22 @@ pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; vmmc-supply = <&ldo10_reg>; - - slot@0 { - reg = <0>; - bus-width = <8>; - }; + bus-width = <8>; + cap-mmc-highspeed; }; mmc@12220000 { status = "okay"; - supports-highspeed; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - vmmc-supply = <&ldo10_reg>; - - slot@0 { - reg = <0>; - bus-width = <4>; - }; + vmmc-supply = <&ldo19_reg>; + vqmmc-supply = <&ldo13_reg>; + bus-width = <4>; + cap-sd-highspeed; }; hsi2c_4: i2c@12CA0000 { @@ -375,3 +368,7 @@ }; }; }; + +&usbdrd_dwc3_1 { + dr_mode = "host"; +}; diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index 228a6b1e0aa1..9a050e19a4dc 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -11,6 +11,8 @@ /dts-v1/; #include <dt-bindings/input/input.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/clock/maxim,max77802.h> #include "exynos5420.dtsi" / { @@ -30,11 +32,12 @@ i2c20 = "/spi@12d40000/cros-ec@0/i2c-tunnel"; }; - backlight { + backlight: backlight { compatible = "pwm-backlight"; pwms = <&pwm 0 1000000 0>; brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; default-brightness-level = <7>; + power-supply = <&tps65090_fet1>; pinctrl-0 = <&pwm0_out>; pinctrl-names = "default"; }; @@ -100,6 +103,17 @@ regulator-boot-on; regulator-always-on; }; + + panel: panel { + compatible = "auo,b116xw03"; + power-supply = <&tps65090_fet6>; + backlight = <&backlight>; + }; +}; + +&adc { + status = "okay"; + vdd-supply = <&ldo9_reg>; }; &dp { @@ -113,22 +127,7 @@ samsung,link-rate = <0x06>; samsung,lane-count = <2>; samsung,hpd-gpio = <&gpx2 6 0>; - - display-timings { - native-mode = <&timing1>; - - timing1: timing@1 { - clock-frequency = <70589280>; - hactive = <1366>; - vactive = <768>; - hfront-porch = <40>; - hback-porch = <40>; - hsync-len = <32>; - vback-porch = <10>; - vfront-porch = <12>; - vsync-len = <6>; - }; - }; + bridge = <&ps8625>; }; &fimd { @@ -142,10 +141,348 @@ pinctrl-names = "default"; pinctrl-0 = <&hdmi_hpd_irq>; ddc = <&i2c_2>; + + hdmi-en-supply = <&tps65090_fet7>; + vdd-supply = <&ldo8_reg>; + vdd_osc-supply = <&ldo10_reg>; + vdd_pll-supply = <&ldo8_reg>; +}; + +&hsi2c_4 { + status = "okay"; + clock-frequency = <400000>; + + max77802: max77802-pmic@9 { + compatible = "maxim,max77802"; + interrupt-parent = <&gpx3>; + interrupts = <1 IRQ_TYPE_NONE>; + pinctrl-names = "default"; + pinctrl-0 = <&max77802_irq>, <&pmic_selb>, + <&pmic_dvs_1>, <&pmic_dvs_2>, <&pmic_dvs_3>; + wakeup-source; + reg = <0x9>; + #clock-cells = <1>; + + inb1-supply = <&tps65090_dcdc2>; + inb2-supply = <&tps65090_dcdc1>; + inb3-supply = <&tps65090_dcdc2>; + inb4-supply = <&tps65090_dcdc2>; + inb5-supply = <&tps65090_dcdc1>; + inb6-supply = <&tps65090_dcdc2>; + inb7-supply = <&tps65090_dcdc1>; + inb8-supply = <&tps65090_dcdc1>; + inb9-supply = <&tps65090_dcdc1>; + inb10-supply = <&tps65090_dcdc1>; + + inl1-supply = <&buck5_reg>; + inl2-supply = <&buck7_reg>; + inl3-supply = <&buck9_reg>; + inl4-supply = <&buck9_reg>; + inl5-supply = <&buck9_reg>; + inl6-supply = <&tps65090_dcdc2>; + inl7-supply = <&buck9_reg>; + inl9-supply = <&tps65090_dcdc2>; + inl10-supply = <&buck7_reg>; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12500>; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12500>; + }; + + buck3_reg: BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12500>; + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12500>; + }; + + buck5_reg: BUCK5 { + regulator-name = "vdd_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + buck6_reg: BUCK6 { + regulator-name = "vdd_kfc"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12500>; + }; + + buck7_reg: BUCK7 { + regulator-name = "vdd_1v35"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + buck8_reg: BUCK8 { + regulator-name = "vdd_emmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + regulator-boot-on; + }; + + buck9_reg: BUCK9 { + regulator-name = "vdd_2v"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + regulator-boot-on; + }; + + buck10_reg: BUCK10 { + regulator-name = "vdd_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "vdd_1v0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "vdd_1v2_2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo3_reg: LDO3 { + regulator-name = "vdd_1v8_3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vqmmc_sdcard: ldo4_reg: LDO4 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo5_reg: LDO5 { + regulator-name = "vdd_1v8_5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "vdd_1v8_6"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo7_reg: LDO7 { + regulator-name = "vdd_1v8_7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo8_reg: LDO8 { + regulator-name = "vdd_ldo8"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo9_reg: LDO9 { + regulator-name = "vdd_ldo9"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "vdd_ldo10"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo11_reg: LDO11 { + regulator-name = "vdd_ldo11"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo12_reg: LDO12 { + regulator-name = "vdd_ldo12"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + ldo13_reg: LDO13 { + regulator-name = "vdd_ldo13"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo14_reg: LDO14 { + regulator-name = "vdd_ldo14"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo15_reg: LDO15 { + regulator-name = "vdd_ldo15"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo17_reg: LDO17 { + regulator-name = "vdd_g3ds"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + }; + + ldo18_reg: LDO18 { + regulator-name = "ldo_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo19_reg: LDO19 { + regulator-name = "ldo_19"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo20_reg: LDO20 { + regulator-name = "ldo_20"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo21_reg: LDO21 { + regulator-name = "ldo_21"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo23_reg: LDO23 { + regulator-name = "ldo_23"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + ldo24_reg: LDO24 { + regulator-name = "ldo_24"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo25_reg: LDO25 { + regulator-name = "ldo_25"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo26_reg: LDO26 { + regulator-name = "ldo_26"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo27_reg: LDO27 { + regulator-name = "ldo_27"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo28_reg: LDO28 { + regulator-name = "ldo_28"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo29_reg: LDO29 { + regulator-name = "ldo_29"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo30_reg: LDO30 { + regulator-name = "vdd_mifs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo32_reg: LDO32 { + regulator-name = "ldo_32"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + ldo33_reg: LDO33 { + regulator-name = "ldo_33"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo34_reg: LDO34 { + regulator-name = "ldo_34"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + ldo35_reg: LDO35 { + regulator-name = "ldo_35"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + }; + }; }; &hsi2c_7 { status = "okay"; + clock-frequency = <400000>; max98090: codec@10 { compatible = "maxim,max98090"; @@ -155,6 +492,44 @@ pinctrl-names = "default"; pinctrl-0 = <&max98090_irq>; }; + + light-sensor@44 { + compatible = "isil,isl29018"; + reg = <0x44>; + vcc-supply = <&tps65090_fet5>; + }; + + ps8625: lvds-bridge@48 { + compatible = "parade,ps8625"; + reg = <0x48>; + sleep-gpios = <&gpx3 5 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpy7 7 GPIO_ACTIVE_HIGH>; + lane-count = <2>; + panel = <&panel>; + use-external-pwm; + }; +}; + +&hsi2c_8 { + status = "okay"; + clock-frequency = <333000>; + + /* Atmel mXT336S */ + trackpad@4b { + compatible = "atmel,maxtouch"; + reg = <0x4b>; + interrupt-parent = <&gpx1>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_irq>; + linux,gpio-keymap = <KEY_RESERVED + KEY_RESERVED + KEY_RESERVED /* GPIO0 */ + KEY_RESERVED /* GPIO1 */ + KEY_RESERVED /* GPIO2 */ + BTN_LEFT>; /* GPIO3 */ + }; }; &hsi2c_9 { @@ -186,8 +561,8 @@ status = "okay"; num-slots = <1>; broken-cd; - caps2-mmc-hs200-1_8v; - supports-highspeed; + mmc-hs200-1_8v; + cap-mmc-highspeed; non-removable; card-detect-delay = <200>; clock-frequency = <400000000>; @@ -196,17 +571,13 @@ samsung,dw-mshc-ddr-timing = <0 2>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; - - slot@0 { - reg = <0>; - bus-width = <8>; - }; + bus-width = <8>; }; &mmc_2 { status = "okay"; num-slots = <1>; - supports-highspeed; + cap-sd-highspeed; card-detect-delay = <200>; clock-frequency = <400000000>; samsung,dw-mshc-ciu-div = <3>; @@ -214,11 +585,7 @@ samsung,dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - - slot@0 { - reg = <0>; - bus-width = <4>; - }; + bus-width = <4>; }; @@ -249,6 +616,13 @@ samsung,pin-drv = <0>; }; + trackpad_irq: trackpad-irq { + samsung,pins = "gpx1-1"; + samsung,pin-function = <0xf>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + power_key_irq: power-key-irq { samsung,pins = "gpx1-2"; samsung,pin-function = <0>; @@ -277,12 +651,42 @@ samsung,pin-drv = <0>; }; + max77802_irq: max77802-irq { + samsung,pins = "gpx3-1"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + hdmi_hpd_irq: hdmi-hpd-irq { samsung,pins = "gpx3-7"; samsung,pin-function = <0>; samsung,pin-pud = <1>; samsung,pin-drv = <0>; }; + + pmic_dvs_1: pmic-dvs-1 { + samsung,pins = "gpy7-6"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_2 { + pmic_dvs_2: pmic-dvs-2 { + samsung,pins = "gpj4-2"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pmic_dvs_3: pmic-dvs-3 { + samsung,pins = "gpj4-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; }; &pinctrl_3 { @@ -312,10 +716,20 @@ samsung,pin-pud = <0>; samsung,pin-drv = <0>; }; + + pmic_selb: pmic-selb { + samsung,pins = "gph0-2", "gph0-3", "gph0-4", "gph0-5", + "gph0-6"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; }; &rtc { status = "okay"; + clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>; + clock-names = "rtc", "rtc_src"; }; &spi_2 { @@ -365,12 +779,12 @@ vsys2-supply = <&vbat>; vsys3-supply = <&vbat>; infet1-supply = <&vbat>; - infet2-supply = <&vbat>; - infet3-supply = <&vbat>; - infet4-supply = <&vbat>; - infet5-supply = <&vbat>; - infet6-supply = <&vbat>; - infet7-supply = <&vbat>; + infet2-supply = <&tps65090_dcdc1>; + infet3-supply = <&tps65090_dcdc2>; + infet4-supply = <&tps65090_dcdc2>; + infet5-supply = <&tps65090_dcdc2>; + infet6-supply = <&tps65090_dcdc2>; + infet7-supply = <&tps65090_dcdc1>; vsys-l1-supply = <&vbat>; vsys-l2-supply = <&vbat>; @@ -427,6 +841,14 @@ status = "okay"; }; +&usbdrd_dwc3_0 { + dr_mode = "host"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; +}; + &usbdrd_phy0 { vbus-supply = <&usb300_vbus_reg>; }; @@ -445,3 +867,4 @@ }; #include "cros-ec-keyboard.dtsi" +#include "cros-adc-thermistors.dtsi" diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts index 6052aa9c5659..8be3d7b489ff 100644 --- a/arch/arm/boot/dts/exynos5420-smdk5420.dts +++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts @@ -76,34 +76,26 @@ mmc@12200000 { status = "okay"; broken-cd; - supports-highspeed; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-ddr-timing = <0 2>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; - - slot@0 { - reg = <0>; - bus-width = <8>; - }; + bus-width = <8>; + cap-mmc-highspeed; }; mmc@12220000 { status = "okay"; - supports-highspeed; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <2 3>; samsung,dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - - slot@0 { - reg = <0>; - bus-width = <4>; - }; + bus-width = <4>; + cap-sd-highspeed; }; dp-controller@145B0000 { diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index bfe056d9148c..517e50f6760b 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -541,12 +541,13 @@ adc: adc@12D10000 { compatible = "samsung,exynos-adc-v2"; - reg = <0x12D10000 0x100>, <0x10040720 0x4>; + reg = <0x12D10000 0x100>; interrupts = <0 106 0>; clocks = <&clock CLK_TSADC>; clock-names = "adc"; #io-channel-cells = <1>; io-channel-ranges; + samsung,syscon-phandle = <&pmu_system_controller>; status = "disabled"; }; @@ -560,6 +561,7 @@ clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c0_bus>; + samsung,sysreg-phandle = <&sysreg_system_controller>; status = "disabled"; }; @@ -573,6 +575,7 @@ clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c1_bus>; + samsung,sysreg-phandle = <&sysreg_system_controller>; status = "disabled"; }; @@ -586,6 +589,7 @@ clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c2_bus>; + samsung,sysreg-phandle = <&sysreg_system_controller>; status = "disabled"; }; @@ -599,6 +603,7 @@ clock-names = "i2c"; pinctrl-names = "default"; pinctrl-0 = <&i2c3_bus>; + samsung,sysreg-phandle = <&sysreg_system_controller>; status = "disabled"; }; @@ -815,7 +820,7 @@ #size-cells = <1>; ranges; - dwc3 { + usbdrd_dwc3_0: dwc3 { compatible = "snps,dwc3"; reg = <0x12000000 0x10000>; interrupts = <0 72 0>; @@ -841,7 +846,7 @@ #size-cells = <1>; ranges; - dwc3 { + usbdrd_dwc3_1: dwc3 { compatible = "snps,dwc3"; reg = <0x12400000 0x10000>; interrupts = <0 73 0>; diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts index f3ee48bbe05f..e8fdda827fc9 100644 --- a/arch/arm/boot/dts/exynos5800-peach-pi.dts +++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts @@ -11,6 +11,8 @@ /dts-v1/; #include <dt-bindings/input/input.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/clock/maxim,max77802.h> #include "exynos5800.dtsi" / { @@ -28,11 +30,13 @@ i2c20 = "/spi@12d40000/cros-ec@0/i2c-tunnel"; }; - backlight { + backlight: backlight { compatible = "pwm-backlight"; pwms = <&pwm 0 1000000 0>; brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; default-brightness-level = <7>; + enable-gpios = <&gpx2 2 GPIO_ACTIVE_HIGH>; + power-supply = <&tps65090_fet1>; pinctrl-0 = <&pwm0_out>; pinctrl-names = "default"; }; @@ -98,6 +102,17 @@ regulator-boot-on; regulator-always-on; }; + + panel: panel { + compatible = "auo,b133htn01"; + power-supply = <&tps65090_fet6>; + backlight = <&backlight>; + }; +}; + +&adc { + status = "okay"; + vdd-supply = <&ldo9_reg>; }; &dp { @@ -111,22 +126,7 @@ samsung,link-rate = <0x0a>; samsung,lane-count = <2>; samsung,hpd-gpio = <&gpx2 6 0>; - - display-timings { - native-mode = <&timing1>; - - timing1: timing@1 { - clock-frequency = <150660000>; - hactive = <1920>; - vactive = <1080>; - hfront-porch = <60>; - hback-porch = <172>; - hsync-len = <80>; - vback-porch = <25>; - vfront-porch = <10>; - vsync-len = <10>; - }; - }; + panel = <&panel>; }; &fimd { @@ -140,10 +140,348 @@ pinctrl-names = "default"; pinctrl-0 = <&hdmi_hpd_irq>; ddc = <&i2c_2>; + + hdmi-en-supply = <&tps65090_fet7>; + vdd-supply = <&ldo8_reg>; + vdd_osc-supply = <&ldo10_reg>; + vdd_pll-supply = <&ldo8_reg>; +}; + +&hsi2c_4 { + status = "okay"; + clock-frequency = <400000>; + + max77802: max77802-pmic@9 { + compatible = "maxim,max77802"; + interrupt-parent = <&gpx3>; + interrupts = <1 IRQ_TYPE_NONE>; + pinctrl-names = "default"; + pinctrl-0 = <&max77802_irq>, <&pmic_selb>, + <&pmic_dvs_1>, <&pmic_dvs_2>, <&pmic_dvs_3>; + wakeup-source; + reg = <0x9>; + #clock-cells = <1>; + + inb1-supply = <&tps65090_dcdc2>; + inb2-supply = <&tps65090_dcdc1>; + inb3-supply = <&tps65090_dcdc2>; + inb4-supply = <&tps65090_dcdc2>; + inb5-supply = <&tps65090_dcdc1>; + inb6-supply = <&tps65090_dcdc2>; + inb7-supply = <&tps65090_dcdc1>; + inb8-supply = <&tps65090_dcdc1>; + inb9-supply = <&tps65090_dcdc1>; + inb10-supply = <&tps65090_dcdc1>; + + inl1-supply = <&buck5_reg>; + inl2-supply = <&buck7_reg>; + inl3-supply = <&buck9_reg>; + inl4-supply = <&buck9_reg>; + inl5-supply = <&buck9_reg>; + inl6-supply = <&tps65090_dcdc2>; + inl7-supply = <&buck9_reg>; + inl9-supply = <&tps65090_dcdc2>; + inl10-supply = <&buck7_reg>; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "vdd_mif"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12500>; + }; + + buck2_reg: BUCK2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12500>; + }; + + buck3_reg: BUCK3 { + regulator-name = "vdd_int"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12500>; + }; + + buck4_reg: BUCK4 { + regulator-name = "vdd_g3d"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12500>; + }; + + buck5_reg: BUCK5 { + regulator-name = "vdd_1v2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; + + buck6_reg: BUCK6 { + regulator-name = "vdd_kfc"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + regulator-ramp-delay = <12500>; + }; + + buck7_reg: BUCK7 { + regulator-name = "vdd_1v35"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + buck8_reg: BUCK8 { + regulator-name = "vdd_emmc"; + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + regulator-always-on; + regulator-boot-on; + }; + + buck9_reg: BUCK9 { + regulator-name = "vdd_2v"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2000000>; + regulator-always-on; + regulator-boot-on; + }; + + buck10_reg: BUCK10 { + regulator-name = "vdd_1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo1_reg: LDO1 { + regulator-name = "vdd_1v0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "vdd_1v2_2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo3_reg: LDO3 { + regulator-name = "vdd_1v8_3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + vqmmc_sdcard: ldo4_reg: LDO4 { + regulator-name = "vdd_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + }; + + ldo5_reg: LDO5 { + regulator-name = "vdd_1v8_5"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo6_reg: LDO6 { + regulator-name = "vdd_1v8_6"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo7_reg: LDO7 { + regulator-name = "vdd_1v8_7"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo8_reg: LDO8 { + regulator-name = "vdd_ldo8"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo9_reg: LDO9 { + regulator-name = "vdd_ldo9"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo10_reg: LDO10 { + regulator-name = "vdd_ldo10"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo11_reg: LDO11 { + regulator-name = "vdd_ldo11"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo12_reg: LDO12 { + regulator-name = "vdd_ldo12"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + }; + + ldo13_reg: LDO13 { + regulator-name = "vdd_ldo13"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo14_reg: LDO14 { + regulator-name = "vdd_ldo14"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo15_reg: LDO15 { + regulator-name = "vdd_ldo15"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo17_reg: LDO17 { + regulator-name = "vdd_g3ds"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + }; + + ldo18_reg: LDO18 { + regulator-name = "ldo_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo19_reg: LDO19 { + regulator-name = "ldo_19"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo20_reg: LDO20 { + regulator-name = "ldo_20"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + ldo21_reg: LDO21 { + regulator-name = "ldo_21"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo23_reg: LDO23 { + regulator-name = "ldo_23"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + ldo24_reg: LDO24 { + regulator-name = "ldo_24"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo25_reg: LDO25 { + regulator-name = "ldo_25"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo26_reg: LDO26 { + regulator-name = "ldo_26"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo27_reg: LDO27 { + regulator-name = "ldo_27"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + ldo28_reg: LDO28 { + regulator-name = "ldo_28"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo29_reg: LDO29 { + regulator-name = "ldo_29"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo30_reg: LDO30 { + regulator-name = "vdd_mifs"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo32_reg: LDO32 { + regulator-name = "ldo_32"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + ldo33_reg: LDO33 { + regulator-name = "ldo_33"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo34_reg: LDO34 { + regulator-name = "ldo_34"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + ldo35_reg: LDO35 { + regulator-name = "ldo_35"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + }; + }; }; &hsi2c_7 { status = "okay"; + clock-frequency = <400000>; max98091: codec@10 { compatible = "maxim,max98091"; @@ -153,6 +491,33 @@ pinctrl-names = "default"; pinctrl-0 = <&max98091_irq>; }; + + light-sensor@44 { + compatible = "isil,isl29018"; + reg = <0x44>; + vcc-supply = <&tps65090_fet5>; + }; +}; + +&hsi2c_8 { + status = "okay"; + clock-frequency = <333000>; + /* Atmel mXT540S */ + trackpad@4b { + compatible = "atmel,maxtouch"; + reg = <0x4b>; + interrupt-parent = <&gpx1>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; + pinctrl-names = "default"; + pinctrl-0 = <&trackpad_irq>; + linux,gpio-keymap = <KEY_RESERVED + KEY_RESERVED + KEY_RESERVED /* GPIO 0 */ + KEY_RESERVED /* GPIO 1 */ + BTN_LEFT /* GPIO 2 */ + KEY_RESERVED>; /* GPIO 3 */ + }; }; &hsi2c_9 { @@ -184,8 +549,8 @@ status = "okay"; num-slots = <1>; broken-cd; - caps2-mmc-hs200-1_8v; - supports-highspeed; + mmc-hs200-1_8v; + cap-mmc-highspeed; non-removable; card-detect-delay = <200>; clock-frequency = <400000000>; @@ -194,17 +559,13 @@ samsung,dw-mshc-ddr-timing = <0 2>; pinctrl-names = "default"; pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>; - - slot@0 { - reg = <0>; - bus-width = <8>; - }; + bus-width = <8>; }; &mmc_2 { status = "okay"; num-slots = <1>; - supports-highspeed; + cap-sd-highspeed; card-detect-delay = <200>; clock-frequency = <400000000>; samsung,dw-mshc-ciu-div = <3>; @@ -212,11 +573,7 @@ samsung,dw-mshc-ddr-timing = <1 2>; pinctrl-names = "default"; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>; - - slot@0 { - reg = <0>; - bus-width = <4>; - }; + bus-width = <4>; }; @@ -247,6 +604,13 @@ samsung,pin-drv = <0>; }; + trackpad_irq: trackpad-irq { + samsung,pins = "gpx1-1"; + samsung,pin-function = <0xf>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + power_key_irq: power-key-irq { samsung,pins = "gpx1-2"; samsung,pin-function = <0>; @@ -275,12 +639,42 @@ samsung,pin-drv = <0>; }; + max77802_irq: max77802-irq { + samsung,pins = "gpx3-1"; + samsung,pin-function = <0>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + hdmi_hpd_irq: hdmi-hpd-irq { samsung,pins = "gpx3-7"; samsung,pin-function = <0>; samsung,pin-pud = <1>; samsung,pin-drv = <0>; }; + + pmic_dvs_1: pmic-dvs-1 { + samsung,pins = "gpy7-6"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; +}; + +&pinctrl_2 { + pmic_dvs_2: pmic-dvs-2 { + samsung,pins = "gpj4-2"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; + + pmic_dvs_3: pmic-dvs-3 { + samsung,pins = "gpj4-3"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; }; &pinctrl_3 { @@ -310,10 +704,20 @@ samsung,pin-pud = <0>; samsung,pin-drv = <0>; }; + + pmic_selb: pmic-selb { + samsung,pins = "gph0-2", "gph0-3", "gph0-4", "gph0-5", + "gph0-6"; + samsung,pin-function = <1>; + samsung,pin-pud = <0>; + samsung,pin-drv = <0>; + }; }; &rtc { status = "okay"; + clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>; + clock-names = "rtc", "rtc_src"; }; &spi_2 { @@ -363,12 +767,12 @@ vsys2-supply = <&vbat>; vsys3-supply = <&vbat>; infet1-supply = <&vbat>; - infet2-supply = <&vbat>; - infet3-supply = <&vbat>; - infet4-supply = <&vbat>; - infet5-supply = <&vbat>; - infet6-supply = <&vbat>; - infet7-supply = <&vbat>; + infet2-supply = <&tps65090_dcdc1>; + infet3-supply = <&tps65090_dcdc2>; + infet4-supply = <&tps65090_dcdc2>; + infet5-supply = <&tps65090_dcdc2>; + infet6-supply = <&tps65090_dcdc2>; + infet7-supply = <&tps65090_dcdc1>; vsys-l1-supply = <&vbat>; vsys-l2-supply = <&vbat>; @@ -425,6 +829,14 @@ status = "okay"; }; +&usbdrd_dwc3_0 { + dr_mode = "host"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "host"; +}; + &usbdrd_phy0 { vbus-supply = <&usb300_vbus_reg>; }; @@ -443,3 +855,4 @@ }; #include "cros-ec-keyboard.dtsi" +#include "cros-adc-thermistors.dtsi" diff --git a/arch/arm/boot/dts/hip04-d01.dts b/arch/arm/boot/dts/hip04-d01.dts new file mode 100644 index 000000000000..40a9e33c2654 --- /dev/null +++ b/arch/arm/boot/dts/hip04-d01.dts @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2013-2014 Linaro Ltd. + * Author: Haojian Zhuang <haojian.zhuang@linaro.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ + +/dts-v1/; + +#include "hip04.dtsi" + +/ { + /* memory bus is 64-bit */ + #address-cells = <2>; + #size-cells = <2>; + model = "Hisilicon D01 Development Board"; + compatible = "hisilicon,hip04-d01"; + + memory@00000000,10000000 { + device_type = "memory"; + reg = <0x00000000 0x10000000 0x00000000 0xc0000000>, + <0x00000004 0xc0000000 0x00000003 0x40000000>; + }; + + soc { + uart0: uart@4007000 { + status = "ok"; + }; + }; +}; diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi new file mode 100644 index 000000000000..238814596a87 --- /dev/null +++ b/arch/arm/boot/dts/hip04.dtsi @@ -0,0 +1,984 @@ +/* + * Hisilicon Ltd. HiP04 SoC + * + * Copyright (C) 2013-2014 Hisilicon Ltd. + * Copyright (C) 2013-2014 Linaro Ltd. + * + * Author: Haojian Zhuang <haojian.zhuang@linaro.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/ { + /* memory bus is 64-bit */ + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + }; + + bootwrapper { + compatible = "hisilicon,hip04-bootwrapper"; + boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + core2 { + cpu = <&CPU2>; + }; + core3 { + cpu = <&CPU3>; + }; + }; + cluster1 { + core0 { + cpu = <&CPU4>; + }; + core1 { + cpu = <&CPU5>; + }; + core2 { + cpu = <&CPU6>; + }; + core3 { + cpu = <&CPU7>; + }; + }; + cluster2 { + core0 { + cpu = <&CPU8>; + }; + core1 { + cpu = <&CPU9>; + }; + core2 { + cpu = <&CPU10>; + }; + core3 { + cpu = <&CPU11>; + }; + }; + cluster3 { + core0 { + cpu = <&CPU12>; + }; + core1 { + cpu = <&CPU13>; + }; + core2 { + cpu = <&CPU14>; + }; + core3 { + cpu = <&CPU15>; + }; + }; + }; + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; + }; + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <1>; + }; + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <2>; + }; + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <3>; + }; + CPU4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x100>; + }; + CPU5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x101>; + }; + CPU6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x102>; + }; + CPU7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x103>; + }; + CPU8: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x200>; + }; + CPU9: cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x201>; + }; + CPU10: cpu@202 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x202>; + }; + CPU11: cpu@203 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x203>; + }; + CPU12: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x300>; + }; + CPU13: cpu@301 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x301>; + }; + CPU14: cpu@302 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x302>; + }; + CPU15: cpu@303 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x303>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupt-parent = <&gic>; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + }; + + clk_50m: clk_50m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <50000000>; + }; + + clk_168m: clk_168m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <168000000>; + }; + + clk_375m: clk_375m { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <375000000>; + }; + + soc { + /* It's a 32-bit SoC. */ + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges = <0 0 0xe0000000 0x10000000>; + + gic: interrupt-controller@c01000 { + compatible = "hisilicon,hip04-intc"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + interrupts = <1 9 0xf04>; + + reg = <0xc01000 0x1000>, <0xc02000 0x1000>, + <0xc04000 0x2000>, <0xc06000 0x2000>; + }; + + sysctrl: sysctrl { + compatible = "hisilicon,sysctrl"; + reg = <0x3e00000 0x00100000>; + }; + + fabric: fabric { + compatible = "hisilicon,hip04-fabric"; + reg = <0x302a000 0x1000>; + }; + + dual_timer0: dual_timer@3000000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x3000000 0x1000>; + interrupts = <0 224 4>; + clocks = <&clk_50m>, <&clk_50m>; + clock-names = "apb_pclk"; + }; + + arm-pmu { + compatible = "arm,cortex-a15-pmu"; + interrupts = <0 64 4>, + <0 65 4>, + <0 66 4>, + <0 67 4>, + <0 68 4>, + <0 69 4>, + <0 70 4>, + <0 71 4>, + <0 72 4>, + <0 73 4>, + <0 74 4>, + <0 75 4>, + <0 76 4>, + <0 77 4>, + <0 78 4>, + <0 79 4>; + }; + + uart0: uart@4007000 { + compatible = "snps,dw-apb-uart"; + reg = <0x4007000 0x1000>; + interrupts = <0 381 4>; + clocks = <&clk_168m>; + clock-names = "uartclk"; + reg-shift = <2>; + status = "disabled"; + }; + + sata0: sata@a000000 { + compatible = "hisilicon,hisi-ahci"; + reg = <0xa000000 0x1000000>; + interrupts = <0 372 4>; + }; + + }; + + etb@0,e3c42000 { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0 0xe3c42000 0 0x1000>; + + coresight-default-sink; + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + port { + etb0_in_port: endpoint@0 { + slave-mode; + remote-endpoint = <&replicator0_out_port0>; + }; + }; + }; + + etb@0,e3c82000 { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0 0xe3c82000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + port { + etb1_in_port: endpoint@0 { + slave-mode; + remote-endpoint = <&replicator1_out_port0>; + }; + }; + }; + + etb@0,e3cc2000 { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0 0xe3cc2000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + port { + etb2_in_port: endpoint@0 { + slave-mode; + remote-endpoint = <&replicator2_out_port0>; + }; + }; + }; + + etb@0,e3d02000 { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0 0xe3d02000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + port { + etb3_in_port: endpoint@0 { + slave-mode; + remote-endpoint = <&replicator3_out_port0>; + }; + }; + }; + + tpiu@0,e3c05000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0 0xe3c05000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + port { + tpiu_in_port: endpoint@0 { + slave-mode; + remote-endpoint = <&funnel4_out_port0>; + }; + }; + }; + + replicator0 { + /* non-configurable replicators don't show up on the + * AMBA bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-replicator"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* replicator output ports */ + port@0 { + reg = <0>; + replicator0_out_port0: endpoint { + remote-endpoint = <&etb0_in_port>; + }; + }; + + port@1 { + reg = <1>; + replicator0_out_port1: endpoint { + remote-endpoint = <&funnel4_in_port0>; + }; + }; + + /* replicator input port */ + port@2 { + reg = <0>; + replicator0_in_port0: endpoint { + slave-mode; + remote-endpoint = <&funnel0_out_port0>; + }; + }; + }; + }; + + replicator1 { + /* non-configurable replicators don't show up on the + * AMBA bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-replicator"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* replicator output ports */ + port@0 { + reg = <0>; + replicator1_out_port0: endpoint { + remote-endpoint = <&etb1_in_port>; + }; + }; + + port@1 { + reg = <1>; + replicator1_out_port1: endpoint { + remote-endpoint = <&funnel4_in_port1>; + }; + }; + + /* replicator input port */ + port@2 { + reg = <0>; + replicator1_in_port0: endpoint { + slave-mode; + remote-endpoint = <&funnel1_out_port0>; + }; + }; + }; + }; + + replicator2 { + /* non-configurable replicators don't show up on the + * AMBA bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-replicator"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* replicator output ports */ + port@0 { + reg = <0>; + replicator2_out_port0: endpoint { + remote-endpoint = <&etb2_in_port>; + }; + }; + + port@1 { + reg = <1>; + replicator2_out_port1: endpoint { + remote-endpoint = <&funnel4_in_port2>; + }; + }; + + /* replicator input port */ + port@2 { + reg = <0>; + replicator2_in_port0: endpoint { + slave-mode; + remote-endpoint = <&funnel2_out_port0>; + }; + }; + }; + }; + + replicator3 { + /* non-configurable replicators don't show up on the + * AMBA bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-replicator"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* replicator output ports */ + port@0 { + reg = <0>; + replicator3_out_port0: endpoint { + remote-endpoint = <&etb3_in_port>; + }; + }; + + port@1 { + reg = <1>; + replicator3_out_port1: endpoint { + remote-endpoint = <&funnel4_in_port3>; + }; + }; + + /* replicator input port */ + port@2 { + reg = <0>; + replicator3_in_port0: endpoint { + slave-mode; + remote-endpoint = <&funnel3_out_port0>; + }; + }; + }; + }; + + funnel@0,e3c41000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0xe3c41000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* funnel output port */ + port@0 { + reg = <0>; + funnel0_out_port0: endpoint { + remote-endpoint = + <&replicator0_in_port0>; + }; + }; + + /* funnel input ports */ + port@1 { + reg = <0>; + funnel0_in_port0: endpoint { + slave-mode; + remote-endpoint = <&ptm0_out_port>; + }; + }; + + port@2 { + reg = <1>; + funnel0_in_port1: endpoint { + slave-mode; + remote-endpoint = <&ptm1_out_port>; + }; + }; + + port@3 { + reg = <2>; + funnel0_in_port2: endpoint { + slave-mode; + remote-endpoint = <&ptm2_out_port>; + }; + }; + + port@4 { + reg = <3>; + funnel0_in_port3: endpoint { + slave-mode; + remote-endpoint = <&ptm3_out_port>; + }; + }; + }; + }; + + funnel@0,e3c81000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0xe3c81000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* funnel output port */ + port@0 { + reg = <0>; + funnel1_out_port0: endpoint { + remote-endpoint = + <&replicator1_in_port0>; + }; + }; + + /* funnel input ports */ + port@1 { + reg = <0>; + funnel1_in_port0: endpoint { + slave-mode; + remote-endpoint = <&ptm4_out_port>; + }; + }; + + port@2 { + reg = <1>; + funnel1_in_port1: endpoint { + slave-mode; + remote-endpoint = <&ptm5_out_port>; + }; + }; + + port@3 { + reg = <2>; + funnel1_in_port2: endpoint { + slave-mode; + remote-endpoint = <&ptm6_out_port>; + }; + }; + + port@4 { + reg = <3>; + funnel1_in_port3: endpoint { + slave-mode; + remote-endpoint = <&ptm7_out_port>; + }; + }; + }; + }; + + funnel@0,e3cc1000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0xe3cc1000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* funnel output port */ + port@0 { + reg = <0>; + funnel2_out_port0: endpoint { + remote-endpoint = + <&replicator2_in_port0>; + }; + }; + + /* funnel input ports */ + port@1 { + reg = <0>; + funnel2_in_port0: endpoint { + slave-mode; + remote-endpoint = <&ptm8_out_port>; + }; + }; + + port@2 { + reg = <1>; + funnel2_in_port1: endpoint { + slave-mode; + remote-endpoint = <&ptm9_out_port>; + }; + }; + + port@3 { + reg = <2>; + funnel2_in_port2: endpoint { + slave-mode; + remote-endpoint = <&ptm10_out_port>; + }; + }; + + port@4 { + reg = <3>; + funnel2_in_port3: endpoint { + slave-mode; + remote-endpoint = <&ptm11_out_port>; + }; + }; + }; + }; + + funnel@0,e3d01000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0xe3d01000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* funnel output port */ + port@0 { + reg = <0>; + funnel3_out_port0: endpoint { + remote-endpoint = + <&replicator3_in_port0>; + }; + }; + + /* funnel input ports */ + port@1 { + reg = <0>; + funnel3_in_port0: endpoint { + slave-mode; + remote-endpoint = <&ptm12_out_port>; + }; + }; + + port@2 { + reg = <1>; + funnel3_in_port1: endpoint { + slave-mode; + remote-endpoint = <&ptm13_out_port>; + }; + }; + + port@3 { + reg = <2>; + funnel3_in_port2: endpoint { + slave-mode; + remote-endpoint = <&ptm14_out_port>; + }; + }; + + port@4 { + reg = <3>; + funnel3_in_port3: endpoint { + slave-mode; + remote-endpoint = <&ptm15_out_port>; + }; + }; + }; + }; + + funnel@0,e3c04000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0xe3c04000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* funnel output port */ + port@0 { + reg = <0>; + funnel4_out_port0: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + + /* funnel input ports */ + port@1 { + reg = <0>; + funnel4_in_port0: endpoint { + slave-mode; + remote-endpoint = + <&replicator0_out_port1>; + }; + }; + + port@2 { + reg = <1>; + funnel4_in_port1: endpoint { + slave-mode; + remote-endpoint = + <&replicator1_out_port1>; + }; + }; + + port@3 { + reg = <2>; + funnel4_in_port2: endpoint { + slave-mode; + remote-endpoint = + <&replicator2_out_port1>; + }; + }; + + port@4 { + reg = <3>; + funnel4_in_port3: endpoint { + slave-mode; + remote-endpoint = + <&replicator3_out_port1>; + }; + }; + }; + }; + + ptm@0,e3c7c000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0xe3c7c000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + cpu = <&CPU0>; + port { + ptm0_out_port: endpoint { + remote-endpoint = <&funnel0_in_port0>; + }; + }; + }; + + ptm@0,e3c7d000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0xe3c7d000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + cpu = <&CPU1>; + port { + ptm1_out_port: endpoint { + remote-endpoint = <&funnel0_in_port1>; + }; + }; + }; + + ptm@0,e3c7e000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0xe3c7e000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + cpu = <&CPU2>; + port { + ptm2_out_port: endpoint { + remote-endpoint = <&funnel0_in_port2>; + }; + }; + }; + + ptm@0,e3c7f000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0xe3c7f000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + cpu = <&CPU3>; + port { + ptm3_out_port: endpoint { + remote-endpoint = <&funnel0_in_port3>; + }; + }; + }; + + ptm@0,e3cbc000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0xe3cbc000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + cpu = <&CPU4>; + port { + ptm4_out_port: endpoint { + remote-endpoint = <&funnel1_in_port0>; + }; + }; + }; + + ptm@0,e3cbd000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0xe3cbd000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + cpu = <&CPU5>; + port { + ptm5_out_port: endpoint { + remote-endpoint = <&funnel1_in_port1>; + }; + }; + }; + + ptm@0,e3cbe000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0xe3cbe000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + cpu = <&CPU6>; + port { + ptm6_out_port: endpoint { + remote-endpoint = <&funnel1_in_port2>; + }; + }; + }; + + ptm@0,e3cbf000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0xe3cbf000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + cpu = <&CPU7>; + port { + ptm7_out_port: endpoint { + remote-endpoint = <&funnel1_in_port3>; + }; + }; + }; + + ptm@0,e3cfc000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0xe3cfc000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + cpu = <&CPU8>; + port { + ptm8_out_port: endpoint { + remote-endpoint = <&funnel2_in_port0>; + }; + }; + }; + + ptm@0,e3cfd000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0xe3cfd000 0 0x1000>; + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + cpu = <&CPU9>; + port { + ptm9_out_port: endpoint { + remote-endpoint = <&funnel2_in_port1>; + }; + }; + }; + + ptm@0,e3cfe000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0xe3cfe000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + cpu = <&CPU10>; + port { + ptm10_out_port: endpoint { + remote-endpoint = <&funnel2_in_port2>; + }; + }; + }; + + ptm@0,e3cff000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0xe3cff000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + cpu = <&CPU11>; + port { + ptm11_out_port: endpoint { + remote-endpoint = <&funnel2_in_port3>; + }; + }; + }; + + ptm@0,e3d3c000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0xe3d3c000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + cpu = <&CPU12>; + port { + ptm12_out_port: endpoint { + remote-endpoint = <&funnel3_in_port0>; + }; + }; + }; + + ptm@0,e3d3d000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0xe3d3d000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + cpu = <&CPU13>; + port { + ptm13_out_port: endpoint { + remote-endpoint = <&funnel3_in_port1>; + }; + }; + }; + + ptm@0,e3d3e000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0xe3d3e000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + cpu = <&CPU14>; + port { + ptm14_out_port: endpoint { + remote-endpoint = <&funnel3_in_port2>; + }; + }; + }; + + ptm@0,e3d3f000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0xe3d3f000 0 0x1000>; + + clocks = <&clk_375m>; + clock-names = "apb_pclk"; + cpu = <&CPU15>; + port { + ptm15_out_port: endpoint { + remote-endpoint = <&funnel3_in_port3>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts index 05b44c272c9a..721b09238f58 100644 --- a/arch/arm/boot/dts/hisi-x5hd2-dkb.dts +++ b/arch/arm/boot/dts/hisi-x5hd2-dkb.dts @@ -51,3 +51,36 @@ &uart0 { status = "okay"; }; + +&gmac0 { + #address-cells = <1>; + #size-cells = <0>; + phy-handle = <&phy2>; + phy-mode = "mii"; + /* Placeholder, overwritten by bootloader */ + mac-address = [00 00 00 00 00 00]; + status = "okay"; + + phy2: ethernet-phy@2 { + reg = <2>; + }; +}; + +&gmac1 { + #address-cells = <1>; + #size-cells = <0>; + phy-handle = <&phy1>; + phy-mode = "rgmii"; + /* Placeholder, overwritten by bootloader */ + mac-address = [00 00 00 00 00 00]; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; +}; + +&ahci { + phys = <&sata_phy>; + phy-names = "sata-phy"; +}; diff --git a/arch/arm/boot/dts/hisi-x5hd2.dtsi b/arch/arm/boot/dts/hisi-x5hd2.dtsi index f85ba2924ff7..c52722b14e4a 100644 --- a/arch/arm/boot/dts/hisi-x5hd2.dtsi +++ b/arch/arm/boot/dts/hisi-x5hd2.dtsi @@ -131,6 +131,249 @@ clock-names = "apb_pclk"; status = "disabled"; }; + + gpio0: gpio@b20000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb20000 0x1000>; + interrupts = <0 108 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio1: gpio@b21000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb21000 0x1000>; + interrupts = <0 109 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio2: gpio@b22000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb22000 0x1000>; + interrupts = <0 110 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio3: gpio@b23000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb23000 0x1000>; + interrupts = <0 111 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio4: gpio@b24000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb24000 0x1000>; + interrupts = <0 112 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio5: gpio@004000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0x004000 0x1000>; + interrupts = <0 113 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio6: gpio@b26000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb26000 0x1000>; + interrupts = <0 114 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio7: gpio@b27000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb27000 0x1000>; + interrupts = <0 115 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio8: gpio@b28000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb28000 0x1000>; + interrupts = <0 116 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio9: gpio@b29000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb29000 0x1000>; + interrupts = <0 117 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio10: gpio@b2a000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb2a000 0x1000>; + interrupts = <0 118 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio11: gpio@b2b000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb2b000 0x1000>; + interrupts = <0 119 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio12: gpio@b2c000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb2c000 0x1000>; + interrupts = <0 120 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio13: gpio@b2d000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb2d000 0x1000>; + interrupts = <0 121 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio14: gpio@b2e000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb2e000 0x1000>; + interrupts = <0 122 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio15: gpio@b2f000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb2f000 0x1000>; + interrupts = <0 123 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio16: gpio@b30000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb30000 0x1000>; + interrupts = <0 124 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + gpio17: gpio@b31000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xb31000 0x1000>; + interrupts = <0 125 0x4>; + gpio-controller; + #gpio-cells = <2>; + clocks = <&clock HIX5HD2_FIXED_100M>; + clock-names = "apb_pclk"; + interrupt-controller; + #interrupt-cells = <2>; + status = "disabled"; + }; + + wdt0: watchdog@a2c000 { + compatible = "arm,sp805", "arm,primecell"; + arm,primecell-periphid = <0x00141805>; + reg = <0xa2c000 0x1000>; + interrupts = <0 29 4>; + clocks = <&clock HIX5HD2_WDG0_RST>; + clock-names = "apb_pclk"; + }; }; local_timer@00a00600 { @@ -148,9 +391,15 @@ }; sysctrl: system-controller@00000000 { - compatible = "hisilicon,sysctrl"; + compatible = "hisilicon,sysctrl", "syscon"; reg = <0x00000000 0x1000>; - reboot-offset = <0x4>; + }; + + reboot { + compatible = "syscon-reboot"; + regmap = <&sysctrl>; + offset = <0x4>; + mask = <0xdeadbeef>; }; cpuctrl@00a22000 { @@ -166,5 +415,142 @@ #clock-cells = <1>; }; }; + + /* unremovable emmc as mmcblk0 */ + mmc: mmc@1830000 { + compatible = "snps,dw-mshc"; + reg = <0x1830000 0x1000>; + interrupts = <0 35 4>; + clocks = <&clock HIX5HD2_MMC_CIU_RST>, + <&clock HIX5HD2_MMC_BIU_CLK>; + clock-names = "ciu", "biu"; + }; + + sd: mmc@1820000 { + compatible = "snps,dw-mshc"; + reg = <0x1820000 0x1000>; + interrupts = <0 34 4>; + clocks = <&clock HIX5HD2_SD_CIU_RST>, + <&clock HIX5HD2_SD_BIU_CLK>; + clock-names = "ciu","biu"; + }; + + gmac0: ethernet@1840000 { + compatible = "hisilicon,hix5hd2-gmac"; + reg = <0x1840000 0x1000>,<0x184300c 0x4>; + interrupts = <0 71 4>; + clocks = <&clock HIX5HD2_MAC0_CLK>; + status = "disabled"; + }; + + gmac1: ethernet@1841000 { + compatible = "hisilicon,hix5hd2-gmac"; + reg = <0x1841000 0x1000>,<0x1843010 0x4>; + interrupts = <0 72 4>; + clocks = <&clock HIX5HD2_MAC1_CLK>; + status = "disabled"; + }; + + usb0: ehci@1890000 { + compatible = "generic-ehci"; + reg = <0x1890000 0x1000>; + interrupts = <0 66 4>; + clocks = <&clock HIX5HD2_USB_CLK>; + }; + + usb1: ohci@1880000 { + compatible = "generic-ohci"; + reg = <0x1880000 0x1000>; + interrupts = <0 67 4>; + clocks = <&clock HIX5HD2_USB_CLK>; + }; + + peripheral_ctrl: syscon@a20000 { + compatible = "syscon"; + reg = <0xa20000 0x1000>; + }; + + sata_phy: phy@1900000 { + compatible = "hisilicon,hix5hd2-sata-phy"; + reg = <0x1900000 0x10000>; + #phy-cells = <0>; + hisilicon,peripheral-syscon = <&peripheral_ctrl>; + hisilicon,power-reg = <0x8 10>; + }; + + ahci: sata@1900000 { + compatible = "hisilicon,hisi-ahci"; + reg = <0x1900000 0x10000>; + interrupts = <0 70 4>; + clocks = <&clock HIX5HD2_SATA_CLK>; + }; + + ir: ir@001000 { + compatible = "hisilicon,hix5hd2-ir"; + reg = <0x001000 0x1000>; + interrupts = <0 47 4>; + clocks = <&clock HIX5HD2_FIXED_24M>; + hisilicon,power-syscon = <&sysctrl>; + }; + + i2c0: i2c@b10000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0xb10000 0x1000>; + interrupts = <0 38 4>; + clocks = <&clock HIX5HD2_I2C0_RST>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@b11000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0xb11000 0x1000>; + interrupts = <0 39 4>; + clocks = <&clock HIX5HD2_I2C1_RST>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@b12000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0xb12000 0x1000>; + interrupts = <0 40 4>; + clocks = <&clock HIX5HD2_I2C2_RST>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@b13000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0xb13000 0x1000>; + interrupts = <0 41 4>; + clocks = <&clock HIX5HD2_I2C3_RST>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@b16000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0xb16000 0x1000>; + interrupts = <0 43 4>; + clocks = <&clock HIX5HD2_I2C4_RST>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@b17000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0xb17000 0x1000>; + interrupts = <0 44 4>; + clocks = <&clock HIX5HD2_I2C5_RST>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/imx1-ads.dts b/arch/arm/boot/dts/imx1-ads.dts new file mode 100644 index 000000000000..af4eee5794aa --- /dev/null +++ b/arch/arm/boot/dts/imx1-ads.dts @@ -0,0 +1,152 @@ +/* + * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx1.dtsi" + +/ { + model = "Freescale MX1 ADS"; + compatible = "fsl,imx1ads", "fsl,imx1"; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x08000000 0x04000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + clk32 { + compatible = "fsl,imx-clk32", "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32000>; + }; + }; +}; + +&cspi1 { + pinctrl-0 = <&pinctrl_cspi1>; + fsl,spi-num-chipselects = <1>; + cs-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&i2c { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c>; + status = "okay"; + + extgpio0: pcf8575@22 { + compatible = "nxp,pcf8575"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + extgpio1: pcf8575@24 { + compatible = "nxp,pcf8575"; + reg = <0x24>; + gpio-controller; + #gpio-cells = <2>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&weim { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_weim>; + status = "okay"; + + nor: nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0x00000000 0x02000000>; + bank-width = <4>; + fsl,weim-cs-timing = <0x00003e00 0x00000801>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&iomuxc { + imx1-ads { + pinctrl_cspi1: cspi1grp { + fsl,pins = < + MX1_PAD_SPI1_MISO__SPI1_MISO 0x0 + MX1_PAD_SPI1_MOSI__SPI1_MOSI 0x0 + MX1_PAD_SPI1_RDY__SPI1_RDY 0x0 + MX1_PAD_SPI1_SCLK__SPI1_SCLK 0x0 + MX1_PAD_SPI1_SS__GPIO3_15 0x0 + >; + }; + + pinctrl_i2c: i2cgrp { + fsl,pins = < + MX1_PAD_I2C_SCL__I2C_SCL 0x0 + MX1_PAD_I2C_SDA__I2C_SDA 0x0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX1_PAD_UART1_TXD__UART1_TXD 0x0 + MX1_PAD_UART1_RXD__UART1_RXD 0x0 + MX1_PAD_UART1_CTS__UART1_CTS 0x0 + MX1_PAD_UART1_RTS__UART1_RTS 0x0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX1_PAD_UART2_TXD__UART2_TXD 0x0 + MX1_PAD_UART2_RXD__UART2_RXD 0x0 + MX1_PAD_UART2_CTS__UART2_CTS 0x0 + MX1_PAD_UART2_RTS__UART2_RTS 0x0 + >; + }; + + pinctrl_weim: weimgrp { + fsl,pins = < + MX1_PAD_A0__A0 0x0 + MX1_PAD_A16__A16 0x0 + MX1_PAD_A17__A17 0x0 + MX1_PAD_A18__A18 0x0 + MX1_PAD_A19__A19 0x0 + MX1_PAD_A20__A20 0x0 + MX1_PAD_A21__A21 0x0 + MX1_PAD_A22__A22 0x0 + MX1_PAD_A23__A23 0x0 + MX1_PAD_A24__A24 0x0 + MX1_PAD_BCLK__BCLK 0x0 + MX1_PAD_CS4__CS4 0x0 + MX1_PAD_DTACK__DTACK 0x0 + MX1_PAD_ECB__ECB 0x0 + MX1_PAD_LBA__LBA 0x0 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx1-apf9328.dts b/arch/arm/boot/dts/imx1-apf9328.dts new file mode 100644 index 000000000000..07d92fb40e6f --- /dev/null +++ b/arch/arm/boot/dts/imx1-apf9328.dts @@ -0,0 +1,129 @@ +/* + * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "imx1.dtsi" + +/ { + model = "Armadeus APF9328"; + compatible = "armadeus,imx1-apf9328", "fsl,imx1"; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x08000000 0x00800000>; + }; +}; + +&i2c { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +&weim { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_weim>; + status = "okay"; + + nor: nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0x00000000 0x02000000>; + bank-width = <2>; + fsl,weim-cs-timing = <0x00330e04 0x00000d01>; + #address-cells = <1>; + #size-cells = <1>; + }; + + eth: eth@4,c00000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eth>; + compatible = "davicom,dm9000"; + reg = < + 4 0x00c00000 0x2 + 4 0x00c00002 0x2 + >; + interrupt-parent = <&gpio2>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + fsl,weim-cs-timing = <0x0000c700 0x19190d01>; + }; +}; + +&iomuxc { + imx1-apf9328 { + pinctrl_eth: ethgrp { + fsl,pins = < + MX1_PAD_SIM_SVEN__GPIO2_14 0x0 + >; + }; + + pinctrl_i2c: i2cgrp { + fsl,pins = < + MX1_PAD_I2C_SCL__I2C_SCL 0x0 + MX1_PAD_I2C_SDA__I2C_SDA 0x0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX1_PAD_UART1_TXD__UART1_TXD 0x0 + MX1_PAD_UART1_RXD__UART1_RXD 0x0 + MX1_PAD_UART1_CTS__UART1_CTS 0x0 + MX1_PAD_UART1_RTS__UART1_RTS 0x0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX1_PAD_UART2_TXD__UART2_TXD 0x0 + MX1_PAD_UART2_RXD__UART2_RXD 0x0 + MX1_PAD_UART2_CTS__UART2_CTS 0x0 + MX1_PAD_UART2_RTS__UART2_RTS 0x0 + >; + }; + + pinctrl_weim: weimgrp { + fsl,pins = < + MX1_PAD_A0__A0 0x0 + MX1_PAD_A16__A16 0x0 + MX1_PAD_A17__A17 0x0 + MX1_PAD_A18__A18 0x0 + MX1_PAD_A19__A19 0x0 + MX1_PAD_A20__A20 0x0 + MX1_PAD_A21__A21 0x0 + MX1_PAD_A22__A22 0x0 + MX1_PAD_A23__A23 0x0 + MX1_PAD_A24__A24 0x0 + MX1_PAD_BCLK__BCLK 0x0 + MX1_PAD_CS4__CS4 0x0 + MX1_PAD_DTACK__DTACK 0x0 + MX1_PAD_ECB__ECB 0x0 + MX1_PAD_LBA__LBA 0x0 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx1-pinfunc.h b/arch/arm/boot/dts/imx1-pinfunc.h new file mode 100644 index 000000000000..22bec8b87680 --- /dev/null +++ b/arch/arm/boot/dts/imx1-pinfunc.h @@ -0,0 +1,302 @@ +/* + * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#ifndef __DTS_IMX1_PINFUNC_H +#define __DTS_IMX1_PINFUNC_H + +/* + * The pin function ID is a tuple of + * <pin mux_id> + * mux_id consists of + * function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10) + * + * function: 0 - Primary function + * 1 - Alternate function + * 2 - GPIO + * direction: 0 - Input + * 1 - Output + * gpio_oconf: 0 - A_IN + * 1 - B_IN + * 2 - A_OUT + * 3 - Data Register + * gpio_iconfa/b: 0 - GPIO_IN + * 1 - Interrupt Status Register + * 2 - 0 + * 3 - 1 + * + * 'pin' is an integer between 0 and 0xbf. i.MX1 has 4 ports with 32 configurable + * configurable pins each. 'pin' is PORT * 32 + PORT_PIN, PORT_PIN is the pin + * number on the specific port (between 0 and 31). + */ + +#define MX1_PAD_A24__A24 0x00 0x004 +#define MX1_PAD_A24__GPIO1_0 0x00 0x032 +#define MX1_PAD_A24__SPI2_CLK 0x00 0x006 +#define MX1_PAD_TIN__TIN 0x01 0x000 +#define MX1_PAD_TIN__GPIO1_1 0x01 0x032 +#define MX1_PAD_TIN__SPI2_RXD 0x01 0x022 +#define MX1_PAD_PWMO__PWMO 0x02 0x004 +#define MX1_PAD_PWMO__GPIO1_2 0x02 0x032 +#define MX1_PAD_CSI_MCLK__CSI_MCLK 0x03 0x004 +#define MX1_PAD_CSI_MCLK__GPIO1_3 0x03 0x032 +#define MX1_PAD_CSI_D0__CSI_D0 0x04 0x000 +#define MX1_PAD_CSI_D0__GPIO1_4 0x04 0x032 +#define MX1_PAD_CSI_D1__CSI_D1 0x05 0x000 +#define MX1_PAD_CSI_D1__GPIO1_5 0x05 0x032 +#define MX1_PAD_CSI_D2__CSI_D2 0x06 0x000 +#define MX1_PAD_CSI_D2__GPIO1_6 0x06 0x032 +#define MX1_PAD_CSI_D3__CSI_D3 0x07 0x000 +#define MX1_PAD_CSI_D3__GPIO1_7 0x07 0x032 +#define MX1_PAD_CSI_D4__CSI_D4 0x08 0x000 +#define MX1_PAD_CSI_D4__GPIO1_8 0x08 0x032 +#define MX1_PAD_CSI_D5__CSI_D5 0x09 0x000 +#define MX1_PAD_CSI_D5__GPIO1_9 0x09 0x032 +#define MX1_PAD_CSI_D6__CSI_D6 0x0a 0x000 +#define MX1_PAD_CSI_D6__GPIO1_10 0x0a 0x032 +#define MX1_PAD_CSI_D7__CSI_D7 0x0b 0x000 +#define MX1_PAD_CSI_D7__GPIO1_11 0x0b 0x032 +#define MX1_PAD_CSI_VSYNC__CSI_VSYNC 0x0c 0x000 +#define MX1_PAD_CSI_VSYNC__GPIO1_12 0x0c 0x032 +#define MX1_PAD_CSI_HSYNC__CSI_HSYNC 0x0d 0x000 +#define MX1_PAD_CSI_HSYNC__GPIO1_13 0x0d 0x032 +#define MX1_PAD_CSI_PIXCLK__CSI_PIXCLK 0x0e 0x000 +#define MX1_PAD_CSI_PIXCLK__GPIO1_14 0x0e 0x032 +#define MX1_PAD_I2C_SDA__I2C_SDA 0x0f 0x000 +#define MX1_PAD_I2C_SDA__GPIO1_15 0x0f 0x032 +#define MX1_PAD_I2C_SCL__I2C_SCL 0x10 0x004 +#define MX1_PAD_I2C_SCL__GPIO1_16 0x10 0x032 +#define MX1_PAD_DTACK__DTACK 0x11 0x000 +#define MX1_PAD_DTACK__GPIO1_17 0x11 0x032 +#define MX1_PAD_DTACK__SPI2_SS 0x11 0x002 +#define MX1_PAD_DTACK__A25 0x11 0x016 +#define MX1_PAD_BCLK__BCLK 0x12 0x004 +#define MX1_PAD_BCLK__GPIO1_18 0x12 0x032 +#define MX1_PAD_LBA__LBA 0x13 0x004 +#define MX1_PAD_LBA__GPIO1_19 0x13 0x032 +#define MX1_PAD_ECB__ECB 0x14 0x000 +#define MX1_PAD_ECB__GPIO1_20 0x14 0x032 +#define MX1_PAD_A0__A0 0x15 0x004 +#define MX1_PAD_A0__GPIO1_21 0x15 0x032 +#define MX1_PAD_CS4__CS4 0x16 0x004 +#define MX1_PAD_CS4__GPIO1_22 0x16 0x032 +#define MX1_PAD_CS5__CS5 0x17 0x004 +#define MX1_PAD_CS5__GPIO1_23 0x17 0x032 +#define MX1_PAD_A16__A16 0x18 0x004 +#define MX1_PAD_A16__GPIO1_24 0x18 0x032 +#define MX1_PAD_A17__A17 0x19 0x004 +#define MX1_PAD_A17__GPIO1_25 0x19 0x032 +#define MX1_PAD_A18__A18 0x1a 0x004 +#define MX1_PAD_A18__GPIO1_26 0x1a 0x032 +#define MX1_PAD_A19__A19 0x1b 0x004 +#define MX1_PAD_A19__GPIO1_27 0x1b 0x032 +#define MX1_PAD_A20__A20 0x1c 0x004 +#define MX1_PAD_A20__GPIO1_28 0x1c 0x032 +#define MX1_PAD_A21__A21 0x1d 0x004 +#define MX1_PAD_A21__GPIO1_29 0x1d 0x032 +#define MX1_PAD_A22__A22 0x1e 0x004 +#define MX1_PAD_A22__GPIO1_30 0x1e 0x032 +#define MX1_PAD_A23__A23 0x1f 0x004 +#define MX1_PAD_A23__GPIO1_31 0x1f 0x032 +#define MX1_PAD_SD_DAT0__SD_DAT0 0x28 0x000 +#define MX1_PAD_SD_DAT0__MS_PI0 0x28 0x001 +#define MX1_PAD_SD_DAT0__GPIO2_8 0x28 0x032 +#define MX1_PAD_SD_DAT1__SD_DAT1 0x29 0x000 +#define MX1_PAD_SD_DAT1__MS_PI1 0x29 0x001 +#define MX1_PAD_SD_DAT1__GPIO2_9 0x29 0x032 +#define MX1_PAD_SD_DAT2__SD_DAT2 0x2a 0x000 +#define MX1_PAD_SD_DAT2__MS_SCLKI 0x2a 0x001 +#define MX1_PAD_SD_DAT2__GPIO2_10 0x2a 0x032 +#define MX1_PAD_SD_DAT3__SD_DAT3 0x2b 0x000 +#define MX1_PAD_SD_DAT3__MS_SDIO 0x2b 0x001 +#define MX1_PAD_SD_DAT3__GPIO2_11 0x2b 0x032 +#define MX1_PAD_SD_SCLK__SD_SCLK 0x2c 0x004 +#define MX1_PAD_SD_SCLK__MS_SCLKO 0x2c 0x005 +#define MX1_PAD_SD_SCLK__GPIO2_12 0x2c 0x032 +#define MX1_PAD_SD_CMD__SD_CMD 0x2d 0x000 +#define MX1_PAD_SD_CMD__MS_BS 0x2d 0x005 +#define MX1_PAD_SD_CMD__GPIO2_13 0x2d 0x032 +#define MX1_PAD_SIM_SVEN__SIM_SVEN 0x2e 0x004 +#define MX1_PAD_SIM_SVEN__SSI_RXFS 0x2e 0x001 +#define MX1_PAD_SIM_SVEN__GPIO2_14 0x2e 0x032 +#define MX1_PAD_SIM_PD__SIM_PD 0x2f 0x000 +#define MX1_PAD_SIM_PD__SSI_RXCLK 0x2f 0x001 +#define MX1_PAD_SIM_PD__GPIO2_15 0x2f 0x032 +#define MX1_PAD_SIM_TX__SIM_TX 0x30 0x000 +#define MX1_PAD_SIM_TX__SSI_RXDAT 0x30 0x001 +#define MX1_PAD_SIM_TX__GPIO2_16 0x30 0x032 +#define MX1_PAD_SIM_RX__SIM_RX 0x31 0x000 +#define MX1_PAD_SIM_RX__SSI_TXDAT 0x31 0x005 +#define MX1_PAD_SIM_RX__GPIO2_17 0x31 0x032 +#define MX1_PAD_SIM_RST__SIM_RST 0x32 0x004 +#define MX1_PAD_SIM_RST__SSI_TXFS 0x32 0x001 +#define MX1_PAD_SIM_RST__GPIO2_18 0x32 0x032 +#define MX1_PAD_SIM_CLK__SIM_CLK 0x33 0x004 +#define MX1_PAD_SIM_CLK__SSI_TXCLK 0x33 0x001 +#define MX1_PAD_SIM_CLK__GPIO2_19 0x33 0x032 +#define MX1_PAD_USBD_AFE__USBD_AFE 0x34 0x004 +#define MX1_PAD_USBD_AFE__GPIO2_20 0x34 0x032 +#define MX1_PAD_USBD_OE__USBD_OE 0x35 0x004 +#define MX1_PAD_USBD_OE__GPIO2_21 0x35 0x032 +#define MX1_PAD_USBD_RCV__USBD_RCV 0x36 0x000 +#define MX1_PAD_USBD_RCV__GPIO2_22 0x36 0x032 +#define MX1_PAD_USBD_SUSPND__USBD_SUSPND 0x37 0x004 +#define MX1_PAD_USBD_SUSPND__GPIO2_23 0x37 0x032 +#define MX1_PAD_USBD_VP__USBD_VP 0x38 0x000 +#define MX1_PAD_USBD_VP__GPIO2_24 0x38 0x032 +#define MX1_PAD_USBD_VM__USBD_VM 0x39 0x000 +#define MX1_PAD_USBD_VM__GPIO2_25 0x39 0x032 +#define MX1_PAD_USBD_VPO__USBD_VPO 0x3a 0x004 +#define MX1_PAD_USBD_VPO__GPIO2_26 0x3a 0x032 +#define MX1_PAD_USBD_VMO__USBD_VMO 0x3b 0x004 +#define MX1_PAD_USBD_VMO__GPIO2_27 0x3b 0x032 +#define MX1_PAD_UART2_CTS__UART2_CTS 0x3c 0x004 +#define MX1_PAD_UART2_CTS__GPIO2_28 0x3c 0x032 +#define MX1_PAD_UART2_RTS__UART2_RTS 0x3d 0x000 +#define MX1_PAD_UART2_RTS__GPIO2_29 0x3d 0x032 +#define MX1_PAD_UART2_TXD__UART2_TXD 0x3e 0x004 +#define MX1_PAD_UART2_TXD__GPIO2_30 0x3e 0x032 +#define MX1_PAD_UART2_RXD__UART2_RXD 0x3f 0x000 +#define MX1_PAD_UART2_RXD__GPIO2_31 0x3f 0x032 +#define MX1_PAD_SSI_RXFS__SSI_RXFS 0x43 0x000 +#define MX1_PAD_SSI_RXFS__GPIO3_3 0x43 0x032 +#define MX1_PAD_SSI_RXCLK__SSI_RXCLK 0x44 0x000 +#define MX1_PAD_SSI_RXCLK__GPIO3_4 0x44 0x032 +#define MX1_PAD_SSI_RXDAT__SSI_RXDAT 0x45 0x000 +#define MX1_PAD_SSI_RXDAT__GPIO3_5 0x45 0x032 +#define MX1_PAD_SSI_TXDAT__SSI_TXDAT 0x46 0x004 +#define MX1_PAD_SSI_TXDAT__GPIO3_6 0x46 0x032 +#define MX1_PAD_SSI_TXFS__SSI_TXFS 0x47 0x000 +#define MX1_PAD_SSI_TXFS__GPIO3_7 0x47 0x032 +#define MX1_PAD_SSI_TXCLK__SSI_TXCLK 0x48 0x000 +#define MX1_PAD_SSI_TXCLK__GPIO3_8 0x48 0x032 +#define MX1_PAD_UART1_CTS__UART1_CTS 0x49 0x004 +#define MX1_PAD_UART1_CTS__GPIO3_9 0x49 0x032 +#define MX1_PAD_UART1_RTS__UART1_RTS 0x4a 0x000 +#define MX1_PAD_UART1_RTS__GPIO3_10 0x4a 0x032 +#define MX1_PAD_UART1_TXD__UART1_TXD 0x4b 0x004 +#define MX1_PAD_UART1_TXD__GPIO3_11 0x4b 0x032 +#define MX1_PAD_UART1_RXD__UART1_RXD 0x4c 0x000 +#define MX1_PAD_UART1_RXD__GPIO3_12 0x4c 0x032 +#define MX1_PAD_SPI1_RDY__SPI1_RDY 0x4d 0x000 +#define MX1_PAD_SPI1_RDY__GPIO3_13 0x4d 0x032 +#define MX1_PAD_SPI1_SCLK__SPI1_SCLK 0x4e 0x004 +#define MX1_PAD_SPI1_SCLK__GPIO3_14 0x4e 0x032 +#define MX1_PAD_SPI1_SS__SPI1_SS 0x4f 0x000 +#define MX1_PAD_SPI1_SS__GPIO3_15 0x4f 0x032 +#define MX1_PAD_SPI1_MISO__SPI1_MISO 0x50 0x000 +#define MX1_PAD_SPI1_MISO__GPIO3_16 0x50 0x032 +#define MX1_PAD_SPI1_MOSI__SPI1_MOSI 0x51 0x004 +#define MX1_PAD_SPI1_MOSI__GPIO3_17 0x51 0x032 +#define MX1_PAD_BT13__BT13 0x53 0x004 +#define MX1_PAD_BT13__SSI2_RXCLK 0x53 0x001 +#define MX1_PAD_BT13__GPIO3_19 0x53 0x032 +#define MX1_PAD_BT12__BT12 0x54 0x004 +#define MX1_PAD_BT12__SSI2_TXFS 0x54 0x001 +#define MX1_PAD_BT12__GPIO3_20 0x54 0x032 +#define MX1_PAD_BT11__BT11 0x55 0x004 +#define MX1_PAD_BT11__SSI2_TXCLK 0x55 0x001 +#define MX1_PAD_BT11__GPIO3_21 0x55 0x032 +#define MX1_PAD_BT10__BT10 0x56 0x004 +#define MX1_PAD_BT10__SSI2_TX 0x56 0x001 +#define MX1_PAD_BT10__GPIO3_22 0x56 0x032 +#define MX1_PAD_BT9__BT9 0x57 0x004 +#define MX1_PAD_BT9__SSI2_RX 0x57 0x001 +#define MX1_PAD_BT9__GPIO3_23 0x57 0x032 +#define MX1_PAD_BT8__BT8 0x58 0x004 +#define MX1_PAD_BT8__SSI2_RXFS 0x58 0x001 +#define MX1_PAD_BT8__GPIO3_24 0x58 0x032 +#define MX1_PAD_BT8__UART3_RI 0x58 0x016 +#define MX1_PAD_BT7__BT7 0x59 0x004 +#define MX1_PAD_BT7__GPIO3_25 0x59 0x032 +#define MX1_PAD_BT7__UART3_DSR 0x59 0x016 +#define MX1_PAD_BT6__BT6 0x5a 0x004 +#define MX1_PAD_BT6__GPIO3_26 0x5a 0x032 +#define MX1_PAD_BT6__SPI2_SS3 0x5a 0x016 +#define MX1_PAD_BT6__UART3_DTR 0x5a 0x022 +#define MX1_PAD_BT5__BT5 0x5b 0x000 +#define MX1_PAD_BT5__GPIO3_27 0x5b 0x032 +#define MX1_PAD_BT5__UART3_DCD 0x5b 0x016 +#define MX1_PAD_BT4__BT4 0x5c 0x000 +#define MX1_PAD_BT4__GPIO3_28 0x5c 0x032 +#define MX1_PAD_BT4__UART3_CTS 0x5c 0x016 +#define MX1_PAD_BT3__BT3 0x5d 0x000 +#define MX1_PAD_BT3__GPIO3_29 0x5d 0x032 +#define MX1_PAD_BT3__UART3_RTS 0x5d 0x022 +#define MX1_PAD_BT2__BT2 0x5e 0x004 +#define MX1_PAD_BT2__GPIO3_30 0x5e 0x032 +#define MX1_PAD_BT2__UART3_TX 0x5e 0x016 +#define MX1_PAD_BT1__BT1 0x5f 0x000 +#define MX1_PAD_BT1__GPIO3_31 0x5f 0x032 +#define MX1_PAD_BT1__UART3_RX 0x5f 0x022 +#define MX1_PAD_LSCLK__LSCLK 0x66 0x004 +#define MX1_PAD_LSCLK__GPIO4_6 0x66 0x032 +#define MX1_PAD_REV__REV 0x67 0x004 +#define MX1_PAD_REV__UART2_DTR 0x67 0x001 +#define MX1_PAD_REV__GPIO4_7 0x67 0x032 +#define MX1_PAD_REV__SPI2_CLK 0x67 0x006 +#define MX1_PAD_CLS__CLS 0x68 0x004 +#define MX1_PAD_CLS__UART2_DCD 0x68 0x005 +#define MX1_PAD_CLS__GPIO4_8 0x68 0x032 +#define MX1_PAD_CLS__SPI2_SS 0x68 0x002 +#define MX1_PAD_PS__PS 0x69 0x004 +#define MX1_PAD_PS__UART2_RI 0x69 0x005 +#define MX1_PAD_PS__GPIO4_9 0x69 0x032 +#define MX1_PAD_PS__SPI2_RXD 0x69 0x022 +#define MX1_PAD_SPL_SPR__SPL_SPR 0x6a 0x004 +#define MX1_PAD_SPL_SPR__UART2_DSR 0x6a 0x005 +#define MX1_PAD_SPL_SPR__GPIO4_10 0x6a 0x032 +#define MX1_PAD_SPL_SPR__SPI2_TXD 0x6a 0x006 +#define MX1_PAD_CONTRAST__CONTRAST 0x6b 0x004 +#define MX1_PAD_CONTRAST__GPIO4_11 0x6b 0x032 +#define MX1_PAD_CONTRAST__SPI2_SS2 0x6b 0x012 +#define MX1_PAD_ACD_OE__ACD_OE 0x6c 0x004 +#define MX1_PAD_ACD_OE__GPIO4_12 0x6c 0x032 +#define MX1_PAD_LP_HSYNC__LP_HSYNC 0x6d 0x004 +#define MX1_PAD_LP_HSYNC__GPIO4_13 0x6d 0x032 +#define MX1_PAD_FLM_VSYNC__FLM_VSYNC 0x6e 0x004 +#define MX1_PAD_FLM_VSYNC__GPIO4_14 0x6e 0x032 +#define MX1_PAD_LD0__LD0 0x6f 0x004 +#define MX1_PAD_LD0__GPIO4_15 0x6f 0x032 +#define MX1_PAD_LD1__LD1 0x70 0x004 +#define MX1_PAD_LD1__GPIO4_16 0x70 0x032 +#define MX1_PAD_LD2__LD2 0x71 0x004 +#define MX1_PAD_LD2__GPIO4_17 0x71 0x032 +#define MX1_PAD_LD3__LD3 0x72 0x004 +#define MX1_PAD_LD3__GPIO4_18 0x72 0x032 +#define MX1_PAD_LD4__LD4 0x73 0x004 +#define MX1_PAD_LD4__GPIO4_19 0x73 0x032 +#define MX1_PAD_LD5__LD5 0x74 0x004 +#define MX1_PAD_LD5__GPIO4_20 0x74 0x032 +#define MX1_PAD_LD6__LD6 0x75 0x004 +#define MX1_PAD_LD6__GPIO4_21 0x75 0x032 +#define MX1_PAD_LD7__LD7 0x76 0x004 +#define MX1_PAD_LD7__GPIO4_22 0x76 0x032 +#define MX1_PAD_LD8__LD8 0x77 0x004 +#define MX1_PAD_LD8__GPIO4_23 0x77 0x032 +#define MX1_PAD_LD9__LD9 0x78 0x004 +#define MX1_PAD_LD9__GPIO4_24 0x78 0x032 +#define MX1_PAD_LD10__LD10 0x79 0x004 +#define MX1_PAD_LD10__GPIO4_25 0x79 0x032 +#define MX1_PAD_LD11__LD11 0x7a 0x004 +#define MX1_PAD_LD11__GPIO4_26 0x7a 0x032 +#define MX1_PAD_LD12__LD12 0x7b 0x004 +#define MX1_PAD_LD12__GPIO4_27 0x7b 0x032 +#define MX1_PAD_LD13__LD13 0x7c 0x004 +#define MX1_PAD_LD13__GPIO4_28 0x7c 0x032 +#define MX1_PAD_LD14__LD14 0x7d 0x004 +#define MX1_PAD_LD14__GPIO4_29 0x7d 0x032 +#define MX1_PAD_LD15__LD15 0x7e 0x004 +#define MX1_PAD_LD15__GPIO4_30 0x7e 0x032 +#define MX1_PAD_TMR2OUT__TMR2OUT 0x7f 0x000 +#define MX1_PAD_TMR2OUT__GPIO4_31 0x7f 0x032 +#define MX1_PAD_TMR2OUT__SPI2_TXD 0x7f 0x006 + +#endif diff --git a/arch/arm/boot/dts/imx1.dtsi b/arch/arm/boot/dts/imx1.dtsi new file mode 100644 index 000000000000..22f5d1db5b31 --- /dev/null +++ b/arch/arm/boot/dts/imx1.dtsi @@ -0,0 +1,266 @@ +/* + * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include "skeleton.dtsi" +#include "imx1-pinfunc.h" + +#include <dt-bindings/clock/imx1-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + i2c0 = &i2c; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + spi0 = &cspi1; + spi1 = &cspi2; + }; + + aitc: aitc-interrupt-controller@00223000 { + compatible = "fsl,imx1-aitc", "fsl,avic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x00223000 0x1000>; + }; + + cpus { + #size-cells = <0>; + #address-cells = <1>; + + cpu: cpu@0 { + device_type = "cpu"; + compatible = "arm,arm920t"; + operating-points = <200000 1900000>; + clock-latency = <62500>; + clocks = <&clks IMX1_CLK_MCU>; + voltage-tolerance = <5>; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&aitc>; + ranges; + + aipi@00200000 { + compatible = "fsl,aipi-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x00200000 0x10000>; + ranges; + + gpt1: timer@00202000 { + compatible = "fsl,imx1-gpt"; + reg = <0x00202000 0x1000>; + interrupts = <59>; + clocks = <&clks IMX1_CLK_HCLK>, + <&clks IMX1_CLK_PER1>; + clock-names = "ipg", "per"; + }; + + gpt2: timer@00203000 { + compatible = "fsl,imx1-gpt"; + reg = <0x00203000 0x1000>; + interrupts = <58>; + clocks = <&clks IMX1_CLK_HCLK>, + <&clks IMX1_CLK_PER1>; + clock-names = "ipg", "per"; + }; + + fb: fb@00205000 { + compatible = "fsl,imx1-fb"; + reg = <0x00205000 0x1000>; + interrupts = <14>; + clocks = <&clks IMX1_CLK_DUMMY>, + <&clks IMX1_CLK_DUMMY>, + <&clks IMX1_CLK_PER2>; + clock-names = "ipg", "ahb", "per"; + status = "disabled"; + }; + + uart1: serial@00206000 { + compatible = "fsl,imx1-uart"; + reg = <0x00206000 0x1000>; + interrupts = <30 29 26>; + clocks = <&clks IMX1_CLK_HCLK>, + <&clks IMX1_CLK_PER1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart2: serial@00207000 { + compatible = "fsl,imx1-uart"; + reg = <0x00207000 0x1000>; + interrupts = <24 23 20>; + clocks = <&clks IMX1_CLK_HCLK>, + <&clks IMX1_CLK_PER1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + pwm: pwm@00208000 { + #pwm-cells = <2>; + compatible = "fsl,imx1-pwm"; + reg = <0x00208000 0x1000>; + interrupts = <34>; + clocks = <&clks IMX1_CLK_DUMMY>, + <&clks IMX1_CLK_PER1>; + clock-names = "ipg", "per"; + }; + + dma: dma@00209000 { + compatible = "fsl,imx1-dma"; + reg = <0x00209000 0x1000>; + interrupts = <61 60>; + clocks = <&clks IMX1_CLK_HCLK>, + <&clks IMX1_CLK_DMA_GATE>; + clock-names = "ipg", "ahb"; + #dma-cells = <1>; + }; + + uart3: serial@0020a000 { + compatible = "fsl,imx1-uart"; + reg = <0x0020a000 0x1000>; + interrupts = <54 4 1>; + clocks = <&clks IMX1_CLK_UART3_GATE>, + <&clks IMX1_CLK_PER1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + }; + + aipi@00210000 { + compatible = "fsl,aipi-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x00210000 0x10000>; + ranges; + + cspi1: cspi@00213000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx1-cspi"; + reg = <0x00213000 0x1000>; + interrupts = <41>; + clocks = <&clks IMX1_CLK_DUMMY>, + <&clks IMX1_CLK_PER1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + i2c: i2c@00217000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx1-i2c"; + reg = <0x00217000 0x1000>; + interrupts = <39>; + clocks = <&clks IMX1_CLK_HCLK>; + status = "disabled"; + }; + + cspi2: cspi@00219000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx1-cspi"; + reg = <0x00219000 0x1000>; + interrupts = <40>; + clocks = <&clks IMX1_CLK_DUMMY>, + <&clks IMX1_CLK_PER1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + clks: ccm@0021b000 { + compatible = "fsl,imx1-ccm"; + reg = <0x0021b000 0x1000>; + #clock-cells = <1>; + }; + + iomuxc: iomuxc@0021c000 { + compatible = "fsl,imx1-iomuxc"; + reg = <0x0021c000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio1: gpio@0021c000 { + compatible = "fsl,imx1-gpio"; + reg = <0x0021c000 0x100>; + interrupts = <11>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@0021c100 { + compatible = "fsl,imx1-gpio"; + reg = <0x0021c100 0x100>; + interrupts = <12>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@0021c200 { + compatible = "fsl,imx1-gpio"; + reg = <0x0021c200 0x100>; + interrupts = <13>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@0021c300 { + compatible = "fsl,imx1-gpio"; + reg = <0x0021c300 0x100>; + interrupts = <62>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + }; + + weim: weim@00220000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,imx1-weim"; + reg = <0x00220000 0x1000>; + clocks = <&clks IMX1_CLK_DUMMY>; + ranges = < + 0 0 0x10000000 0x02000000 + 1 0 0x12000000 0x01000000 + 2 0 0x13000000 0x01000000 + 3 0 0x14000000 0x01000000 + 4 0 0x15000000 0x01000000 + 5 0 0x16000000 0x01000000 + >; + status = "disabled"; + }; + + esram: esram@00300000 { + compatible = "mmio-sram"; + reg = <0x00300000 0x20000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts index a33f66c11b73..57e29977ba06 100644 --- a/arch/arm/boot/dts/imx23-evk.dts +++ b/arch/arm/boot/dts/imx23-evk.dts @@ -60,10 +60,10 @@ pinctrl-names = "default"; pinctrl-0 = <&lcdif_24bit_pins_a>; lcd-supply = <®_lcd_3v3>; - display = <&display>; + display = <&display0>; status = "okay"; - display: display { + display0: display0 { bits-per-pixel = <32>; bus-width = <24>; diff --git a/arch/arm/boot/dts/imx25-pinfunc.h b/arch/arm/boot/dts/imx25-pinfunc.h index 9238a95d8e62..88eebb15da6a 100644 --- a/arch/arm/boot/dts/imx25-pinfunc.h +++ b/arch/arm/boot/dts/imx25-pinfunc.h @@ -247,6 +247,7 @@ #define MX25_PAD_OE_ACD__GPIO_1_25 0x114 0x30c 0x000 0x15 0x000 #define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x10 0x000 +#define MX25_PAD_CONTRAST__CC4 0x118 0x310 0x000 0x11 0x000 #define MX25_PAD_CONTRAST__PWM4_PWMO 0x118 0x310 0x000 0x14 0x000 #define MX25_PAD_CONTRAST__FEC_CRS 0x118 0x310 0x508 0x15 0x001 @@ -260,6 +261,7 @@ #define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x000 0x17 0x000 #define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x10 0x000 +#define MX25_PAD_CSI_D3__UART5_TXD_MUX 0x124 0x31c 0x000 0x11 0x000 #define MX25_PAD_CSI_D3__GPIO_1_28 0x124 0x31c 0x000 0x15 0x000 #define MX25_PAD_CSI_D3__CSPI3_MISO 0x124 0x31c 0x4b4 0x17 0x001 @@ -269,31 +271,46 @@ #define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x000 0x17 0x000 #define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x10 0x000 +#define MX25_PAD_CSI_D5__UART5_CTS 0x12c 0x324 0x000 0x11 0x001 #define MX25_PAD_CSI_D5__GPIO_1_30 0x12c 0x324 0x000 0x15 0x000 #define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x17 0x000 #define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x10 0x000 +#define MX25_PAD_CSI_D6__SDHC2_CMD 0x130 0x328 0x4e0 0x12 0x001 #define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x15 0x000 #define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x10 0x000 +#define MX25_PAD_CSI_D7__SDHC2_DAT_CLK 0x134 0x32C 0x4dc 0x12 0x001 #define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x15 0x000 #define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x10 0x000 +#define MX25_PAD_CSI_D8__AUD6_RXC 0x138 0x330 0x000 0x12 0x001 #define MX25_PAD_CSI_D8__GPIO_1_7 0x138 0x330 0x000 0x15 0x000 +#define MX25_PAD_CSI_D8__CSPI3_SS2 0x138 0x330 0x4c4 0x17 0x000 #define MX25_PAD_CSI_D9__CSI_D9 0x13c 0x334 0x000 0x10 0x000 +#define MX25_PAD_CSI_D9__AUD6_RXFS 0x13c 0x334 0x000 0x12 0x001 #define MX25_PAD_CSI_D9__GPIO_4_21 0x13c 0x334 0x000 0x15 0x000 +#define MX25_PAD_CSI_D9__CSPI3_SS3 0x13c 0x334 0x4c8 0x17 0x000 #define MX25_PAD_CSI_MCLK__CSI_MCLK 0x140 0x338 0x000 0x10 0x000 +#define MX25_PAD_CSI_MCLK__AUD6_TXD 0x140 0x338 0x000 0x11 0x001 +#define MX25_PAD_CSI_MCLK__SDHC2_DAT0 0x140 0x338 0x4e4 0x12 0x001 #define MX25_PAD_CSI_MCLK__GPIO_1_8 0x140 0x338 0x000 0x15 0x000 #define MX25_PAD_CSI_VSYNC__CSI_VSYNC 0x144 0x33c 0x000 0x10 0x000 +#define MX25_PAD_CSI_VSYNC__AUD6_RXD 0x144 0x33c 0x000 0x11 0x001 +#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1 0x144 0x33c 0x4e8 0x12 0x001 #define MX25_PAD_CSI_VSYNC__GPIO_1_9 0x144 0x33c 0x000 0x15 0x000 #define MX25_PAD_CSI_HSYNC__CSI_HSYNC 0x148 0x340 0x000 0x10 0x000 +#define MX25_PAD_CSI_HSYNC__AUD6_TXC 0x148 0x340 0x000 0x11 0x001 +#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2 0x148 0x340 0x4ec 0x12 0x001 #define MX25_PAD_CSI_HSYNC__GPIO_1_10 0x148 0x340 0x000 0x15 0x000 #define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK 0x14c 0x344 0x000 0x10 0x000 +#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS 0x14c 0x344 0x000 0x11 0x001 +#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3 0x14c 0x344 0x4f0 0x12 0x001 #define MX25_PAD_CSI_PIXCLK__GPIO_1_11 0x14c 0x344 0x000 0x15 0x000 #define MX25_PAD_I2C1_CLK__I2C1_CLK 0x150 0x348 0x000 0x10 0x000 @@ -303,18 +320,24 @@ #define MX25_PAD_I2C1_DAT__GPIO_1_13 0x154 0x34c 0x000 0x15 0x000 #define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI 0x158 0x350 0x000 0x10 0x000 +#define MX25_PAD_CSPI1_MOSI__UART3_RXD 0x158 0x350 0x000 0x12 0x000 #define MX25_PAD_CSPI1_MOSI__GPIO_1_14 0x158 0x350 0x000 0x15 0x000 #define MX25_PAD_CSPI1_MISO__CSPI1_MISO 0x15c 0x354 0x000 0x10 0x000 +#define MX25_PAD_CSPI1_MISO__UART3_TXD 0x15c 0x354 0x000 0x12 0x000 #define MX25_PAD_CSPI1_MISO__GPIO_1_15 0x15c 0x354 0x000 0x15 0x000 #define MX25_PAD_CSPI1_SS0__CSPI1_SS0 0x160 0x358 0x000 0x10 0x000 +#define MX25_PAD_CSPI1_SS0__PWM2_PWMO 0x160 0x358 0x000 0x12 0x000 #define MX25_PAD_CSPI1_SS0__GPIO_1_16 0x160 0x358 0x000 0x15 0x000 #define MX25_PAD_CSPI1_SS1__CSPI1_SS1 0x164 0x35c 0x000 0x10 0x000 +#define MX25_PAD_CSPI1_SS1__I2C3_DAT 0x164 0x35C 0x528 0x11 0x001 +#define MX25_PAD_CSPI1_SS1__UART3_RTS 0x164 0x35c 0x000 0x12 0x000 #define MX25_PAD_CSPI1_SS1__GPIO_1_17 0x164 0x35c 0x000 0x15 0x000 #define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK 0x168 0x360 0x000 0x10 0x000 +#define MX25_PAD_CSPI1_SCLK__UART3_CTS 0x168 0x360 0x000 0x12 0x000 #define MX25_PAD_CSPI1_SCLK__GPIO_1_18 0x168 0x360 0x000 0x15 0x000 #define MX25_PAD_CSPI1_RDY__CSPI1_RDY 0x16c 0x364 0x000 0x10 0x000 @@ -328,6 +351,7 @@ #define MX25_PAD_UART1_RTS__UART1_RTS 0x178 0x370 0x000 0x10 0x000 #define MX25_PAD_UART1_RTS__CSI_D0 0x178 0x370 0x488 0x11 0x001 +#define MX25_PAD_UART1_RTS__CC3 0x178 0x370 0x000 0x12 0x000 #define MX25_PAD_UART1_RTS__GPIO_4_24 0x178 0x370 0x000 0x15 0x000 #define MX25_PAD_UART1_CTS__UART1_CTS 0x17c 0x374 0x000 0x10 0x000 @@ -342,6 +366,7 @@ #define MX25_PAD_UART2_RTS__UART2_RTS 0x188 0x380 0x000 0x10 0x000 #define MX25_PAD_UART2_RTS__FEC_COL 0x188 0x380 0x504 0x12 0x002 +#define MX25_PAD_UART2_RTS__CC1 0x188 0x380 0x000 0x13 0x000 #define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x15 0x000 #define MX25_PAD_UART2_CTS__FEC_RX_ER 0x18c 0x384 0x518 0x12 0x002 @@ -349,14 +374,17 @@ #define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x15 0x000 #define MX25_PAD_SD1_CMD__SD1_CMD 0x190 0x388 0x000 0x10 0x000 +#define MX25_PAD_SD1_CMD__CSPI2_MOSI 0x190 0x388 0x4a0 0x11 0x001 #define MX25_PAD_SD1_CMD__FEC_RDATA2 0x190 0x388 0x50c 0x12 0x002 #define MX25_PAD_SD1_CMD__GPIO_2_23 0x190 0x388 0x000 0x15 0x000 #define MX25_PAD_SD1_CLK__SD1_CLK 0x194 0x38c 0x000 0x10 0x000 +#define MX25_PAD_SD1_CLK__CSPI2_MISO 0x194 0x38c 0x49c 0x11 0x001 #define MX25_PAD_SD1_CLK__FEC_RDATA3 0x194 0x38c 0x510 0x12 0x002 #define MX25_PAD_SD1_CLK__GPIO_2_24 0x194 0x38c 0x000 0x15 0x000 #define MX25_PAD_SD1_DATA0__SD1_DATA0 0x198 0x390 0x000 0x10 0x000 +#define MX25_PAD_SD1_DATA0__CSPI2_SCLK 0x198 0x390 0x494 0x11 0x001 #define MX25_PAD_SD1_DATA0__GPIO_2_25 0x198 0x390 0x000 0x15 0x000 #define MX25_PAD_SD1_DATA1__SD1_DATA1 0x19c 0x394 0x000 0x10 0x000 @@ -457,14 +485,15 @@ #define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x16 0x000 #define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x10 0x000 -#define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x02 0x000 #define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x16 0x001 #define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x10 0x000 -#define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x02 0x000 +#define MX25_PAD_GPIO_E__I2C3_CLK 0x204 0x400 0x524 0x11 0x002 +#define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x12 0x000 #define MX25_PAD_GPIO_E__AUD7_TXD 0x204 0x400 0x000 0x14 0x000 #define MX25_PAD_GPIO_F__GPIO_F 0x208 0x404 0x000 0x10 0x000 +#define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x12 0x000 #define MX25_PAD_GPIO_F__AUD7_TXC 0x208 0x404 0x000 0x14 0x000 #define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK 0x20c 0x000 0x000 0x10 0x000 diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi index c1740396b2c9..58d3c3cf2923 100644 --- a/arch/arm/boot/dts/imx25.dtsi +++ b/arch/arm/boot/dts/imx25.dtsi @@ -239,6 +239,7 @@ }; ssi2: ssi@50014000 { + #sound-dai-cells = <0>; compatible = "fsl,imx25-ssi", "fsl,imx21-ssi"; reg = <0x50014000 0x4000>; interrupts = <11>; @@ -274,6 +275,7 @@ }; ssi1: ssi@50034000 { + #sound-dai-cells = <0>; compatible = "fsl,imx25-ssi", "fsl,imx21-ssi"; reg = <0x50034000 0x4000>; interrupts = <12>; @@ -453,7 +455,7 @@ }; sdma: sdma@53fd4000 { - compatible = "fsl,imx25-sdma", "fsl,imx35-sdma"; + compatible = "fsl,imx25-sdma"; reg = <0x53fd4000 0x4000>; clocks = <&clks 112>, <&clks 68>; clock-names = "ipg", "ahb"; diff --git a/arch/arm/boot/dts/imx27-apf27dev.dts b/arch/arm/boot/dts/imx27-apf27dev.dts index 2b6d489dae69..da306c5dd678 100644 --- a/arch/arm/boot/dts/imx27-apf27dev.dts +++ b/arch/arm/boot/dts/imx27-apf27dev.dts @@ -67,6 +67,16 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_cspi1 &pinctrl_cspi1_cs>; status = "okay"; + + adc@0 { + compatible = "maxim,max1027"; + reg = <0>; + interrupt-parent = <&gpio5>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_max1027>; + spi-max-frequency = <10000000>; + }; }; &cspi2 { @@ -189,6 +199,13 @@ >; }; + pinctrl_max1027: max1027 { + fsl,pins = < + MX27_PAD_UART1_CTS__GPIO5_14 0x0 /* CNVST */ + MX27_PAD_UART1_RTS__GPIO5_15 0x0 /* EOC */ + >; + }; + pinctrl_pwm: pwmgrp { fsl,pins = < MX27_PAD_PWMO__PWMO 0x0 diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts index 221cac4fb2cd..1f38a052ad4b 100644 --- a/arch/arm/boot/dts/imx28-apf28dev.dts +++ b/arch/arm/boot/dts/imx28-apf28dev.dts @@ -83,10 +83,10 @@ pinctrl-names = "default"; pinctrl-0 = <&lcdif_16bit_pins_a &lcdif_pins_apf28dev>; - display = <&display>; + display = <&display0>; status = "okay"; - display: display { + display0: display0 { bits-per-pixel = <16>; bus-width = <16>; diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts index e1ce9179db63..1092b761d7ac 100644 --- a/arch/arm/boot/dts/imx28-apx4devkit.dts +++ b/arch/arm/boot/dts/imx28-apx4devkit.dts @@ -94,10 +94,10 @@ pinctrl-names = "default"; pinctrl-0 = <&lcdif_24bit_pins_a &lcdif_pins_apx4>; - display = <&display>; + display = <&display0>; status = "okay"; - display: display { + display0: display0 { bits-per-pixel = <32>; bus-width = <24>; diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts index 7d51459de5e8..ef944b6d4f01 100644 --- a/arch/arm/boot/dts/imx28-cfa10049.dts +++ b/arch/arm/boot/dts/imx28-cfa10049.dts @@ -177,10 +177,10 @@ pinctrl-0 = <&lcdif_18bit_pins_cfa10049 &lcdif_pins_cfa10049 &lcdif_pins_cfa10049_pullup>; - display = <&display>; + display = <&display0>; status = "okay"; - display: display { + display0: display0 { bits-per-pixel = <32>; bus-width = <18>; diff --git a/arch/arm/boot/dts/imx28-cfa10055.dts b/arch/arm/boot/dts/imx28-cfa10055.dts index c3900e7ba331..6a34114bec29 100644 --- a/arch/arm/boot/dts/imx28-cfa10055.dts +++ b/arch/arm/boot/dts/imx28-cfa10055.dts @@ -92,10 +92,10 @@ pinctrl-0 = <&lcdif_18bit_pins_cfa10055 &lcdif_pins_cfa10055 &lcdif_pins_cfa10055_pullup>; - display = <&display>; + display = <&display0>; status = "okay"; - display: display { + display0: display0 { bits-per-pixel = <32>; bus-width = <18>; diff --git a/arch/arm/boot/dts/imx28-cfa10056.dts b/arch/arm/boot/dts/imx28-cfa10056.dts index cef959a97219..ba6495ca44d2 100644 --- a/arch/arm/boot/dts/imx28-cfa10056.dts +++ b/arch/arm/boot/dts/imx28-cfa10056.dts @@ -64,10 +64,10 @@ pinctrl-0 = <&lcdif_24bit_pins_a &lcdif_pins_cfa10056 &lcdif_pins_cfa10056_pullup >; - display = <&display>; + display = <&display0>; status = "okay"; - display: display { + display0: display0 { bits-per-pixel = <32>; bus-width = <24>; diff --git a/arch/arm/boot/dts/imx28-cfa10057.dts b/arch/arm/boot/dts/imx28-cfa10057.dts index c4e00ce4b6da..5df0b24eaf59 100644 --- a/arch/arm/boot/dts/imx28-cfa10057.dts +++ b/arch/arm/boot/dts/imx28-cfa10057.dts @@ -78,10 +78,10 @@ pinctrl-names = "default"; pinctrl-0 = <&lcdif_18bit_pins_cfa10057 &lcdif_pins_cfa10057>; - display = <&display>; + display = <&display0>; status = "okay"; - display: display { + display0: display0 { bits-per-pixel = <32>; bus-width = <18>; diff --git a/arch/arm/boot/dts/imx28-cfa10058.dts b/arch/arm/boot/dts/imx28-cfa10058.dts index 7c9cc783f0d1..f5c6dce34abe 100644 --- a/arch/arm/boot/dts/imx28-cfa10058.dts +++ b/arch/arm/boot/dts/imx28-cfa10058.dts @@ -51,10 +51,10 @@ pinctrl-names = "default"; pinctrl-0 = <&lcdif_24bit_pins_a &lcdif_pins_cfa10058>; - display = <&display>; + display = <&display0>; status = "okay"; - display: display { + display0: display0 { bits-per-pixel = <32>; bus-width = <24>; diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts index e4cc44c98585..0e13b4b10a92 100644 --- a/arch/arm/boot/dts/imx28-evk.dts +++ b/arch/arm/boot/dts/imx28-evk.dts @@ -124,10 +124,10 @@ pinctrl-0 = <&lcdif_24bit_pins_a &lcdif_pins_evk>; lcd-supply = <®_lcd_3v3>; - display = <&display>; + display = <&display0>; status = "okay"; - display: display { + display0: display0 { bits-per-pixel = <32>; bus-width = <24>; @@ -193,7 +193,6 @@ i2c0: i2c@80058000 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_a>; - clock-frequency = <400000>; status = "okay"; sgtl5000: codec@0a { diff --git a/arch/arm/boot/dts/imx28-m28cu3.dts b/arch/arm/boot/dts/imx28-m28cu3.dts index 9348ce59dda4..2df63bee6f4e 100644 --- a/arch/arm/boot/dts/imx28-m28cu3.dts +++ b/arch/arm/boot/dts/imx28-m28cu3.dts @@ -115,10 +115,10 @@ pinctrl-names = "default"; pinctrl-0 = <&lcdif_24bit_pins_a &lcdif_pins_m28>; - display = <&display>; + display = <&display0>; status = "okay"; - display: display0 { + display0: display0 { bits-per-pixel = <32>; bus-width = <24>; diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts index b3c09ae3b928..e35cc6ba3ca6 100644 --- a/arch/arm/boot/dts/imx28-m28evk.dts +++ b/arch/arm/boot/dts/imx28-m28evk.dts @@ -81,10 +81,10 @@ pinctrl-names = "default"; pinctrl-0 = <&lcdif_24bit_pins_a &lcdif_pins_m28>; - display = <&display>; + display = <&display0>; status = "okay"; - display: display { + display0: display0 { bits-per-pixel = <16>; bus-width = <18>; diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts index e14bd86f3e99..a5b27c85a91c 100644 --- a/arch/arm/boot/dts/imx28-tx28.dts +++ b/arch/arm/boot/dts/imx28-tx28.dts @@ -21,12 +21,15 @@ aliases { can0 = &can0; can1 = &can1; - display = &display; + display = &display0; ds1339 = &ds1339; gpio5 = &gpio5; lcdif = &lcdif; lcdif_23bit_pins = &tx28_lcdif_23bit_pins; lcdif_24bit_pins = &lcdif_24bit_pins_a; + reg_can_xcvr = ®_can_xcvr; + spi_gpio = &spi_gpio; + spi_mxs = &ssp3; stk5led = &user_led; usbotg = &usb0; }; @@ -37,7 +40,7 @@ onewire { compatible = "w1-gpio"; - gpios = <&gpio2 7 0>; + gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; status = "disabled"; }; @@ -52,7 +55,7 @@ regulator-name = "usb0_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpio0 18 0>; + gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>; enable-active-high; }; @@ -62,7 +65,7 @@ regulator-name = "usb1_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpio3 27 0>; + gpio = <&gpio3 27 GPIO_ACTIVE_HIGH>; enable-active-high; }; @@ -90,7 +93,7 @@ regulator-name = "CAN XCVR"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&gpio1 0 0>; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&tx28_flexcan_xcvr_pins>; }; @@ -101,7 +104,7 @@ regulator-name = "LCD POWER"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&gpio1 31 0>; + gpio = <&gpio1 31 GPIO_ACTIVE_HIGH>; enable-active-high; }; @@ -111,7 +114,7 @@ regulator-name = "LCD RESET"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - gpio = <&gpio3 30 0>; + gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>; startup-delay-us = <300000>; enable-active-high; regulator-always-on; @@ -143,7 +146,7 @@ user_led: user { label = "Heartbeat"; - gpios = <&gpio4 10 0>; + gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; @@ -172,16 +175,16 @@ matrix_keypad: matrix-keypad@0 { compatible = "gpio-matrix-keypad"; col-gpios = < - &gpio5 0 0 - &gpio5 1 0 - &gpio5 2 0 - &gpio5 3 0 + &gpio5 0 GPIO_ACTIVE_HIGH + &gpio5 1 GPIO_ACTIVE_HIGH + &gpio5 2 GPIO_ACTIVE_HIGH + &gpio5 3 GPIO_ACTIVE_HIGH >; row-gpios = < - &gpio5 4 0 - &gpio5 5 0 - &gpio5 6 0 - &gpio5 7 0 + &gpio5 4 GPIO_ACTIVE_HIGH + &gpio5 5 GPIO_ACTIVE_HIGH + &gpio5 6 GPIO_ACTIVE_HIGH + &gpio5 7 GPIO_ACTIVE_HIGH >; /* sample keymap */ linux,keymap = < @@ -203,6 +206,44 @@ col-scan-delay-us = <5000>; linux,no-autorepeat; }; + + spi_gpio: spi-gpio { + compatible = "spi-gpio"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&tx28_spi_gpio_pins>; + + gpio-sck = <&gpio2 24 GPIO_ACTIVE_HIGH>; + gpio-mosi = <&gpio2 25 GPIO_ACTIVE_HIGH>; + gpio-miso = <&gpio2 26 GPIO_ACTIVE_HIGH>; + num-chipselects = <3>; + cs-gpios = < + &gpio2 27 GPIO_ACTIVE_LOW + &gpio3 8 GPIO_ACTIVE_LOW + &gpio3 9 GPIO_ACTIVE_LOW + >; + /* enable this and disable ssp3 below, if you need full duplex SPI transfer */ + status = "disabled"; + + spi@0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <57600000>; + }; + + spi@1 { + compatible = "spidev"; + reg = <1>; + spi-max-frequency = <57600000>; + }; + + spi@2 { + compatible = "spidev"; + reg = <2>; + spi-max-frequency = <57600000>; + }; + }; }; /* 2nd TX-Std UART - (A)UART1 */ @@ -284,8 +325,8 @@ pinctrl-0 = <&tx28_edt_ft5x06_pins>; interrupt-parent = <&gpio2>; interrupts = <5 0>; - reset-gpios = <&gpio2 6 1>; - wake-gpios = <&gpio4 9 0>; + reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; + wake-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>; }; touchscreen: tsc2007@48 { @@ -295,7 +336,7 @@ pinctrl-0 = <&tx28_tsc2007_pins>; interrupt-parent = <&gpio3>; interrupts = <20 0>; - pendown-gpio = <&gpio3 20 1>; + pendown-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; ti,x-plate-ohms = /bits/ 16 <660>; }; @@ -309,10 +350,10 @@ pinctrl-names = "default"; pinctrl-0 = <&lcdif_24bit_pins_a &lcdif_sync_pins_a &tx28_lcdif_ctrl_pins>; lcd-supply = <®_lcd>; - display = <&display>; + display = <&display0>; status = "okay"; - display: display@0 { + display0: display0 { bits-per-pixel = <32>; bus-width = <24>; display-timings { @@ -558,6 +599,20 @@ fsl,pull-up = <MXS_PULL_DISABLE>; }; + tx28_spi_gpio_pins: spi-gpiogrp { + fsl,pinmux-ids = < + MX28_PAD_AUART2_RX__GPIO_3_8 + MX28_PAD_AUART2_TX__GPIO_3_9 + MX28_PAD_SSP3_SCK__GPIO_2_24 + MX28_PAD_SSP3_MOSI__GPIO_2_25 + MX28_PAD_SSP3_MISO__GPIO_2_26 + MX28_PAD_SSP3_SS0__GPIO_2_27 + >; + fsl,drive-strength = <MXS_DRIVE_8mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + tx28_tsc2007_pins: tx28-tsc2007-pins { fsl,pinmux-ids = < MX28_PAD_SAIF0_MCLK__GPIO_3_20 /* TSC2007 IRQ */ @@ -619,17 +674,23 @@ clock-frequency = <57600000>; status = "okay"; - spidev0: spi@0 { + spi@0 { compatible = "spidev"; reg = <0>; spi-max-frequency = <57600000>; }; - spidev1: spi@1 { + spi@1 { compatible = "spidev"; reg = <1>; spi-max-frequency = <57600000>; }; + + spi@2 { + compatible = "spidev"; + reg = <2>; + spi-max-frequency = <57600000>; + }; }; &usb0 { diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index a95cc5358ff4..47f68ac868d4 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -489,6 +489,38 @@ fsl,pull-up = <MXS_PULL_DISABLE>; }; + mmc1_4bit_pins_a: mmc1-4bit@0 { + reg = <0>; + fsl,pinmux-ids = < + MX28_PAD_GPMI_D00__SSP1_D0 + MX28_PAD_GPMI_D01__SSP1_D1 + MX28_PAD_GPMI_D02__SSP1_D2 + MX28_PAD_GPMI_D03__SSP1_D3 + MX28_PAD_GPMI_RDY1__SSP1_CMD + MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT + MX28_PAD_GPMI_WRN__SSP1_SCK + >; + fsl,drive-strength = <MXS_DRIVE_8mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_ENABLE>; + }; + + mmc1_cd_cfg: mmc1-cd-cfg { + fsl,pinmux-ids = < + MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT + >; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + mmc1_sck_cfg: mmc1-sck-cfg { + fsl,pinmux-ids = < + MX28_PAD_GPMI_WRN__SSP1_SCK + >; + fsl,drive-strength = <MXS_DRIVE_12mA>; + fsl,pull-up = <MXS_PULL_DISABLE>; + }; + + mmc2_4bit_pins_a: mmc2-4bit@0 { reg = <0>; fsl,pinmux-ids = < @@ -553,6 +585,17 @@ fsl,pull-up = <MXS_PULL_ENABLE>; }; + i2c1_pins_b: i2c1@1 { + reg = <1>; + fsl,pinmux-ids = < + MX28_PAD_AUART2_CTS__I2C1_SCL + MX28_PAD_AUART2_RTS__I2C1_SDA + >; + fsl,drive-strength = <MXS_DRIVE_8mA>; + fsl,voltage = <MXS_VOLTAGE_HIGH>; + fsl,pull-up = <MXS_PULL_ENABLE>; + }; + saif0_pins_a: saif0@0 { reg = <0>; fsl,pinmux-ids = < diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi index 442e216ca9d9..6932928f3b45 100644 --- a/arch/arm/boot/dts/imx35.dtsi +++ b/arch/arm/boot/dts/imx35.dtsi @@ -114,6 +114,7 @@ }; ssi1: ssi@43fa0000 { + #sound-dai-cells = <0>; compatible = "fsl,imx35-ssi", "fsl,imx21-ssi"; reg = <0x43fa0000 0x4000>; interrupts = <11>; diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index c0e0f60ab6b2..620b0f030591 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -145,6 +145,7 @@ }; ssi2: ssi@50014000 { + #sound-dai-cells = <0>; compatible = "fsl,imx50-ssi", "fsl,imx51-ssi", "fsl,imx21-ssi"; @@ -454,6 +455,7 @@ }; ssi1: ssi@63fcc000 { + #sound-dai-cells = <0>; compatible = "fsl,imx50-ssi", "fsl,imx51-ssi", "fsl,imx21-ssi"; reg = <0x63fcc000 0x4000>; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 17c05a6fa776..c0116cffc513 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -210,10 +210,13 @@ }; ssi2: ssi@70014000 { + #sound-dai-cells = <0>; compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; reg = <0x70014000 0x4000>; interrupts = <30>; - clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>; + clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>, + <&clks IMX5_CLK_SSI2_ROOT_GATE>; + clock-names = "ipg", "baud"; dmas = <&sdma 24 1 0>, <&sdma 25 1 0>; dma-names = "rx", "tx"; @@ -499,10 +502,13 @@ }; ssi1: ssi@83fcc000 { + #sound-dai-cells = <0>; compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; reg = <0x83fcc000 0x4000>; interrupts = <29>; - clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>; + clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>, + <&clks IMX5_CLK_SSI1_ROOT_GATE>; + clock-names = "ipg", "baud"; dmas = <&sdma 28 0 0>, <&sdma 29 0 0>; dma-names = "rx", "tx"; @@ -554,10 +560,13 @@ }; ssi3: ssi@83fe8000 { + #sound-dai-cells = <0>; compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; reg = <0x83fe8000 0x4000>; interrupts = <96>; - clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>; + clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>, + <&clks IMX5_CLK_SSI3_ROOT_GATE>; + clock-names = "ipg", "baud"; dmas = <&sdma 46 0 0>, <&sdma 47 0 0>; dma-names = "rx", "tx"; diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts index 5ec1590ff7bc..1d325576bcc0 100644 --- a/arch/arm/boot/dts/imx53-smd.dts +++ b/arch/arm/boot/dts/imx53-smd.dts @@ -265,7 +265,7 @@ }; pmic: dialog@48 { - compatible = "dialog,da9053", "dialog,da9052"; + compatible = "dlg,da9053", "dlg,da9052"; reg = <0x48>; }; }; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 6b675a02066f..a30bddfdbdb6 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -46,10 +46,21 @@ cpus { #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a8"; reg = <0x0>; + clocks = <&clks IMX5_CLK_ARM>; + clock-latency = <61036>; + voltage-tolerance = <5>; + operating-points = < + /* kHz */ + 166666 850000 + 400000 900000 + 800000 1050000 + 1000000 1200000 + 1200000 1300000 + >; }; }; @@ -221,12 +232,15 @@ }; ssi2: ssi@50014000 { + #sound-dai-cells = <0>; compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", "fsl,imx21-ssi"; reg = <0x50014000 0x4000>; interrupts = <30>; - clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>; + clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>, + <&clks IMX5_CLK_SSI2_ROOT_GATE>; + clock-names = "ipg", "baud"; dmas = <&sdma 24 1 0>, <&sdma 25 1 0>; dma-names = "rx", "tx"; @@ -669,11 +683,14 @@ }; ssi1: ssi@63fcc000 { + #sound-dai-cells = <0>; compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", "fsl,imx21-ssi"; reg = <0x63fcc000 0x4000>; interrupts = <29>; - clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>; + clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>, + <&clks IMX5_CLK_SSI1_ROOT_GATE>; + clock-names = "ipg", "baud"; dmas = <&sdma 28 0 0>, <&sdma 29 0 0>; dma-names = "rx", "tx"; @@ -696,11 +713,14 @@ }; ssi3: ssi@63fe8000 { + #sound-dai-cells = <0>; compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", "fsl,imx21-ssi"; reg = <0x63fe8000 0x4000>; interrupts = <96>; - clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>; + clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>, + <&clks IMX5_CLK_SSI3_ROOT_GATE>; + clock-names = "ipg", "baud"; dmas = <&sdma 46 0 0>, <&sdma 47 0 0>; dma-names = "rx", "tx"; @@ -752,5 +772,10 @@ reg = <0xf8000000 0x20000>; clocks = <&clks IMX5_CLK_OCRAM>; }; + + pmu { + compatible = "arm,cortex-a8-pmu"; + interrupts = <77>; + }; }; }; diff --git a/arch/arm/boot/dts/imx6dl-gw552x.dts b/arch/arm/boot/dts/imx6dl-gw552x.dts new file mode 100644 index 000000000000..a4b700cef188 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-gw552x.dts @@ -0,0 +1,20 @@ +/* + * Copyright 2014 Gateworks Corporation + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-gw552x.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 DualLite/Solo GW552X"; + compatible = "gw,imx6dl-gw552x", "gw,ventana", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/imx6dl-hummingboard.dts b/arch/arm/boot/dts/imx6dl-hummingboard.dts index 71598546087f..44a0e6736bb1 100644 --- a/arch/arm/boot/dts/imx6dl-hummingboard.dts +++ b/arch/arm/boot/dts/imx6dl-hummingboard.dts @@ -1,206 +1,13 @@ /* - * Copyright (C) 2013,2014 Russell King + * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) + * Based on dt work by Russell King */ /dts-v1/; #include "imx6dl.dtsi" -#include "imx6qdl-microsom.dtsi" -#include "imx6qdl-microsom-ar8035.dtsi" +#include "imx6qdl-hummingboard.dtsi" / { - model = "SolidRun HummingBoard DL/Solo"; - compatible = "solidrun,hummingboard", "fsl,imx6dl"; - - chosen { - stdout-path = &uart1; - }; - - ir_recv: ir-receiver { - compatible = "gpio-ir-receiver"; - gpios = <&gpio1 2 1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_gpio1_2>; - }; - - regulators { - compatible = "simple-bus"; - - reg_3p3v: 3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - reg_usbh1_vbus: usb-h1-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 0 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_usbh1_vbus>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usbotg_vbus: usb-otg-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 22 0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_usbotg_vbus>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - }; - - sound-spdif { - compatible = "fsl,imx-audio-spdif"; - model = "On-board SPDIF"; - /* IMX6 doesn't implement this yet */ - spdif-controller = <&spdif>; - spdif-out; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_flexcan1>; - status = "okay"; -}; - -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_hdmi>; - ddc-i2c-bus = <&i2c2>; - status = "okay"; -}; - -&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_i2c1>; - - /* - * Not fitted on Carrier-1 board... yet - status = "okay"; - - rtc: pcf8523@68 { - compatible = "nxp,pcf8523"; - reg = <0x68>; - }; - */ -}; - -&i2c2 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_i2c2>; - status = "okay"; -}; - -&iomuxc { - hummingboard { - pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 { - fsl,pins = < - MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x80000000 - MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x80000000 - >; - }; - - pinctrl_hummingboard_gpio1_2: hummingboard-gpio1_2 { - fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 - >; - }; - - pinctrl_hummingboard_hdmi: hummingboard-hdmi { - fsl,pins = < - MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 - >; - }; - - pinctrl_hummingboard_i2c1: hummingboard-i2c1 { - fsl,pins = < - MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 - >; - }; - - pinctrl_hummingboard_i2c2: hummingboard-i2c2 { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_hummingboard_spdif: hummingboard-spdif { - fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>; - }; - - pinctrl_hummingboard_usbh1_vbus: hummingboard-usbh1-vbus { - fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0>; - }; - - pinctrl_hummingboard_usbotg_id: hummingboard-usbotg-id { - /* - * Similar to pinctrl_usbotg_2, but we want it - * pulled down for a fixed host connection. - */ - fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>; - }; - - pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus { - fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0>; - }; - - pinctrl_hummingboard_usdhc2_aux: hummingboard-usdhc2-aux { - fsl,pins = < - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 - >; - }; - - pinctrl_hummingboard_usdhc2: hummingboard-usdhc2 { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 - MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 - MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 - MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 - MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 - MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 - >; - }; - }; -}; - -&spdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_spdif>; - status = "okay"; -}; - -&usbh1 { - disable-over-current; - vbus-supply = <®_usbh1_vbus>; - status = "okay"; -}; - -&usbotg { - disable-over-current; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hummingboard_usbotg_id>; - vbus-supply = <®_usbotg_vbus>; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default"; - pinctrl-0 = < - &pinctrl_hummingboard_usdhc2_aux - &pinctrl_hummingboard_usdhc2 - >; - vmmc-supply = <®_3p3v>; - cd-gpios = <&gpio1 4 0>; - status = "okay"; + model = "SolidRun HummingBoard Solo/DualLite"; + compatible = "solidrun,hummingboard/dl", "fsl,imx6dl"; }; diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi index b453e0e28aee..1ac2fe732867 100644 --- a/arch/arm/boot/dts/imx6dl.dtsi +++ b/arch/arm/boot/dts/imx6dl.dtsi @@ -13,6 +13,10 @@ #include "imx6qdl.dtsi" / { + aliases { + i2c3 = &i2c4; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -114,3 +118,7 @@ "di0_sel", "di1_sel", "di0", "di1"; }; + +&vpu { + compatible = "fsl,imx6dl-vpu", "cnm,coda960"; +}; diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts index 22e6f8e657d2..822ffb231c57 100644 --- a/arch/arm/boot/dts/imx6q-gw5400-a.dts +++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts @@ -10,6 +10,7 @@ */ /dts-v1/; +#include <dt-bindings/gpio/gpio.h> #include "imx6q.dtsi" / { @@ -18,7 +19,6 @@ /* these are used by bootloader for disabling nodes */ aliases { - ethernet0 = &fec; ethernet1 = ð1; i2c0 = &i2c1; i2c1 = &i2c2; @@ -26,12 +26,10 @@ led0 = &led0; led1 = &led1; led2 = &led2; - sky2 = ð1; ssi0 = &ssi1; spi0 = &ecspi1; usb0 = &usbh1; usb1 = &usbotg; - usdhc2 = &usdhc3; }; chosen { @@ -40,23 +38,25 @@ leds { compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; led0: user1 { label = "user1"; - gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 -> MX6_PANLEDG */ default-state = "on"; linux,default-trigger = "heartbeat"; }; led1: user2 { label = "user2"; - gpios = <&gpio4 10 0>; /* 106 -> MX6_PANLEDR */ + gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; /* 106 -> MX6_PANLEDR */ default-state = "off"; }; led2: user3 { label = "user3"; - gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */ + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* 111 -> MX6_LOCLED# */ default-state = "off"; }; }; @@ -67,7 +67,9 @@ pps { compatible = "pps-gpio"; - gpios = <&gpio1 5 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -109,7 +111,7 @@ regulator-name = "usb_otg_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 0>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; enable-active-high; }; }; @@ -137,7 +139,7 @@ &ecspi1 { fsl,spi-num-chipselects = <1>; - cs-gpios = <&gpio3 19 0>; + cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; status = "okay"; @@ -153,7 +155,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 30 0>; + phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -199,11 +201,6 @@ #gpio-cells = <2>; }; - hwmon: gsc@29 { - compatible = "gw,gsp"; - reg = <0x29>; - }; - rtc: ds1672@68 { compatible = "dallas,ds1672"; reg = <0x68>; @@ -314,16 +311,6 @@ }; }; }; - - pciswitch: pex8609@3f { - compatible = "plx,pex8609"; - reg = <0x3f>; - }; - - pciclkgen: si52147@6b { - compatible = "sil,si52147"; - reg = <0x6b>; - }; }; &i2c3 { @@ -345,51 +332,73 @@ VDDIO-supply = <®_3p3v>; }; - hdmiin: adv7611@4c { - compatible = "adi,adv7611"; - reg = <0x4c>; - }; - touchscreen: egalax_ts@04 { compatible = "eeti,egalax_ts"; reg = <0x04>; interrupt-parent = <&gpio7>; - interrupts = <12 2>; /* gpio7_12 active low */ - wakeup-gpios = <&gpio7 12 0>; + interrupts = <12 2>; + wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; }; +}; - videoout: adv7393@2a { - compatible = "adi,adv7393"; - reg = <0x2a>; - }; +&ldb { + status = "okay"; +}; + +&pcie { + reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; + status = "okay"; - videoin: adv7180@20 { - compatible = "adi,adv7180"; - reg = <0x20>; + eth1: sky2@8 { /* MAC/PHY on bus 8 */ + compatible = "marvell,sky2"; }; }; -&iomuxc { +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usdhc3 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; +&iomuxc { imx6q-gw5400-a { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* SPINOR_CS0# */ - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE RST */ - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 /* GPS_PPS */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* TOUCH_IRQ# */ - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ - MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x80000000 /* user2 led */ - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */ - MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000 /* USBHUB_RST# */ - MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x80000000 /* MIPI_DIO */ - >; - }; pinctrl_audmux: audmuxgrp { fsl,pins = < @@ -397,6 +406,7 @@ MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ >; }; @@ -405,6 +415,7 @@ MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 /* SPINOR_CS0# */ >; }; @@ -429,6 +440,14 @@ >; }; + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 /* user1 led */ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 /* user2 led */ + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 /* user3 led */ + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 @@ -450,6 +469,19 @@ >; }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 /* GPS_PPS */ + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 @@ -474,6 +506,7 @@ pinctrl_usbotg: usbotggrp { fsl,pins = < MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ >; }; @@ -489,59 +522,3 @@ }; }; }; - -&ldb { - status = "okay"; -}; - -&pcie { - reset-gpio = <&gpio1 29 0>; - status = "okay"; - - eth1: sky2@8 { /* MAC/PHY on bus 8 */ - compatible = "marvell,sky2"; - }; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 0 0>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6q-gw552x.dts b/arch/arm/boot/dts/imx6q-gw552x.dts new file mode 100644 index 000000000000..f87a8fa6e04d --- /dev/null +++ b/arch/arm/boot/dts/imx6q-gw552x.dts @@ -0,0 +1,24 @@ +/* + * Copyright 2014 Gateworks Corporation + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-gw552x.dtsi" + +/ { + model = "Gateworks Ventana i.MX6 Dual/Quad GW552X"; + compatible = "gw,imx6q-gw552x", "gw,ventana", "fsl,imx6q"; +}; + +&sata { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6q-hummingboard.dts b/arch/arm/boot/dts/imx6q-hummingboard.dts new file mode 100644 index 000000000000..c2bf8476ce45 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-hummingboard.dts @@ -0,0 +1,21 @@ +/* + * Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com) + * Based on dt work by Russell King + */ +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-hummingboard.dtsi" + +/ { + model = "SolidRun HummingBoard Dual/Quad"; + compatible = "solidrun,hummingboard/q", "fsl,imx6q"; +}; + +&sata { + status = "okay"; + fsl,transmit-level-mV = <1025>; + fsl,transmit-boost-mdB = <3330>; + fsl,transmit-atten-16ths = <9>; + fsl,receive-eq-mdB = <3000>; +}; diff --git a/arch/arm/boot/dts/imx6q-tbs2910.dts b/arch/arm/boot/dts/imx6q-tbs2910.dts new file mode 100644 index 000000000000..a43abfa21e33 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-tbs2910.dts @@ -0,0 +1,432 @@ +/* + * Copyright 2014 Soeren Moch <smoch@web.de> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include "imx6q.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + model = "TBS2910 Matrix ARM mini PC"; + compatible = "tbs,imx6q-tbs2910", "fsl,imx6q"; + + chosen { + stdout-path = &uart1; + }; + + memory { + reg = <0x10000000 0x80000000>; + }; + + fan { + compatible = "gpio-fan"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_fan>; + gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = <0 0 + 3000 1>; + }; + + ir_recv { + compatible = "gpio-ir-receiver"; + gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ir>; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + blue { + label = "blue_status_led"; + gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_2p5v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + reg_3p3v: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5p0v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "5P0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + }; + + sound-sgtl5000 { + audio-codec = <&sgtl5000>; + audio-routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "Headphone Jack", "HP_OUT"; + compatible = "fsl,imx-audio-sgtl5000"; + model = "On-board Codec"; + mux-ext-port = <3>; + mux-int-port = <1>; + ssi-controller = <&ssi1>; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "On-board SPDIF"; + spdif-controller = <&spdif>; + spdif-out; + }; +}; + +&audmux { + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi>; + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + sgtl5000: sgtl5000@0a { + clocks = <&clks 201>; + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgtl5000>; + reg = <0x0a>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + rtc: ds1307@68 { + compatible = "dallas,ds1307"; + reg = <0x68>; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_5p0v>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_5p0v>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <4>; + cd-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <4>; + cd-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&usdhc4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc4>; + bus-width = <8>; + non-removable; + no-1-8-v; + status = "okay"; +}; + +&iomuxc { + imx6q-tbs2910 { + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b059 + >; + }; + + pinctrl_hdmi: hdmigrp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_ir: irgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x17059 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x17059 + >; + }; + + pinctrl_sgtl5000: sgtl5000grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 + >; + }; + + pinctrl_spdif: spdifgrp { + fsl,pins = <MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x13091 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x17059 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x17059 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x17059 + >; + }; + + pinctrl_usdhc4: usdhc4grp { + fsl,pins = < + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 + >; + }; + }; + + gpio_fan { + pinctrl_gpio_fan: gpiofangrp { + fsl,pins = < + MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x130b1 + >; + }; + }; + + gpio_leds { + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b1 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index e9f3646d1760..85f72e6b5bad 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -308,3 +308,7 @@ }; }; }; + +&vpu { + compatible = "fsl,imx6q-vpu", "cnm,coda960"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi index 0db15af41cb1..f2867c4b34a8 100644 --- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi @@ -9,11 +9,11 @@ * http://www.gnu.org/copyleft/gpl.html */ +#include <dt-bindings/gpio/gpio.h> + / { /* these are used by bootloader for disabling nodes */ aliases { - can0 = &can1; - ethernet0 = &fec; led0 = &led0; led1 = &led1; nand = &gpmi; @@ -27,17 +27,19 @@ leds { compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; led0: user1 { label = "user1"; - gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ default-state = "on"; linux,default-trigger = "heartbeat"; }; led1: user2 { label = "user2"; - gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */ + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ default-state = "off"; }; }; @@ -48,7 +50,9 @@ pps { compatible = "pps-gpio"; - gpios = <&gpio1 26 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -81,7 +85,7 @@ regulator-name = "usb_otg_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 0>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; enable-active-high; }; }; @@ -91,7 +95,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 30 0>; + phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -143,11 +147,6 @@ #gpio-cells = <2>; }; - hwmon: gsc@29 { - compatible = "gw,gsp"; - reg = <0x29>; - }; - rtc: ds1672@68 { compatible = "dallas,ds1672"; reg = <0x68>; @@ -159,53 +158,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - - pmic: ltc3676@3c { - compatible = "lltc,ltc3676"; - reg = <0x3c>; - - regulators { - sw1_reg: ltc3676__sw1 { - regulator-min-microvolt = <1175000>; - regulator-max-microvolt = <1175000>; - regulator-boot-on; - regulator-always-on; - }; - - sw2_reg: ltc3676__sw2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3_reg: ltc3676__sw3 { - regulator-min-microvolt = <1175000>; - regulator-max-microvolt = <1175000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: ltc3676__sw4 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: ltc3676__ldo2 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4_reg: ltc3676__ldo4 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - }; - }; }; &i2c3 { @@ -213,31 +165,53 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; +}; - videoin: adv7180@20 { - compatible = "adi,adv7180"; - reg = <0x20>; - }; +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; + status = "okay"; }; -&iomuxc { +&uart1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; - imx6qdl-gw51xx { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 /* MEZZ_DIO0 */ - MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 /* MEZZ_DIO1 */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */ - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* PHY Reset */ - MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x80000000 /* PCIE_RST# */ - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */ - >; - }; +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&iomuxc { + imx6qdl-gw51xx { pinctrl_enet: enetgrp { fsl,pins = < MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 @@ -256,6 +230,14 @@ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */ + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 >; }; @@ -301,6 +283,18 @@ >; }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 @@ -332,48 +326,8 @@ pinctrl_usbotg: usbotggrp { fsl,pins = < MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ >; }; }; }; - -&pcie { - reset-gpio = <&gpio1 0 0>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi index 234e7b755232..b5756c21ea1d 100644 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi @@ -9,10 +9,11 @@ * http://www.gnu.org/copyleft/gpl.html */ +#include <dt-bindings/gpio/gpio.h> + / { /* these are used by bootloader for disabling nodes */ aliases { - ethernet0 = &fec; led0 = &led0; led1 = &led1; led2 = &led2; @@ -20,7 +21,6 @@ ssi0 = &ssi1; usb0 = &usbh1; usb1 = &usbotg; - usdhc2 = &usdhc3; }; chosen { @@ -36,23 +36,25 @@ leds { compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; led0: user1 { label = "user1"; - gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ default-state = "on"; linux,default-trigger = "heartbeat"; }; led1: user2 { label = "user2"; - gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */ + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ default-state = "off"; }; led2: user3 { label = "user3"; - gpios = <&gpio4 15 1>; /* 111 - MX6_LOCLED# */ + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ default-state = "off"; }; }; @@ -63,7 +65,9 @@ pps { compatible = "pps-gpio"; - gpios = <&gpio1 26 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -115,7 +119,7 @@ regulator-name = "usb_otg_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 0>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; enable-active-high; }; }; @@ -141,11 +145,17 @@ status = "okay"; }; +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 30 0>; + phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -197,11 +207,6 @@ #gpio-cells = <2>; }; - hwmon: gsc@29 { - compatible = "gw,gsp"; - reg = <0x29>; - }; - rtc: ds1672@68 { compatible = "dallas,ds1672"; reg = <0x68>; @@ -213,65 +218,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - - pciswitch: pex8609@3f { - compatible = "plx,pex8609"; - reg = <0x3f>; - }; - - pmic: ltc3676@3c { - compatible = "lltc,ltc3676"; - reg = <0x3c>; - - regulators { - sw1_reg: ltc3676__sw1 { - regulator-min-microvolt = <1175000>; - regulator-max-microvolt = <1175000>; - regulator-boot-on; - regulator-always-on; - }; - - sw2_reg: ltc3676__sw2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - sw3_reg: ltc3676__sw3 { - regulator-min-microvolt = <1175000>; - regulator-max-microvolt = <1175000>; - regulator-boot-on; - regulator-always-on; - }; - - sw4_reg: ltc3676__sw4 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo2_reg: ltc3676__ldo2 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo3_reg: ltc3676__ldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - ldo4_reg: ltc3676__ldo4 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - }; - }; }; &i2c3 { @@ -280,11 +226,6 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - accelerometer: fxos8700@1e { - compatible = "fsl,fxos8700"; - reg = <0x13>; - }; - codec: sgtl5000@0a { compatible = "fsl,sgtl5000"; reg = <0x0a>; @@ -297,49 +238,100 @@ compatible = "eeti,egalax_ts"; reg = <0x04>; interrupt-parent = <&gpio7>; - interrupts = <12 2>; /* gpio7_12 active low */ - wakeup-gpios = <&gpio7 12 0>; + interrupts = <12 2>; + wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; }; +}; + +&ldb { + status = "okay"; - videoin: adv7180@20 { - compatible = "adi,adv7180"; - reg = <0x20>; + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; }; }; -&iomuxc { +&pcie { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; + status = "okay"; +}; - imx6qdl-gw52xx { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 /* MEZZ_DIO0 */ - MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 /* MEZZ_DIO1 */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ - MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x80000000 /* VIDDEC_PDN# */ - MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* PHY Reset */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE_RST# */ - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 /* GPS_PWDN */ - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */ - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* USB_SEL_PCI */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* TOUCH_IRQ# */ - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */ - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */ - MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x80000000 /* LVDS_TCH# */ - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* SD3_CD# */ - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x80000000 /* UART2_EN# */ - >; - }; +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; +&iomuxc { + imx6qdl-gw52xx { pinctrl_audmux: audmuxgrp { fsl,pins = < MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ >; }; @@ -361,6 +353,23 @@ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */ + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 >; }; @@ -406,6 +415,18 @@ >; }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */ + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 + >; + }; + pinctrl_pwm4: pwm4grp { fsl,pins = < MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 @@ -436,6 +457,7 @@ pinctrl_usbotg: usbotggrp { fsl,pins = < MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ >; }; @@ -447,85 +469,8 @@ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */ >; }; }; }; - -&ldb { - status = "okay"; - - lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - }; - }; - }; -}; - -&pcie { - reset-gpio = <&gpio1 29 0>; - status = "okay"; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 0 0>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi index 143f84f7812c..86f03c1b147c 100644 --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi @@ -9,21 +9,19 @@ * http://www.gnu.org/copyleft/gpl.html */ +#include <dt-bindings/gpio/gpio.h> + / { /* these are used by bootloader for disabling nodes */ aliases { - can0 = &can1; - ethernet0 = &fec; ethernet1 = ð1; led0 = &led0; led1 = &led1; led2 = &led2; nand = &gpmi; - sky2 = ð1; ssi0 = &ssi1; usb0 = &usbh1; usb1 = &usbotg; - usdhc2 = &usdhc3; }; chosen { @@ -39,23 +37,25 @@ leds { compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; led0: user1 { label = "user1"; - gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ default-state = "on"; linux,default-trigger = "heartbeat"; }; led1: user2 { label = "user2"; - gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */ + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ default-state = "off"; }; led2: user3 { label = "user3"; - gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */ + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ default-state = "off"; }; }; @@ -66,7 +66,9 @@ pps { compatible = "pps-gpio"; - gpios = <&gpio1 26 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -118,7 +120,7 @@ regulator-name = "usb_otg_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 0>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; enable-active-high; }; }; @@ -154,7 +156,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 30 0>; + phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -206,11 +208,6 @@ #gpio-cells = <2>; }; - hwmon: gsc@29 { - compatible = "gw,gsp"; - reg = <0x29>; - }; - rtc: ds1672@68 { compatible = "dallas,ds1672"; reg = <0x68>; @@ -222,77 +219,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; - - pciclkgen: si53156@6b { - compatible = "sil,si53156"; - reg = <0x6b>; - }; - - pciswitch: pex8606@3f { - compatible = "plx,pex8606"; - reg = <0x3f>; - }; - - pmic: ltc3676@3c { - compatible = "lltc,ltc3676"; - reg = <0x3c>; - - regulators { - /* VDD_SOC */ - sw1_reg: ltc3676__sw1 { - regulator-min-microvolt = <1175000>; - regulator-max-microvolt = <1175000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_1P8 */ - sw2_reg: ltc3676__sw2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_ARM */ - sw3_reg: ltc3676__sw3 { - regulator-min-microvolt = <1175000>; - regulator-max-microvolt = <1175000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_DDR */ - sw4_reg: ltc3676__sw4 { - regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <1500000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_2P5 */ - ldo2_reg: ltc3676__ldo2 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_1P8 */ - ldo3_reg: ltc3676__ldo3 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - /* VDD_HIGH */ - ldo4_reg: ltc3676__ldo4 { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - }; - }; - }; }; &i2c3 { @@ -301,11 +227,6 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - accelerometer: fxos8700@1e { - compatible = "fsl,fxos8700"; - reg = <0x1e>; - }; - codec: sgtl5000@0a { compatible = "fsl,sgtl5000"; reg = <0x0a>; @@ -314,65 +235,109 @@ VDDIO-supply = <®_3p3v>; }; - hdmiin: adv7611@4c { - compatible = "adi,adv7611"; - reg = <0x4c>; - }; - touchscreen: egalax_ts@04 { compatible = "eeti,egalax_ts"; reg = <0x04>; interrupt-parent = <&gpio1>; - interrupts = <11 2>; /* gpio1_11 active low */ - wakeup-gpios = <&gpio1 11 0>; + interrupts = <11 2>; + wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; }; +}; - videoout: adv7393@2a { - compatible = "adi,adv7393"; - reg = <0x2a>; +&ldb { + status = "okay"; + + lvds-channel@1 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; }; +}; - videoin: adv7180@20 { - compatible = "adi,adv7180"; - reg = <0x20>; +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; + status = "okay"; + + eth1: sky2@8 { /* MAC/PHY on bus 8 */ + compatible = "marvell,sky2"; }; }; -&iomuxc { +&pwm4 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; - imx6qdl-gw53xx { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 /* PCIE6EXP_DIO0 */ - MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 /* PCIE6EXP_DIO1 */ - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ - MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 /* GPS_SHDN */ - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */ - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE RST */ - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAN_STBY */ - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x80000000 /* PMIC_IRQ# */ - MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000 /* HUB_RST# */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* PCIE_WDIS# */ - MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000 /* ACCEL_IRQ# */ - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ - MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x80000000 /* USBOTG_OC# */ - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */ - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */ - MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x80000000 /* TOUCH_IRQ# */ - MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* SD3_DET# */ - >; - }; +&ssi1 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; + +&iomuxc { + imx6qdl-gw53xx { pinctrl_audmux: audmuxgrp { fsl,pins = < MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ >; }; @@ -399,8 +364,17 @@ pinctrl_flexcan1: flexcan1grp { fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 >; }; @@ -446,6 +420,19 @@ >; }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 + >; + }; + pinctrl_pwm4: pwm4grp { fsl,pins = < MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 @@ -476,6 +463,8 @@ pinctrl_usbotg: usbotggrp { fsl,pins = < MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ >; }; @@ -487,90 +476,8 @@ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */ >; }; }; }; - -&ldb { - status = "okay"; - - lvds-channel@1 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - }; - }; - }; -}; - -&pcie { - reset-gpio = <&gpio1 29 0>; - status = "okay"; - - eth1: sky2@8 { /* MAC/PHY on bus 8 */ - compatible = "marvell,sky2"; - }; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 0 0>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index 16e7ad3d98ad..4a8d97f47759 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -9,21 +9,19 @@ * http://www.gnu.org/copyleft/gpl.html */ +#include <dt-bindings/gpio/gpio.h> + / { /* these are used by bootloader for disabling nodes */ aliases { - can0 = &can1; - ethernet0 = &fec; ethernet1 = ð1; led0 = &led0; led1 = &led1; led2 = &led2; nand = &gpmi; - sky2 = ð1; ssi0 = &ssi1; usb0 = &usbh1; usb1 = &usbotg; - usdhc2 = &usdhc3; }; chosen { @@ -39,23 +37,25 @@ leds { compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; led0: user1 { label = "user1"; - gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ default-state = "on"; linux,default-trigger = "heartbeat"; }; led1: user2 { label = "user2"; - gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */ + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ default-state = "off"; }; led2: user3 { label = "user3"; - gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */ + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ default-state = "off"; }; }; @@ -66,7 +66,9 @@ pps { compatible = "pps-gpio"; - gpios = <&gpio1 26 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pps>; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; status = "okay"; }; @@ -108,7 +110,7 @@ regulator-name = "usb_otg_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; - gpio = <&gpio3 22 0>; + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; enable-active-high; }; }; @@ -144,7 +146,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii"; - phy-reset-gpios = <&gpio1 30 0>; + phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -196,11 +198,6 @@ #gpio-cells = <2>; }; - hwmon: gsc@29 { - compatible = "gw,gsp"; - reg = <0x29>; - }; - rtc: ds1672@68 { compatible = "dallas,ds1672"; reg = <0x68>; @@ -311,16 +308,6 @@ }; }; }; - - pciswitch: pex8609@3f { - compatible = "plx,pex8609"; - reg = <0x3f>; - }; - - pciclkgen: si52147@6b { - compatible = "sil,si52147"; - reg = <0x6b>; - }; }; &i2c3 { @@ -329,11 +316,6 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - accelerometer: fxos8700@1e { - compatible = "fsl,fxos8700"; - reg = <0x1e>; - }; - codec: sgtl5000@0a { compatible = "fsl,sgtl5000"; reg = <0x0a>; @@ -342,59 +324,113 @@ VDDIO-supply = <®_3p3v>; }; - hdmiin: adv7611@4c { - compatible = "adi,adv7611"; - reg = <0x4c>; - }; - touchscreen: egalax_ts@04 { compatible = "eeti,egalax_ts"; reg = <0x04>; interrupt-parent = <&gpio7>; - interrupts = <12 2>; /* gpio7_12 active low */ - wakeup-gpios = <&gpio7 12 0>; + interrupts = <12 2>; + wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; }; +}; - videoout: adv7393@2a { - compatible = "adi,adv7393"; - reg = <0x2a>; +&ldb { + status = "okay"; + + lvds-channel@1 { + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + display-timings { + native-mode = <&timing0>; + timing0: hsd100pxn1 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <220>; + hfront-porch = <40>; + vback-porch = <21>; + vfront-porch = <7>; + hsync-len = <60>; + vsync-len = <10>; + }; + }; }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; + status = "okay"; - videoin: adv7180@20 { - compatible = "adi,adv7180"; - reg = <0x20>; + eth1: sky2@8 { /* MAC/PHY on bus 8 */ + compatible = "marvell,sky2"; }; }; -&iomuxc { +&pwm4 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; - imx6qdl-gw54xx { - pinctrl_hog: hoggrp { - fsl,pins = < - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ - MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* SPINOR_CS0# */ - MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */ - MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE RST */ - MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAN_STBY */ - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* TOUCH_IRQ# */ - MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ - MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */ - MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */ - MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000 /* USBHUB_RST# */ - MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x80000000 /* MIPI_DIO */ - >; - }; +&ssi1 { + status = "okay"; +}; + +&ssi2 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + cd-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_3p3v>; + status = "okay"; +}; +&iomuxc { + imx6qdl-gw54xx { pinctrl_audmux: audmuxgrp { fsl,pins = < MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 + MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ >; }; @@ -421,8 +457,17 @@ pinctrl_flexcan1: flexcan1grp { fsl,pins = < - MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000 - MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000 + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */ + >; + }; + + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 >; }; @@ -468,6 +513,19 @@ >; }; + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */ + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */ + >; + }; + + pinctrl_pps: ppsgrp { + fsl,pins = < + MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 + >; + }; + pinctrl_pwm4: pwm4grp { fsl,pins = < MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 @@ -498,6 +556,7 @@ pinctrl_usbotg: usbotggrp { fsl,pins = < MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ >; }; @@ -513,90 +572,3 @@ }; }; }; - -&ldb { - status = "okay"; - - lvds-channel@1 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; - - display-timings { - native-mode = <&timing0>; - timing0: hsd100pxn1 { - clock-frequency = <65000000>; - hactive = <1024>; - vactive = <768>; - hback-porch = <220>; - hfront-porch = <40>; - vback-porch = <21>; - vfront-porch = <7>; - hsync-len = <60>; - vsync-len = <10>; - }; - }; - }; -}; - -&pcie { - reset-gpio = <&gpio1 29 0>; - status = "okay"; - - eth1: sky2@8 { /* MAC/PHY on bus 8 */ - compatible = "marvell,sky2"; - }; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&ssi1 { - status = "okay"; -}; - -&ssi2 { - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - status = "okay"; -}; - -&usbotg { - vbus-supply = <®_usb_otg_vbus>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usb_h1_vbus>; - status = "okay"; -}; - -&usdhc3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>; - cd-gpios = <&gpio7 0 0>; - vmmc-supply = <®_3p3v>; - status = "okay"; -}; diff --git a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi new file mode 100644 index 000000000000..5c6587f6c420 --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi @@ -0,0 +1,267 @@ +/* + * Copyright 2014 Gateworks Corporation + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <dt-bindings/gpio/gpio.h> + +/ { + /* these are used by bootloader for disabling nodes */ + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + nand = &gpmi; + usb0 = &usbh1; + usb1 = &usbotg; + }; + + chosen { + bootargs = "console=ttymxc1,115200"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led0: user1 { + label = "user1"; + gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led1: user2 { + label = "user2"; + gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ + default-state = "off"; + }; + + led2: user3 { + label = "user3"; + gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ + default-state = "off"; + }; + }; + + memory { + reg = <0x10000000 0x20000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_1p0v: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "1P0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + reg_3p3v: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5p0v: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "5P0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&hdmi { + ddc-i2c-bus = <&i2c3>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + eeprom1: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + eeprom2: eeprom@51 { + compatible = "atmel,24c02"; + reg = <0x51>; + pagesize = <16>; + }; + + eeprom3: eeprom@52 { + compatible = "atmel,24c02"; + reg = <0x52>; + pagesize = <16>; + }; + + eeprom4: eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + + gpio: pca9555@23 { + compatible = "nxp,pca9555"; + reg = <0x23>; + gpio-controller; + #gpio-cells = <2>; + }; + + rtc: ds1672@68 { + compatible = "dallas,ds1672"; + reg = <0x68>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; }; + +&usbh1 { + status = "okay"; +}; + +&iomuxc { + imx6qdl-gw552x { + pinctrl_gpio_leds: gpioledsgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpminandgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi new file mode 100644 index 000000000000..62841e85a91e --- /dev/null +++ b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi @@ -0,0 +1,200 @@ +/* + * Copyright (C) 2013,2014 Russell King + */ +#include "imx6qdl-microsom.dtsi" +#include "imx6qdl-microsom-ar8035.dtsi" + +/ { + chosen { + stdout-path = &uart1; + }; + + ir_recv: ir-receiver { + compatible = "gpio-ir-receiver"; + gpios = <&gpio3 5 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_gpio3_5>; + }; + + regulators { + compatible = "simple-bus"; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbh1_vbus: usb-h1-vbus { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 0 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_usbh1_vbus>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbotg_vbus: usb-otg-vbus { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 22 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "On-board SPDIF"; + /* IMX6 doesn't implement this yet */ + spdif-controller = <&spdif>; + spdif-out; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_flexcan1>; + status = "okay"; +}; + +&hdmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_hdmi>; + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_i2c1>; + + /* + * Not fitted on Carrier-1 board... yet + status = "okay"; + + rtc: pcf8523@68 { + compatible = "nxp,pcf8523"; + reg = <0x68>; + }; + */ +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_i2c2>; + status = "okay"; +}; + +&iomuxc { + hummingboard { + pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x80000000 + MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x80000000 + >; + }; + + pinctrl_hummingboard_gpio3_5: hummingboard-gpio3_5 { + fsl,pins = < + MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0b1 + >; + }; + + pinctrl_hummingboard_hdmi: hummingboard-hdmi { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0 + >; + }; + + pinctrl_hummingboard_i2c1: hummingboard-i2c1 { + fsl,pins = < + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_hummingboard_i2c2: hummingboard-i2c2 { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_hummingboard_spdif: hummingboard-spdif { + fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>; + }; + + pinctrl_hummingboard_usbh1_vbus: hummingboard-usbh1-vbus { + fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0>; + }; + + pinctrl_hummingboard_usbotg_id: hummingboard-usbotg-id { + /* + * Similar to pinctrl_usbotg_2, but we want it + * pulled down for a fixed host connection. + */ + fsl,pins = <MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059>; + }; + + pinctrl_hummingboard_usbotg_vbus: hummingboard-usbotg-vbus { + fsl,pins = <MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0>; + }; + + pinctrl_hummingboard_usdhc2_aux: hummingboard-usdhc2-aux { + fsl,pins = < + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1f071 + >; + }; + + pinctrl_hummingboard_usdhc2: hummingboard-usdhc2 { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059 + >; + }; + }; +}; + +&spdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_spdif>; + status = "okay"; +}; + +&usbh1 { + disable-over-current; + vbus-supply = <®_usbh1_vbus>; + status = "okay"; +}; + +&usbotg { + disable-over-current; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hummingboard_usbotg_id>; + vbus-supply = <®_usbotg_vbus>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_hummingboard_usdhc2_aux + &pinctrl_hummingboard_usdhc2 + >; + vmmc-supply = <®_3p3v>; + cd-gpios = <&gpio1 4 0>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi index 42ff525ebe13..08218120e770 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi @@ -174,6 +174,11 @@ status = "okay"; }; +&hdmi { + ddc-i2c-bus = <&i2c2>; + status = "okay"; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -187,6 +192,25 @@ VDDA-supply = <®_2p5v>; VDDIO-supply = <®_3p3v>; }; + + rtc: rtc@6f { + compatible = "isil,isl1208"; + reg = <0x6f>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; }; &iomuxc { @@ -266,6 +290,20 @@ >; }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 + >; + }; + pinctrl_pwm1: pwm1grp { fsl,pins = < MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi index 584721264121..585b4f6986c1 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi @@ -9,17 +9,103 @@ * http://www.gnu.org/copyleft/gpl.html */ +#include <dt-bindings/sound/fsl-imx-audmux.h> + / { chosen { linux,stdout-path = &uart4; }; + + regulators { + sound_1v8: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "i2s-audio-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + sound_3v3: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "i2s-audio-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + + tlv320_mclk: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + clock-output-names = "tlv320-mclk"; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "OnboardTLV320AIC3007"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Line", "Line In", + "Line", "Line Out", + "Speaker", "Speaker", + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Line Out", "LLOUT", + "Line Out", "RLOUT", + "Speaker", "SPOP", + "Speaker", "SPOM", + "Headphone Jack", "HPLOUT", + "Headphone Jack", "HPROUT", + "MIC3L", "Mic Jack", + "MIC3R", "Mic Jack", + "Mic Jack", "Mic Bias", + "LINE1L", "Line In", + "LINE1R", "Line In"; + + simple-audio-card,cpu { + sound-dai = <&ssi2>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&codec>; + clocks = <&tlv320_mclk>; + }; + }; + }; -&fec { +&audmux { status = "okay"; + + ssi2 { + fsl,audmux-port = <1>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TFSEL(4) | + IMX_AUDMUX_V2_PTCR_TCLKDIR | + IMX_AUDMUX_V2_PTCR_TCSEL(4)) + IMX_AUDMUX_V2_PDCR_RXDSEL(4) + >; + }; + + pins5 { + fsl,audmux-port = <4>; + fsl,port-config = < + 0x00000000 + IMX_AUDMUX_V2_PDCR_RXDSEL(1) + >; + }; }; -&gpmi { +&can1 { + status = "okay"; +}; + +&fec { status = "okay"; }; @@ -28,14 +114,18 @@ }; &i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - clock-frequency = <100000>; status = "okay"; - tlv320@18 { - compatible = "ti,tlv320aic3x"; + codec: tlv320@18 { + compatible = "ti,tlv320aic3007"; + #sound-dai-cells = <0>; reg = <0x18>; + ai3x-micbias-vg = <2>; + + AVDD-supply = <&sound_3v3>; + IOVDD-supply = <&sound_3v3>; + DRVDD-supply = <&sound_3v3>; + DVDD-supply = <&sound_1v8>; }; stmpe@41 { @@ -55,9 +145,14 @@ }; &i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - clock-frequency = <100000>; + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +&ssi2 { status = "okay"; }; @@ -84,19 +179,3 @@ &usdhc3 { status = "okay"; }; - -&iomuxc { - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 - >; - }; -}; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index 2694aa84e187..19cc269a08d4 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -58,6 +58,18 @@ }; }; +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "disabled"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "disabled"; +}; + &ecspi3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi3>; @@ -72,6 +84,22 @@ }; }; +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; + phy-supply = <&vdd_eth_io_reg>; + status = "disabled"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + status = "okay"; +}; + &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; @@ -83,10 +111,10 @@ }; pmic@58 { - compatible = "dialog,da9063"; + compatible = "dlg,da9063"; reg = <0x58>; - interrupt-parent = <&gpio4>; - interrupts = <17 0x8>; /* active-low GPIO4_17 */ + interrupt-parent = <&gpio2>; + interrupts = <9 0x8>; /* active-low GPIO2_9 */ regulators { vddcore_reg: bcore1 { @@ -162,6 +190,18 @@ }; }; +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + clock-frequency = <100000>; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + clock-frequency = <100000>; +}; + &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; @@ -171,7 +211,7 @@ fsl,pins = < MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */ - MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000 /* PMIC interrupt */ + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x80000000 /* PMIC interrupt */ MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */ MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */ >; @@ -206,6 +246,13 @@ >; }; + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 + >; + }; + pinctrl_gpmi_nand: gpminandgrp { fsl,pins = < MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 @@ -235,6 +282,24 @@ >; }; + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = <MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000>; + }; + pinctrl_uart3: uart3grp { fsl,pins = < MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 @@ -293,22 +358,22 @@ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 >; }; - }; -}; -&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; - phy-supply = <&vdd_eth_io_reg>; - status = "disabled"; + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0 + MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x110b0 + MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0 + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 + >; + }; + }; }; -&gpmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; +&pcie { + pinctrl-name = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio4 17 0>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6qdl-rex.dtsi b/arch/arm/boot/dts/imx6qdl-rex.dtsi index df7bcf86c156..488a640796ac 100644 --- a/arch/arm/boot/dts/imx6qdl-rex.dtsi +++ b/arch/arm/boot/dts/imx6qdl-rex.dtsi @@ -308,7 +308,6 @@ }; &ssi1 { - fsl,mode = "i2s-slave"; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index ec43dde78525..f1cd2147421d 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -54,6 +54,19 @@ gpio = <&gpio4 10 0>; enable-active-high; }; + + reg_pcie: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_reg>; + regulator-name = "MPCIE_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio3 19 0>; + regulator-always-on; + enable-active-high; + }; }; gpio-keys { @@ -94,10 +107,8 @@ "Headphone Jack", "HPOUTR", "Ext Spk", "SPKOUTL", "Ext Spk", "SPKOUTR", - "MICBIAS", "AMIC", - "IN3R", "MICBIAS", - "DMIC", "MICBIAS", - "DMICDAT", "DMIC"; + "AMIC", "MICBIAS", + "IN3R", "AMIC"; mux-int-port = <2>; mux-ext-port = <3>; }; @@ -166,7 +177,7 @@ codec: wm8962@1a { compatible = "wlf,wm8962"; reg = <0x1a>; - clocks = <&clks 201>; + clocks = <&clks IMX6QDL_CLK_CKO>; DCVDD-supply = <®_audio>; DBVDD-supply = <®_audio>; AVDD-supply = <®_audio>; @@ -314,15 +325,15 @@ imx6qdl-sabresd { pinctrl_hog: hoggrp { fsl,pins = < - MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000 - MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000 - MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000 - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000 + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 - MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000 - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 - MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000 + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0 + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 + MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 >; }; @@ -367,9 +378,9 @@ pinctrl_gpio_keys: gpio_keysgrp { fsl,pins = < - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 - MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 - MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b0 + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0 >; }; @@ -396,7 +407,13 @@ pinctrl_pcie: pciegrp { fsl,pins = < - MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0 + >; + }; + + pinctrl_pcie_reg: pciereggrp { + fsl,pins = < + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0 >; }; @@ -468,7 +485,7 @@ gpio_leds { pinctrl_gpio_leds: gpioledsgrp { fsl,pins = < - MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 >; }; }; @@ -512,6 +529,10 @@ status = "okay"; }; +&snvs_poweroff { + status = "okay"; +}; + &ssi2 { status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index c701af958006..4fc03b7f1cee 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -137,7 +137,9 @@ pcie: pcie@0x01000000 { compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; - reg = <0x01ffc000 0x4000>; /* DBI */ + reg = <0x01ffc000 0x04000>, + <0x01f00000 0x80000>; + reg-names = "dbi", "config"; #address-cells = <3>; #size-cells = <2>; device_type = "pci"; @@ -273,11 +275,14 @@ }; ssi1: ssi@02028000 { + #sound-dai-cells = <0>; compatible = "fsl,imx6q-ssi", "fsl,imx51-ssi"; reg = <0x02028000 0x4000>; interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_SSI1_IPG>; + clocks = <&clks IMX6QDL_CLK_SSI1_IPG>, + <&clks IMX6QDL_CLK_SSI1>; + clock-names = "ipg", "baud"; dmas = <&sdma 37 1 0>, <&sdma 38 1 0>; dma-names = "rx", "tx"; @@ -286,11 +291,14 @@ }; ssi2: ssi@0202c000 { + #sound-dai-cells = <0>; compatible = "fsl,imx6q-ssi", "fsl,imx51-ssi"; reg = <0x0202c000 0x4000>; interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_SSI2_IPG>; + clocks = <&clks IMX6QDL_CLK_SSI2_IPG>, + <&clks IMX6QDL_CLK_SSI2>; + clock-names = "ipg", "baud"; dmas = <&sdma 41 1 0>, <&sdma 42 1 0>; dma-names = "rx", "tx"; @@ -299,11 +307,14 @@ }; ssi3: ssi@02030000 { + #sound-dai-cells = <0>; compatible = "fsl,imx6q-ssi", "fsl,imx51-ssi"; reg = <0x02030000 0x4000>; interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_SSI3_IPG>; + clocks = <&clks IMX6QDL_CLK_SSI3_IPG>, + <&clks IMX6QDL_CLK_SSI3>; + clock-names = "ipg", "baud"; dmas = <&sdma 45 1 0>, <&sdma 46 1 0>; dma-names = "rx", "tx"; @@ -322,9 +333,17 @@ }; vpu: vpu@02040000 { + compatible = "cnm,coda960"; reg = <0x02040000 0x3c000>; interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>, <0 12 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "bit", "jpeg"; + clocks = <&clks IMX6QDL_CLK_VPU_AXI>, + <&clks IMX6QDL_CLK_MMDC_CH0_AXI>, + <&clks IMX6QDL_CLK_OCRAM>; + clock-names = "per", "ahb", "ocram"; + resets = <&src 1>; + iram = <&ocram>; }; aipstz@0207c000 { /* AIPSTZ1 */ @@ -396,8 +415,9 @@ reg = <0x02098000 0x4000>; interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_GPT_IPG>, - <&clks IMX6QDL_CLK_GPT_IPG_PER>; - clock-names = "ipg", "per"; + <&clks IMX6QDL_CLK_GPT_IPG_PER>, + <&clks IMX6QDL_CLK_GPT_3M>; + clock-names = "ipg", "per", "osc_per"; }; gpio1: gpio@0209c000 { @@ -645,6 +665,12 @@ interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, <0 20 IRQ_TYPE_LEVEL_HIGH>; }; + + snvs_poweroff: snvs-poweroff@38 { + compatible = "fsl,sec-v4.0-poweroff"; + reg = <0x38 0x4>; + status = "disabled"; + }; }; epit1: epit@020d0000 { /* EPIT1 */ diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts index 3f9e041c0252..fda4932faefd 100644 --- a/arch/arm/boot/dts/imx6sl-evk.dts +++ b/arch/arm/boot/dts/imx6sl-evk.dts @@ -20,6 +20,13 @@ reg = <0x80000000 0x40000000>; }; + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -74,6 +81,14 @@ regulator-max-microvolt = <4325000>; regulator-boot-on; }; + + reg_lcd_3v3: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "lcd-3v3"; + gpio = <&gpio4 3 0>; + enable-active-high; + }; }; sound { @@ -329,12 +344,6 @@ >; }; - pinctrl_led: ledgrp { - fsl,pins = < - MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x17059 - >; - }; - pinctrl_kpp: kppgrp { fsl,pins = < MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010 @@ -346,6 +355,51 @@ >; }; + pinctrl_lcd: lcdgrp { + fsl,pins = < + MX6SL_PAD_LCD_DAT0__LCD_DATA00 0x1b0b0 + MX6SL_PAD_LCD_DAT1__LCD_DATA01 0x1b0b0 + MX6SL_PAD_LCD_DAT2__LCD_DATA02 0x1b0b0 + MX6SL_PAD_LCD_DAT3__LCD_DATA03 0x1b0b0 + MX6SL_PAD_LCD_DAT4__LCD_DATA04 0x1b0b0 + MX6SL_PAD_LCD_DAT5__LCD_DATA05 0x1b0b0 + MX6SL_PAD_LCD_DAT6__LCD_DATA06 0x1b0b0 + MX6SL_PAD_LCD_DAT7__LCD_DATA07 0x1b0b0 + MX6SL_PAD_LCD_DAT8__LCD_DATA08 0x1b0b0 + MX6SL_PAD_LCD_DAT9__LCD_DATA09 0x1b0b0 + MX6SL_PAD_LCD_DAT10__LCD_DATA10 0x1b0b0 + MX6SL_PAD_LCD_DAT11__LCD_DATA11 0x1b0b0 + MX6SL_PAD_LCD_DAT12__LCD_DATA12 0x1b0b0 + MX6SL_PAD_LCD_DAT13__LCD_DATA13 0x1b0b0 + MX6SL_PAD_LCD_DAT14__LCD_DATA14 0x1b0b0 + MX6SL_PAD_LCD_DAT15__LCD_DATA15 0x1b0b0 + MX6SL_PAD_LCD_DAT16__LCD_DATA16 0x1b0b0 + MX6SL_PAD_LCD_DAT17__LCD_DATA17 0x1b0b0 + MX6SL_PAD_LCD_DAT18__LCD_DATA18 0x1b0b0 + MX6SL_PAD_LCD_DAT19__LCD_DATA19 0x1b0b0 + MX6SL_PAD_LCD_DAT20__LCD_DATA20 0x1b0b0 + MX6SL_PAD_LCD_DAT21__LCD_DATA21 0x1b0b0 + MX6SL_PAD_LCD_DAT22__LCD_DATA22 0x1b0b0 + MX6SL_PAD_LCD_DAT23__LCD_DATA23 0x1b0b0 + MX6SL_PAD_LCD_CLK__LCD_CLK 0x1b0b0 + MX6SL_PAD_LCD_ENABLE__LCD_ENABLE 0x1b0b0 + MX6SL_PAD_LCD_HSYNC__LCD_HSYNC 0x1b0b0 + MX6SL_PAD_LCD_VSYNC__LCD_VSYNC 0x1b0b0 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x17059 + >; + }; + + pinctrl_pwm1: pwmgrp { + fsl,pins = < + MX6SL_PAD_PWM1__PWM1_OUT 0x110b0 + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1 @@ -488,6 +542,48 @@ status = "okay"; }; +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd>; + lcd-supply = <®_lcd_3v3>; + display = <&display0>; + status = "okay"; + + display0: display0 { + bits-per-pixel = <32>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + &ssi2 { status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index c75800ca8b35..36ab8e054cee 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -226,11 +226,14 @@ }; ssi1: ssi@02028000 { + #sound-dai-cells = <0>; compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; reg = <0x02028000 0x4000>; interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_SSI1>; + clocks = <&clks IMX6SL_CLK_SSI1_IPG>, + <&clks IMX6SL_CLK_SSI1>; + clock-names = "ipg", "baud"; dmas = <&sdma 37 1 0>, <&sdma 38 1 0>; dma-names = "rx", "tx"; @@ -239,11 +242,14 @@ }; ssi2: ssi@0202c000 { + #sound-dai-cells = <0>; compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; reg = <0x0202c000 0x4000>; interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_SSI2>; + clocks = <&clks IMX6SL_CLK_SSI2_IPG>, + <&clks IMX6SL_CLK_SSI2>; + clock-names = "ipg", "baud"; dmas = <&sdma 41 1 0>, <&sdma 42 1 0>; dma-names = "rx", "tx"; @@ -252,11 +258,14 @@ }; ssi3: ssi@02030000 { + #sound-dai-cells = <0>; compatible = "fsl,imx6sl-ssi", "fsl,imx51-ssi"; reg = <0x02030000 0x4000>; interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6SL_CLK_SSI3>; + clocks = <&clks IMX6SL_CLK_SSI3_IPG>, + <&clks IMX6SL_CLK_SSI3>; + clock-names = "ipg", "baud"; dmas = <&sdma 45 1 0>, <&sdma 46 1 0>; dma-names = "rx", "tx"; @@ -529,6 +538,14 @@ }; }; + tempmon: tempmon { + compatible = "fsl,imx6q-tempmon"; + interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; + fsl,tempmon = <&anatop>; + fsl,tempmon-data = <&ocotp>; + clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>; + }; + usbphy1: usbphy@020c9000 { compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; reg = <0x020c9000 0x1000>; @@ -557,6 +574,12 @@ interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, <0 20 IRQ_TYPE_LEVEL_HIGH>; }; + + snvs_poweroff: snvs-poweroff@38 { + compatible = "fsl,sec-v4.0-poweroff"; + reg = <0x38 0x4>; + status = "disabled"; + }; }; epit1: epit@020d0000 { @@ -627,8 +650,14 @@ }; lcdif: lcdif@020f8000 { + compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif"; reg = <0x020f8000 0x4000>; interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6SL_CLK_LCDIF_PIX>, + <&clks IMX6SL_CLK_LCDIF_AXI>, + <&clks IMX6SL_CLK_DUMMY>; + clock-names = "pix", "axi", "disp_axi"; + status = "disabled"; }; dcp: dcp@020fc000 { @@ -784,7 +813,7 @@ }; ocotp: ocotp@021bc000 { - compatible = "fsl,imx6sl-ocotp"; + compatible = "fsl,imx6sl-ocotp", "syscon"; reg = <0x021bc000 0x4000>; }; diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts index a3980d970590..1e6e5cc1c14c 100644 --- a/arch/arm/boot/dts/imx6sx-sdb.dts +++ b/arch/arm/boot/dts/imx6sx-sdb.dts @@ -24,6 +24,13 @@ reg = <0x80000000 0x40000000>; }; + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -90,6 +97,38 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; + + reg_lcd_3v3: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "lcd-3v3"; + gpio = <&gpio3 27 0>; + enable-active-high; + }; + + reg_peri_3v3: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_peri_3v3>; + regulator-name = "peri_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_enet_3v3: regulator@6 { + compatible = "regulator-fixed"; + reg = <6>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_3v3>; + regulator-name = "enet_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpios = <&gpio2 6 GPIO_ACTIVE_LOW>; + }; }; sound { @@ -118,6 +157,14 @@ &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1>; + phy-supply = <®_enet_3v3>; + phy-mode = "rgmii"; + status = "okay"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; phy-mode = "rgmii"; status = "okay"; }; @@ -251,6 +298,48 @@ }; }; +&lcdif1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd>; + lcd-supply = <®_lcd_3v3>; + display = <&display0>; + status = "okay"; + + display0: display0 { + bits-per-pixel = <16>; + bus-width = <24>; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <33500000>; + hactive = <800>; + vactive = <480>; + hback-porch = <89>; + hfront-porch = <164>; + vback-porch = <23>; + vfront-porch = <10>; + hsync-len = <10>; + vsync-len = <10>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + &ssi2 { status = "okay"; }; @@ -341,6 +430,30 @@ MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081 MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081 + MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91 + >; + }; + + pinctrl_enet_3v3: enet3v3grp { + fsl,pins = < + MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x80000000 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9 + MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1 + MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1 + MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1 + MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1 + MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1 + MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081 + MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081 + MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081 + MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081 + MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081 + MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081 >; }; @@ -365,6 +478,52 @@ >; }; + pinctrl_lcd: lcdgrp { + fsl,pins = < + MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0 + MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0 + MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0 + MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0 + MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0 + MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0 + MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0 + MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0 + MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0 + MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0 + MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0 + MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0 + MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0 + MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0 + MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0 + MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0 + MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0 + MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0 + MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0 + MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0 + MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0 + MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0 + MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0 + MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0 + MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0 + MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0 + MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0 + MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0 + >; + }; + + pinctrl_peri_3v3: peri3v3grp { + fsl,pins = < + MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000 + >; + }; + + pinctrl_pwm3: pwm3grp-1 { + fsl,pins = < + MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0 + >; + }; + pinctrl_vcc_sd3: vccsd3grp { fsl,pins = < MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059 diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index f4b9da65bc0f..7a24fee1e7ae 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -298,6 +298,7 @@ }; ssi1: ssi@02028000 { + #sound-dai-cells = <0>; compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; reg = <0x02028000 0x4000>; interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; @@ -311,6 +312,7 @@ }; ssi2: ssi@0202c000 { + #sound-dai-cells = <0>; compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; reg = <0x0202c000 0x4000>; interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; @@ -324,6 +326,7 @@ }; ssi3: ssi@02030000 { + #sound-dai-cells = <0>; compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi"; reg = <0x02030000 0x4000>; interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; @@ -418,7 +421,7 @@ reg = <0x02098000 0x4000>; interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SX_CLK_GPT_BUS>, - <&clks IMX6SX_CLK_GPT_SERIAL>; + <&clks IMX6SX_CLK_GPT_3M>; clock-names = "ipg", "per"; }; @@ -668,6 +671,12 @@ reg = <0x34 0x58>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; }; + + snvs_poweroff: snvs-poweroff@38 { + compatible = "fsl,sec-v4.0-poweroff"; + reg = <0x38 0x4>; + status = "disabled"; + }; }; epit1: epit@020d0000 { @@ -776,6 +785,8 @@ <&clks IMX6SX_CLK_ENET_PTP>; clock-names = "ipg", "ahb", "ptp", "enet_clk_ref", "enet_out"; + fsl,num-tx-queues=<3>; + fsl,num-rx-queues=<3>; status = "disabled"; }; @@ -872,7 +883,7 @@ }; fec2: ethernet@021b4000 { - compatible = "fsl,imx6sx-fec"; + compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec"; reg = <0x021b4000 0x4000>; interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; @@ -1062,6 +1073,7 @@ }; lcdif1: lcdif@02220000 { + compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; reg = <0x02220000 0x4000>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>, @@ -1072,6 +1084,7 @@ }; lcdif2: lcdif@02224000 { + compatible = "fsl,imx6sx-lcdif", "fsl,imx28-lcdif"; reg = <0x02224000 0x4000>; interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>, diff --git a/arch/arm/boot/dts/integrator.dtsi b/arch/arm/boot/dts/integrator.dtsi index 88e3d477bf16..28e38f8c6b0f 100644 --- a/arch/arm/boot/dts/integrator.dtsi +++ b/arch/arm/boot/dts/integrator.dtsi @@ -6,8 +6,18 @@ / { core-module@10000000 { - compatible = "arm,core-module-integrator"; + compatible = "arm,core-module-integrator", "syscon"; reg = <0x10000000 0x200>; + + /* Use core module LED to indicate CPU load */ + led@0c.0 { + compatible = "register-bit-led"; + offset = <0x0c>; + mask = <0x01>; + label = "integrator:core_module"; + linux,default-trigger = "cpu0"; + default-state = "on"; + }; }; ebi@12000000 { @@ -82,5 +92,41 @@ reg = <0x19000000 0x1000>; interrupts = <4>; }; + + syscon { + /* Debug registers mapped as syscon */ + compatible = "syscon"; + reg = <0x1a000000 0x10>; + + led@04.0 { + compatible = "register-bit-led"; + offset = <0x04>; + mask = <0x01>; + label = "integrator:green0"; + linux,default-trigger = "heartbeat"; + default-state = "on"; + }; + led@04.1 { + compatible = "register-bit-led"; + offset = <0x04>; + mask = <0x02>; + label = "integrator:yellow"; + default-state = "off"; + }; + led@04.2 { + compatible = "register-bit-led"; + offset = <0x04>; + mask = <0x04>; + label = "integrator:red"; + default-state = "off"; + }; + led@04.3 { + compatible = "register-bit-led"; + offset = <0x04>; + mask = <0x08>; + label = "integrator:green1"; + default-state = "off"; + }; + }; }; }; diff --git a/arch/arm/boot/dts/k2e-evm.dts b/arch/arm/boot/dts/k2e-evm.dts index c568f067604d..560d62150ade 100644 --- a/arch/arm/boot/dts/k2e-evm.dts +++ b/arch/arm/boot/dts/k2e-evm.dts @@ -139,3 +139,15 @@ }; }; }; + +&mdio { + ethphy0: ethernet-phy@0 { + compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; diff --git a/arch/arm/boot/dts/k2e.dtsi b/arch/arm/boot/dts/k2e.dtsi index 03d01909525b..5fc14683d6df 100644 --- a/arch/arm/boot/dts/k2e.dtsi +++ b/arch/arm/boot/dts/k2e.dtsi @@ -67,6 +67,8 @@ clock-names = "usb"; interrupts = <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>; ranges; + dma-coherent; + dma-ranges; status = "disabled"; dwc3@25010000 { @@ -76,5 +78,61 @@ usb-phy = <&usb1_phy>, <&usb1_phy>; }; }; + + dspgpio0: keystone_dsp_gpio@02620240 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x240>; + }; + + pcie@21020000 { + compatible = "ti,keystone-pcie","snps,dw-pcie"; + clocks = <&clkpcie1>; + clock-names = "pcie"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>; + ranges = <0x81000000 0 0 0x23260000 0x4000 0x4000 + 0x82000000 0 0x60000000 0x60000000 0 0x10000000>; + + device_type = "pci"; + num-lanes = <2>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc1 0>, /* INT A */ + <0 0 0 2 &pcie_intc1 1>, /* INT B */ + <0 0 0 3 &pcie_intc1 2>, /* INT C */ + <0 0 0 4 &pcie_intc1 3>; /* INT D */ + + pcie_msi_intc1: msi-interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 379 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 380 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 381 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 382 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 383 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 384 IRQ_TYPE_EDGE_RISING>; + }; + + pcie_intc1: legacy-interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>; + }; + }; }; }; + +&mdio { + reg = <0x24200f00 0x100>; +}; diff --git a/arch/arm/boot/dts/k2hk.dtsi b/arch/arm/boot/dts/k2hk.dtsi index c73899c73118..d721f4b737f7 100644 --- a/arch/arm/boot/dts/k2hk.dtsi +++ b/arch/arm/boot/dts/k2hk.dtsi @@ -42,5 +42,61 @@ soc { /include/ "k2hk-clocks.dtsi" + + dspgpio0: keystone_dsp_gpio@02620240 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x240>; + }; + + dspgpio1: keystone_dsp_gpio@2620244 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x244>; + }; + + dspgpio2: keystone_dsp_gpio@2620248 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x248>; + }; + + dspgpio3: keystone_dsp_gpio@262024c { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x24c>; + }; + + dspgpio4: keystone_dsp_gpio@2620250 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x250>; + }; + + dspgpio5: keystone_dsp_gpio@2620254 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x254>; + }; + + dspgpio6: keystone_dsp_gpio@2620258 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x258>; + }; + + dspgpio7: keystone_dsp_gpio@262025c { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x25c>; + }; }; }; diff --git a/arch/arm/boot/dts/k2l-evm.dts b/arch/arm/boot/dts/k2l-evm.dts index fec43128a2e0..85cc7f2872d7 100644 --- a/arch/arm/boot/dts/k2l-evm.dts +++ b/arch/arm/boot/dts/k2l-evm.dts @@ -116,3 +116,15 @@ }; }; }; + +&mdio { + ethphy0: ethernet-phy@0 { + compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + + ethphy1: ethernet-phy@1 { + compatible = "marvell,88E1514", "marvell,88E1510", "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; diff --git a/arch/arm/boot/dts/k2l.dtsi b/arch/arm/boot/dts/k2l.dtsi index 1f7f479589e1..e32c3baa77b8 100644 --- a/arch/arm/boot/dts/k2l.dtsi +++ b/arch/arm/boot/dts/k2l.dtsi @@ -51,5 +51,51 @@ clocks = <&clkuart3>; interrupts = <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>; }; + + dspgpio0: keystone_dsp_gpio@02620240 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x240>; + }; + + dspgpio1: keystone_dsp_gpio@2620244 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x244>; + }; + + dspgpio2: keystone_dsp_gpio@2620248 { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x248>; + }; + + dspgpio3: keystone_dsp_gpio@262024c { + compatible = "ti,keystone-dsp-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio,syscon-dev = <&devctrl 0x24c>; + }; }; }; + +&spi0 { + ti,davinci-spi-num-cs = <5>; +}; + +&spi1 { + ti,davinci-spi-num-cs = <3>; +}; + +&spi2 { + ti,davinci-spi-num-cs = <5>; + /* Pin muxed. Enabled and configured by Bootloader */ + status = "disabled"; +}; + +&mdio { + reg = <0x26200f00 0x100>; +}; diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi index 9e31fe7d31f8..c06542b2c954 100644 --- a/arch/arm/boot/dts/keystone.dtsi +++ b/arch/arm/boot/dts/keystone.dtsi @@ -172,7 +172,7 @@ compatible = "ti,keystone-usbphy"; #address-cells = <1>; #size-cells = <1>; - reg = <0x2620738 32>; + reg = <0x2620738 24>; status = "disabled"; }; @@ -277,5 +277,58 @@ clock-names = "fck"; bus_freq = <2500000>; }; + + kirq0: keystone_irq@26202a0 { + compatible = "ti,keystone-irq"; + interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>; + interrupt-controller; + #interrupt-cells = <1>; + ti,syscon-dev = <&devctrl 0x2a0>; + }; + + pcie@21800000 { + compatible = "ti,keystone-pcie", "snps,dw-pcie"; + clocks = <&clkpcie>; + clock-names = "pcie"; + #address-cells = <3>; + #size-cells = <2>; + reg = <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>; + ranges = <0x81000000 0 0 0x23250000 0 0x4000 + 0x82000000 0 0x50000000 0x50000000 0 0x10000000>; + + device_type = "pci"; + num-lanes = <2>; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */ + <0 0 0 2 &pcie_intc0 1>, /* INT B */ + <0 0 0 3 &pcie_intc0 2>, /* INT C */ + <0 0 0 4 &pcie_intc0 3>; /* INT D */ + + pcie_msi_intc0: msi-interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>; + }; + + pcie_intc0: legacy-interrupt-controller { + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>; + }; + }; }; }; diff --git a/arch/arm/boot/dts/kirkwood-dir665.dts b/arch/arm/boot/dts/kirkwood-dir665.dts new file mode 100644 index 000000000000..786959ee9cbe --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-dir665.dts @@ -0,0 +1,278 @@ +/* + * Copyright (C) 2014 Claudio Leite <leitec@staticky.com> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +/dts-v1/; + +#include "kirkwood.dtsi" +#include "kirkwood-6281.dtsi" + +/ { + model = "D-Link DIR-665"; + compatible = "dlink,dir-665", "marvell,kirkwood-88f6281", "marvell,kirkwood"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x8000000>; /* 128 MB */ + }; + + chosen { + bootargs = "console=ttyS0,115200n8 earlyprintk"; + stdout-path = &uart0; + }; + + mbus { + pcie-controller { + status = "okay"; + + pcie@1,0 { + status = "okay"; + }; + }; + }; + + ocp@f1000000 { + pinctrl: pin-controller@10000 { + pinctrl-0 =< &pmx_led_usb + &pmx_led_internet_blue + &pmx_led_internet_amber + &pmx_led_5g &pmx_led_status_blue + &pmx_led_wps &pmx_led_status_amber + &pmx_led_24g + &pmx_btn_restart &pmx_btn_wps>; + pinctrl-names = "default"; + + pmx_led_usb: pmx-led-usb { + marvell,pins = "mpp12"; + marvell,function = "gpio"; + }; + pmx_led_internet_blue: pmx-led-internet-blue { + marvell,pins = "mpp42"; + marvell,function = "gpio"; + }; + pmx_led_internet_amber: pmx-led-internet-amber { + marvell,pins = "mpp43"; + marvell,function = "gpio"; + }; + pmx_led_5g: pmx-led-5g { + marvell,pins = "mpp44"; + marvell,function = "gpio"; + }; + pmx_led_status_blue: pmx-led-status-blue { + marvell,pins = "mpp45"; + marvell,function = "gpio"; + }; + pmx_led_wps: pmx-led-wps { + marvell,pins = "mpp47"; + marvell,function = "gpio"; + }; + pmx_led_status_amber: pmx-led-status-amber { + marvell,pins = "mpp48"; + marvell,function = "gpio"; + }; + pmx_led_24g: pmx-led-24g { + marvell,pins = "mpp49"; + marvell,function = "gpio"; + }; + pmx_btn_restart: pmx-btn-restart { + marvell,pins = "mpp28"; + marvell,function = "gpio"; + }; + pmx_btn_wps: pmx-btn-wps { + marvell,pins = "mpp46"; + marvell,function = "gpio"; + }; + }; + + spi@10600 { + status = "okay"; + m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "mxicy,mx25l12805d"; + spi-max-frequency = <50000000>; + reg = <0>; + + partition@0 { + label = "uboot"; + reg = <0x0 0x30000>; + read-only; + }; + + partition@30000 { + label = "nvram"; + reg = <0x30000 0x10000>; + read-only; + }; + + partition@40000 { + label = "kernel"; + reg = <0x40000 0x180000>; + }; + + partition@1c0000 { + label = "rootfs"; + reg = <0x1c0000 0xe00000>; + }; + + cal_data: partition@fc0000 { + label = "cal_data"; + reg = <0xfc0000 0x10000>; + read-only; + }; + + partition@fd0000 { + label = "lang_pack"; + reg = <0xfd0000 0x30000>; + read-only; + }; + }; + }; + + serial@12000 { + status = "okay"; + }; + + i2c@11000 { + status = "okay"; + }; + + ehci@50000 { + status = "okay"; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + blue-usb { + label = "dir665:blue:usb"; + gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; + }; + blue-internet { + /* Can only be turned on if the Internet + * Ethernet port has Link + */ + label = "dir665:blue:internet"; + gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + }; + amber-internet { + label = "dir665:amber:internet"; + gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; + }; + blue-wifi5g { + label = "dir665:blue:5g"; + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + }; + blue-status { + label = "dir665:blue:status"; + gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; + }; + blue-wps { + label = "dir665:blue:wps"; + gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; + }; + amber-status { + label = "dir665:amber:status"; + gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; + }; + blue-24g { + label = "dir665:blue:24g"; + gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + + reset { + label = "reset"; + linux,code = <KEY_RESTART>; + gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; + }; + wps { + label = "wps"; + linux,code = <KEY_WPS_BUTTON>; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + }; + }; + + dsa@0 { + compatible = "marvell,dsa"; + #address-cells = <2>; + #size-cells = <0>; + + dsa,ethernet = <ð0port>; + dsa,mii-bus = <&mdio>; + + switch@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0>; /* MDIO address 0, switch 0 in tree */ + + port@0 { + reg = <0>; + label = "lan4"; + }; + + port@1 { + reg = <1>; + label = "lan3"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan1"; + }; + + port@4 { + reg = <4>; + label = "wan"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + }; + }; + }; +}; + +&mdio { + status = "okay"; +}; + +/* eth0 is connected to a Marvell 88E6171 switch, without a PHY. So set + * fixed speed and duplex. */ +ð0 { + status = "okay"; + + ethernet0-port@0 { + speed = <1000>; + duplex = <1>; + }; +}; + +/* eth1 is connected to the switch as well. However DSA only supports a + * single CPU port. So leave this port disabled to avoid confusion. */ + +ð1 { + status = "disabled"; +}; + +/* There is no battery on the boards, so the RTC does not keep time + * when there is no power, making it useless. */ +&rtc { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts index 8f76d28759a3..f82827d6fcff 100644 --- a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts +++ b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts @@ -123,11 +123,11 @@ dsa@0 { compatible = "marvell,dsa"; - #address-cells = <2>; + #address-cells = <1>; #size-cells = <0>; - dsa,ethernet = <ð0>; - dsa,mii-bus = <ðphy0>; + dsa,ethernet = <ð0port>; + dsa,mii-bus = <&mdio>; switch@0 { #address-cells = <1>; @@ -169,17 +169,13 @@ &mdio { status = "okay"; - - ethphy0: ethernet-phy@ff { - reg = <0xff>; /* No phy attached */ - speed = <1000>; - duplex = <1>; - }; }; ð0 { status = "okay"; + ethernet0-port@0 { - phy-handle = <ðphy0>; + speed = <1000>; + duplex = <1>; }; }; diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281-a.dts b/arch/arm/boot/dts/kirkwood-rd88f6281-a.dts new file mode 100644 index 000000000000..f2e08b3b33ea --- /dev/null +++ b/arch/arm/boot/dts/kirkwood-rd88f6281-a.dts @@ -0,0 +1,43 @@ +/* + * Marvell RD88F6181 A Board descrition + * + * Andrew Lunn <andrew@lunn.ch> + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + * + * This file contains the definitions for the board with the A0 or + * higher stepping of the SoC. The ethernet switch does not have a + * "wan" port. + */ + +/dts-v1/; +#include "kirkwood-rd88f6281.dtsi" + +/ { + model = "Marvell RD88f6281 Reference design, with A0 or higher SoC"; + compatible = "marvell,rd88f6281-a", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood"; + + dsa@0 { + switch@0 { + reg = <10 0>; /* MDIO address 10, switch 0 in tree */ + }; + }; +}; + +&mdio { + status = "okay"; + + ethphy1: ethernet-phy@11 { + reg = <11>; + }; +}; + +ð1 { + status = "okay"; + + ethernet1-port@0 { + phy-handle = <ðphy1>; + }; +}; diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281-a0.dts b/arch/arm/boot/dts/kirkwood-rd88f6281-a0.dts deleted file mode 100644 index a803bbb70bc8..000000000000 --- a/arch/arm/boot/dts/kirkwood-rd88f6281-a0.dts +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Marvell RD88F6181 A0 Board descrition - * - * Andrew Lunn <andrew@lunn.ch> - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - * - * This file contains the definitions for the board with the A0 variant of - * the SoC. The ethernet switch does not have a "wan" port. - */ - -/dts-v1/; -#include "kirkwood-rd88f6281.dtsi" - -/ { - model = "Marvell RD88f6281 Reference design, with A0 SoC"; - compatible = "marvell,rd88f6281-a0", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood"; - - dsa@0 { - switch@0 { - reg = <10 0>; /* MDIO address 10, switch 0 in tree */ - }; - }; -};
\ No newline at end of file diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281-a1.dts b/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts index baeebbf1d8c7..f4272b64ed7f 100644 --- a/arch/arm/boot/dts/kirkwood-rd88f6281-a1.dts +++ b/arch/arm/boot/dts/kirkwood-rd88f6281-z0.dts @@ -1,5 +1,5 @@ /* - * Marvell RD88F6181 A1 Board descrition + * Marvell RD88F6181 Z0 stepping descrition * * Andrew Lunn <andrew@lunn.ch> * @@ -7,17 +7,17 @@ * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. * - * This file contains the definitions for the board with the A1 variant of - * the SoC. The ethernet switch has a "wan" port. - */ + * This file contains the definitions for the board using the Z0 + * stepping of the SoC. The ethernet switch has a "wan" port. +*/ /dts-v1/; #include "kirkwood-rd88f6281.dtsi" / { - model = "Marvell RD88f6281 Reference design, with A1 SoC"; - compatible = "marvell,rd88f6281-a1", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood"; + model = "Marvell RD88f6281 Reference design, with Z0 SoC"; + compatible = "marvell,rd88f6281-z0", "marvell,rd88f6281","marvell,kirkwood-88f6281", "marvell,kirkwood"; dsa@0 { switch@0 { @@ -28,4 +28,8 @@ }; }; }; -};
\ No newline at end of file +}; + +ð1 { + status = "disabled"; +}; diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi index 26cf0e0ccefd..d195e884b3b5 100644 --- a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi +++ b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi @@ -37,7 +37,6 @@ ocp@f1000000 { pinctrl: pin-controller@10000 { - pinctrl-0 = <&pmx_sdio_cd>; pinctrl-names = "default"; pmx_sdio_cd: pmx-sdio-cd { @@ -69,8 +68,8 @@ #address-cells = <2>; #size-cells = <0>; - dsa,ethernet = <ð0>; - dsa,mii-bus = <ðphy1>; + dsa,ethernet = <ð0port>; + dsa,mii-bus = <&mdio>; switch@0 { #address-cells = <1>; @@ -119,35 +118,19 @@ }; partition@300000 { - label = "data"; + label = "rootfs"; reg = <0x0300000 0x500000>; }; }; &mdio { status = "okay"; - - ethphy0: ethernet-phy@0 { - reg = <0>; - }; - - ethphy1: ethernet-phy@ff { - reg = <0xff>; /* No PHY attached */ - speed = <1000>; - duple = <1>; - }; }; ð0 { status = "okay"; ethernet0-port@0 { - phy-handle = <ðphy0>; - }; -}; - -ð1 { - status = "okay"; - ethernet1-port@0 { - phy-handle = <ðphy1>; + speed = <1000>; + duplex = <1>; }; }; diff --git a/arch/arm/boot/dts/kirkwood-synology.dtsi b/arch/arm/boot/dts/kirkwood-synology.dtsi index 811e0971fc58..8be5b2e4626e 100644 --- a/arch/arm/boot/dts/kirkwood-synology.dtsi +++ b/arch/arm/boot/dts/kirkwood-synology.dtsi @@ -266,7 +266,7 @@ s35390a: s35390a@30 { status = "disabled"; - compatible = "ssi,s35390a"; + compatible = "sii,s35390a"; reg = <0x30>; }; }; diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi index afc640cd80c5..464f09a1a4a5 100644 --- a/arch/arm/boot/dts/kirkwood.dtsi +++ b/arch/arm/boot/dts/kirkwood.dtsi @@ -309,7 +309,7 @@ marvell,tx-checksum-limit = <1600>; status = "disabled"; - ethernet0-port@0 { + eth0port: ethernet0-port@0 { compatible = "marvell,kirkwood-eth-port"; reg = <0>; interrupts = <11>; @@ -342,7 +342,7 @@ pinctrl-names = "default"; status = "disabled"; - ethernet1-port@0 { + eth1port: ethernet1-port@0 { compatible = "marvell,kirkwood-eth-port"; reg = <0>; interrupts = <15>; diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts new file mode 100644 index 000000000000..9c5e16ba8c95 --- /dev/null +++ b/arch/arm/boot/dts/ls1021a-qds.dts @@ -0,0 +1,240 @@ +/* + * Copyright 2013-2014 Freescale Semiconductor, Inc. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "ls1021a.dtsi" + +/ { + model = "LS1021A QDS Board"; + + aliases { + enet0_rgmii_phy = &rgmii_phy1; + enet1_rgmii_phy = &rgmii_phy2; + enet2_rgmii_phy = &rgmii_phy3; + enet0_sgmii_phy = &sgmii_phy1c; + enet1_sgmii_phy = &sgmii_phy1d; + }; +}; + +&dspi0 { + bus-num = <0>; + status = "okay"; + + dspiflash: at45db021d@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at45db021d", "atmel,at45", "atmel,dataflash"; + spi-max-frequency = <16000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; +}; + +&i2c0 { + status = "okay"; + + pca9547: mux@77 { + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + + ds3232: rtc@68 { + compatible = "dallas,ds3232"; + reg = <0x68>; + interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + + ina220@40 { + compatible = "ti,ina220"; + reg = <0x40>; + shunt-resistor = <1000>; + }; + + ina220@41 { + compatible = "ti,ina220"; + reg = <0x41>; + shunt-resistor = <1000>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + eeprom@56 { + compatible = "atmel,24c512"; + reg = <0x56>; + }; + + eeprom@57 { + compatible = "atmel,24c512"; + reg = <0x57>; + }; + + adt7461a@4c { + compatible = "adi,adt7461a"; + reg = <0x4c>; + }; + }; + }; +}; + +&ifc { + #address-cells = <2>; + #size-cells = <1>; + /* NOR, NAND Flashes and FPGA on board */ + ranges = <0x0 0x0 0x0 0x60000000 0x08000000 + 0x2 0x0 0x0 0x7e800000 0x00010000 + 0x3 0x0 0x0 0x7fb00000 0x00000100>; + status = "okay"; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x8000000>; + bank-width = <2>; + device-width = <1>; + }; + + fpga: board-control@3,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + reg = <0x3 0x0 0x0000100>; + bank-width = <1>; + device-width = <1>; + ranges = <0 3 0 0x100>; + + mdio-mux-emi1 { + compatible = "mdio-mux-mmioreg"; + mdio-parent-bus = <&mdio0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x54 1>; /* BRDCFG4 */ + mux-mask = <0xe0>; /* EMI1[2:0] */ + + /* Onboard PHYs */ + ls1021amdio0: mdio@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + rgmii_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + }; + + ls1021amdio1: mdio@20 { + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + rgmii_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + }; + + ls1021amdio2: mdio@40 { + reg = <0x40>; + #address-cells = <1>; + #size-cells = <0>; + rgmii_phy3: ethernet-phy@3 { + reg = <0x3>; + }; + }; + + ls1021amdio3: mdio@60 { + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + sgmii_phy1c: ethernet-phy@1c { + reg = <0x1c>; + }; + }; + + ls1021amdio4: mdio@80 { + reg = <0x80>; + #address-cells = <1>; + #size-cells = <0>; + sgmii_phy1d: ethernet-phy@1d { + reg = <0x1d>; + }; + }; + }; + }; +}; + +&lpuart0 { + status = "okay"; +}; + +&mdio0 { + tbi0: tbi-phy@8 { + reg = <0x8>; + device_type = "tbi-phy"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts new file mode 100644 index 000000000000..a2c591e2d918 --- /dev/null +++ b/arch/arm/boot/dts/ls1021a-twr.dts @@ -0,0 +1,127 @@ +/* + * Copyright 2013-2014 Freescale Semiconductor, Inc. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "ls1021a.dtsi" + +/ { + model = "LS1021A TWR Board"; + + aliases { + enet2_rgmii_phy = &rgmii_phy1; + enet0_sgmii_phy = &sgmii_phy2; + enet1_sgmii_phy = &sgmii_phy0; + }; +}; + +&dspi1 { + bus-num = <0>; + status = "okay"; + + dspiflash: s25fl064k@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spansion,s25fl064k"; + spi-max-frequency = <16000000>; + spi-cpol; + spi-cpha; + reg = <0>; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&ifc { + #address-cells = <2>; + #size-cells = <1>; + /* NOR Flash on board */ + ranges = <0x0 0x0 0x0 0x60000000 0x08000000>; + status = "okay"; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x8000000>; + bank-width = <2>; + device-width = <1>; + }; +}; + +&lpuart0 { + status = "okay"; +}; + +&mdio0 { + sgmii_phy0: ethernet-phy@0 { + reg = <0x0>; + }; + rgmii_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + sgmii_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + tbi1: tbi-phy@1f { + reg = <0x1f>; + device_type = "tbi-phy"; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi new file mode 100644 index 000000000000..657da14cb4b5 --- /dev/null +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -0,0 +1,408 @@ +/* + * Copyright 2013-2014 Freescale Semiconductor, Inc. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "skeleton64.dtsi" +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + compatible = "fsl,ls1021a"; + interrupt-parent = <&gic>; + + aliases { + serial0 = &lpuart0; + serial1 = &lpuart1; + serial2 = &lpuart2; + serial3 = &lpuart3; + serial4 = &lpuart4; + serial5 = &lpuart5; + sysclk = &sysclk; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@f00 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0xf00>; + clocks = <&cluster1_clk>; + }; + + cpu@f01 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0xf01>; + clocks = <&cluster1_clk>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + device_type = "soc"; + interrupt-parent = <&gic>; + ranges; + + gic: interrupt-controller@1400000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x1401000 0x0 0x1000>, + <0x0 0x1402000 0x0 0x1000>, + <0x0 0x1404000 0x0 0x2000>, + <0x0 0x1406000 0x0 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; + + }; + + ifc: ifc@1530000 { + compatible = "fsl,ifc", "simple-bus"; + reg = <0x0 0x1530000 0x0 0x10000>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + }; + + dcfg: dcfg@1ee0000 { + compatible = "fsl,ls1021a-dcfg", "syscon"; + reg = <0x0 0x1ee0000 0x0 0x10000>; + big-endian; + }; + + esdhc: esdhc@1560000 { + compatible = "fsl,esdhc"; + reg = <0x0 0x1560000 0x0 0x10000>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <0>; + voltage-ranges = <1800 1800 3300 3300>; + sdhci,auto-cmd12; + big-endian; + bus-width = <4>; + status = "disabled"; + }; + + scfg: scfg@1570000 { + compatible = "fsl,ls1021a-scfg", "syscon"; + reg = <0x0 0x1570000 0x0 0x10000>; + }; + + clockgen: clocking@1ee1000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x1ee1000 0x10000>; + + sysclk: sysclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-output-names = "sysclk"; + }; + + cga_pll1: pll@800 { + compatible = "fsl,qoriq-core-pll-2.0"; + #clock-cells = <1>; + reg = <0x800 0x10>; + clocks = <&sysclk>; + clock-output-names = "cga-pll1", "cga-pll1-div2", + "cga-pll1-div4"; + }; + + platform_clk: pll@c00 { + compatible = "fsl,qoriq-core-pll-2.0"; + #clock-cells = <1>; + reg = <0xc00 0x10>; + clocks = <&sysclk>; + clock-output-names = "platform-clk", "platform-clk-div2"; + }; + + cluster1_clk: clk0c0@0 { + compatible = "fsl,qoriq-core-mux-2.0"; + #clock-cells = <0>; + reg = <0x0 0x10>; + clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4"; + clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>; + clock-output-names = "cluster1-clk"; + }; + }; + + dspi0: dspi@2100000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2100000 0x0 0x10000>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "dspi"; + clocks = <&platform_clk 1>; + spi-num-chipselects = <5>; + big-endian; + status = "disabled"; + }; + + dspi1: dspi@2110000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2110000 0x0 0x10000>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "dspi"; + clocks = <&platform_clk 1>; + spi-num-chipselects = <5>; + big-endian; + status = "disabled"; + }; + + i2c0: i2c@2180000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2180000 0x0 0x10000>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "i2c"; + clocks = <&platform_clk 1>; + status = "disabled"; + }; + + i2c1: i2c@2190000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2190000 0x0 0x10000>; + interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "i2c"; + clocks = <&platform_clk 1>; + status = "disabled"; + }; + + i2c2: i2c@21a0000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x21a0000 0x0 0x10000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "i2c"; + clocks = <&platform_clk 1>; + status = "disabled"; + }; + + uart0: serial@21c0500 { + compatible = "fsl,16550-FIFO64", "ns16550a"; + reg = <0x0 0x21c0500 0x0 0x100>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <0>; + fifo-size = <15>; + status = "disabled"; + }; + + uart1: serial@21c0600 { + compatible = "fsl,16550-FIFO64", "ns16550a"; + reg = <0x0 0x21c0600 0x0 0x100>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <0>; + fifo-size = <15>; + status = "disabled"; + }; + + uart2: serial@21d0500 { + compatible = "fsl,16550-FIFO64", "ns16550a"; + reg = <0x0 0x21d0500 0x0 0x100>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <0>; + fifo-size = <15>; + status = "disabled"; + }; + + uart3: serial@21d0600 { + compatible = "fsl,16550-FIFO64", "ns16550a"; + reg = <0x0 0x21d0600 0x0 0x100>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <0>; + fifo-size = <15>; + status = "disabled"; + }; + + lpuart0: serial@2950000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2950000 0x0 0x1000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysclk>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart1: serial@2960000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2960000 0x0 0x1000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart2: serial@2970000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2970000 0x0 0x1000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart3: serial@2980000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2980000 0x0 0x1000>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart4: serial@2990000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2990000 0x0 0x1000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + lpuart5: serial@29a0000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x29a0000 0x0 0x1000>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "ipg"; + status = "disabled"; + }; + + wdog0: watchdog@2ad0000 { + compatible = "fsl,imx21-wdt"; + reg = <0x0 0x2ad0000 0x0 0x10000>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "wdog-en"; + big-endian; + }; + + sai1: sai@2b50000 { + compatible = "fsl,vf610-sai"; + reg = <0x0 0x2b50000 0x0 0x10000>; + interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "sai"; + dma-names = "tx", "rx"; + dmas = <&edma0 1 47>, + <&edma0 1 46>; + big-endian; + status = "disabled"; + }; + + sai2: sai@2b60000 { + compatible = "fsl,vf610-sai"; + reg = <0x0 0x2b60000 0x0 0x10000>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&platform_clk 1>; + clock-names = "sai"; + dma-names = "tx", "rx"; + dmas = <&edma0 1 45>, + <&edma0 1 44>; + big-endian; + status = "disabled"; + }; + + edma0: edma@2c00000 { + #dma-cells = <2>; + compatible = "fsl,vf610-edma"; + reg = <0x0 0x2c00000 0x0 0x10000>, + <0x0 0x2c10000 0x0 0x10000>, + <0x0 0x2c20000 0x0 0x10000>; + interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma-tx", "edma-err"; + dma-channels = <32>; + big-endian; + clock-names = "dmamux0", "dmamux1"; + clocks = <&platform_clk 1>, + <&platform_clk 1>; + }; + + mdio0: mdio@2d24000 { + compatible = "gianfar"; + device_type = "mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2d24000 0x0 0x4000>; + }; + + usb@8600000 { + compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; + reg = <0x0 0x8600000 0x0 0x1000>; + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "host"; + phy_type = "ulpi"; + }; + + usb3@3100000 { + compatible = "snps,dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "host"; + }; + }; +}; diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi new file mode 100644 index 000000000000..b67ede515bcd --- /dev/null +++ b/arch/arm/boot/dts/meson.dtsi @@ -0,0 +1,154 @@ +/* + * Copyright 2014 Carlo Caione <carlo@caione.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/include/ "skeleton.dtsi" + +/ { + interrupt-parent = <&gic>; + + L2: l2-cache-controller@c4200000 { + compatible = "arm,pl310-cache"; + reg = <0xc4200000 0x1000>; + cache-unified; + cache-level = <2>; + }; + + gic: interrupt-controller@c4301000 { + compatible = "arm,cortex-a9-gic"; + reg = <0xc4301000 0x1000>, + <0xc4300100 0x0100>; + interrupt-controller; + #interrupt-cells = <3>; + }; + + timer@c1109940 { + compatible = "amlogic,meson6-timer"; + reg = <0xc1109940 0x14>; + interrupts = <0 10 1>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + wdt: watchdog@c1109900 { + compatible = "amlogic,meson6-wdt"; + reg = <0xc1109900 0x8>; + }; + + uart_AO: serial@c81004c0 { + compatible = "amlogic,meson-uart"; + reg = <0xc81004c0 0x14>; + interrupts = <0 90 1>; + clocks = <&clk81>; + status = "disabled"; + }; + + uart_A: serial@c81084c0 { + compatible = "amlogic,meson-uart"; + reg = <0xc81084c0 0x14>; + interrupts = <0 90 1>; + clocks = <&clk81>; + status = "disabled"; + }; + + uart_B: serial@c81084dc { + compatible = "amlogic,meson-uart"; + reg = <0xc81084dc 0x14>; + interrupts = <0 90 1>; + clocks = <&clk81>; + status = "disabled"; + }; + + uart_C: serial@c8108700 { + compatible = "amlogic,meson-uart"; + reg = <0xc8108700 0x14>; + interrupts = <0 90 1>; + clocks = <&clk81>; + status = "disabled"; + }; + + i2c_AO: i2c@c8100500 { + compatible = "amlogic,meson6-i2c"; + reg = <0xc8100500 0x20>; + interrupts = <0 92 1>; + clocks = <&clk81>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c_A: i2c@c1108500 { + compatible = "amlogic,meson6-i2c"; + reg = <0xc1108500 0x20>; + interrupts = <0 21 1>; + clocks = <&clk81>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c_B: i2c@c11087c0 { + compatible = "amlogic,meson6-i2c"; + reg = <0xc11087c0 0x20>; + interrupts = <0 128 1>; + clocks = <&clk81>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ir_receiver: ir-receiver@c8100480 { + compatible= "amlogic,meson6-ir"; + reg = <0xc8100480 0x20>; + interrupts = <0 15 1>; + status = "disabled"; + }; + }; +}; /* end of / */ diff --git a/arch/arm/boot/dts/meson6-atv1200.dts b/arch/arm/boot/dts/meson6-atv1200.dts new file mode 100644 index 000000000000..d7d351a68944 --- /dev/null +++ b/arch/arm/boot/dts/meson6-atv1200.dts @@ -0,0 +1,66 @@ +/* + * Copyright 2014 Carlo Caione <carlo@caione.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +/include/ "meson6.dtsi" + +/ { + model = "Geniatech ATV1200"; + compatible = "geniatech,atv1200", "amlogic,meson6"; + + aliases { + serial0 = &uart_AO; + }; + + memory { + reg = <0x40000000 0x80000000>; + }; +}; + +&uart_AO { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi new file mode 100644 index 000000000000..8b33be15af94 --- /dev/null +++ b/arch/arm/boot/dts/meson6.dtsi @@ -0,0 +1,80 @@ +/* + * Copyright 2014 Carlo Caione <carlo@caione.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/include/ "meson.dtsi" + +/ { + model = "Amlogic Meson6 SoC"; + compatible = "amlogic,meson6"; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x200>; + }; + + cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x201>; + }; + }; + + clk81: clk@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; +}; /* end of / */ diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi new file mode 100644 index 000000000000..1f442a7fe03b --- /dev/null +++ b/arch/arm/boot/dts/meson8.dtsi @@ -0,0 +1,92 @@ +/* + * Copyright 2014 Carlo Caione <carlo@caione.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/include/ "meson.dtsi" + +/ { + model = "Amlogic Meson8 SoC"; + compatible = "amlogic,meson8"; + + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x200>; + }; + + cpu@201 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x201>; + }; + + cpu@202 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x202>; + }; + + cpu@203 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + next-level-cache = <&L2>; + reg = <0x203>; + }; + }; + + clk81: clk@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <141666666>; + }; +}; /* end of / */ diff --git a/arch/arm/boot/dts/mmp2-brownstone.dts b/arch/arm/boot/dts/mmp2-brownstone.dts index 7f70a39459f6..350208c5e1ed 100644 --- a/arch/arm/boot/dts/mmp2-brownstone.dts +++ b/arch/arm/boot/dts/mmp2-brownstone.dts @@ -8,7 +8,7 @@ */ /dts-v1/; -/include/ "mmp2.dtsi" +#include "mmp2.dtsi" / { model = "Marvell MMP2 Brownstone Development Board"; diff --git a/arch/arm/boot/dts/mmp2.dtsi b/arch/arm/boot/dts/mmp2.dtsi index 4e8b08c628c7..766bbb8495b6 100644 --- a/arch/arm/boot/dts/mmp2.dtsi +++ b/arch/arm/boot/dts/mmp2.dtsi @@ -7,7 +7,8 @@ * publishhed by the Free Software Foundation. */ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" +#include <dt-bindings/clock/marvell,mmp2.h> / { aliases { @@ -135,6 +136,8 @@ compatible = "mrvl,mmp-uart"; reg = <0xd4030000 0x1000>; interrupts = <27>; + clocks = <&soc_clocks MMP2_CLK_UART0>; + resets = <&soc_clocks MMP2_CLK_UART0>; status = "disabled"; }; @@ -142,6 +145,8 @@ compatible = "mrvl,mmp-uart"; reg = <0xd4017000 0x1000>; interrupts = <28>; + clocks = <&soc_clocks MMP2_CLK_UART1>; + resets = <&soc_clocks MMP2_CLK_UART1>; status = "disabled"; }; @@ -149,6 +154,8 @@ compatible = "mrvl,mmp-uart"; reg = <0xd4018000 0x1000>; interrupts = <24>; + clocks = <&soc_clocks MMP2_CLK_UART2>; + resets = <&soc_clocks MMP2_CLK_UART2>; status = "disabled"; }; @@ -156,6 +163,8 @@ compatible = "mrvl,mmp-uart"; reg = <0xd4016000 0x1000>; interrupts = <46>; + clocks = <&soc_clocks MMP2_CLK_UART3>; + resets = <&soc_clocks MMP2_CLK_UART3>; status = "disabled"; }; @@ -168,6 +177,8 @@ #gpio-cells = <2>; interrupts = <49>; interrupt-names = "gpio_mux"; + clocks = <&soc_clocks MMP2_CLK_GPIO>; + resets = <&soc_clocks MMP2_CLK_GPIO>; interrupt-controller; #interrupt-cells = <1>; ranges; @@ -201,6 +212,8 @@ compatible = "mrvl,mmp-twsi"; reg = <0xd4011000 0x1000>; interrupts = <7>; + clocks = <&soc_clocks MMP2_CLK_TWSI0>; + resets = <&soc_clocks MMP2_CLK_TWSI0>; #address-cells = <1>; #size-cells = <0>; mrvl,i2c-fast-mode; @@ -211,6 +224,8 @@ compatible = "mrvl,mmp-twsi"; reg = <0xd4025000 0x1000>; interrupts = <58>; + clocks = <&soc_clocks MMP2_CLK_TWSI1>; + resets = <&soc_clocks MMP2_CLK_TWSI1>; status = "disabled"; }; @@ -220,8 +235,20 @@ interrupts = <1 0>; interrupt-names = "rtc 1Hz", "rtc alarm"; interrupt-parent = <&intcmux5>; + clocks = <&soc_clocks MMP2_CLK_RTC>; + resets = <&soc_clocks MMP2_CLK_RTC>; status = "disabled"; }; }; + + soc_clocks: clocks{ + compatible = "marvell,mmp2-clock"; + reg = <0xd4050000 0x1000>, + <0xd4282800 0x400>, + <0xd4015000 0x1000>; + reg-names = "mpmu", "apmu", "apbc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; }; }; diff --git a/arch/arm/boot/dts/mt6589-aquaris5.dts b/arch/arm/boot/dts/mt6589-aquaris5.dts index 443b4467de15..0da047013120 100644 --- a/arch/arm/boot/dts/mt6589-aquaris5.dts +++ b/arch/arm/boot/dts/mt6589-aquaris5.dts @@ -18,6 +18,11 @@ / { model = "bq Aquaris5"; + compatible = "mundoreader,bq-aquaris5", "mediatek,mt6589"; + + chosen { + bootargs = "earlyprintk"; + }; memory { reg = <0x80000000 0x40000000>; diff --git a/arch/arm/boot/dts/mt6589.dtsi b/arch/arm/boot/dts/mt6589.dtsi index d0297a051549..e3c7600ddb38 100644 --- a/arch/arm/boot/dts/mt6589.dtsi +++ b/arch/arm/boot/dts/mt6589.dtsi @@ -81,8 +81,8 @@ clock-names = "system-clk", "rtc-clk"; }; - gic: interrupt-controller@10212000 { - compatible = "arm,cortex-a15-gic"; + gic: interrupt-controller@10211000 { + compatible = "arm,cortex-a7-gic"; interrupt-controller; #interrupt-cells = <3>; reg = <0x10211000 0x1000>, diff --git a/arch/arm/boot/dts/mt6592-evb.dts b/arch/arm/boot/dts/mt6592-evb.dts new file mode 100644 index 000000000000..b57237e6394a --- /dev/null +++ b/arch/arm/boot/dts/mt6592-evb.dts @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Howard Chen <ibanezchen@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +#include "mt6592.dtsi" + +/ { + model = "mt6592 evb"; + compatible = "mediatek,mt6592-evb", "mediatek,mt6592"; + + memory { + reg = <0x80000000 0x40000000>; + }; +}; + diff --git a/arch/arm/boot/dts/mt6592.dtsi b/arch/arm/boot/dts/mt6592.dtsi new file mode 100644 index 000000000000..31e5a0979d78 --- /dev/null +++ b/arch/arm/boot/dts/mt6592.dtsi @@ -0,0 +1,98 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Howard Chen <ibanezchen@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include "skeleton.dtsi" + +/ { + compatible = "mediatek,mt6592"; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x3>; + }; + cpu@4 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x4>; + }; + cpu@5 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x5>; + }; + cpu@6 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x6>; + }; + cpu@7 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x7>; + }; + }; + + system_clk: dummy13m { + compatible = "fixed-clock"; + clock-frequency = <13000000>; + #clock-cells = <0>; + }; + + rtc_clk: dummy32k { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + + timer: timer@10008000 { + compatible = "mediatek,mt6577-timer"; + reg = <0x10008000 0x80>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&system_clk>, <&rtc_clk>; + clock-names = "system-clk", "rtc-clk"; + }; + + gic: interrupt-controller@10211000 { + compatible = "arm,cortex-a7-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x10211000 0x1000>, + <0x10212000 0x1000>; + }; + +}; + diff --git a/arch/arm/boot/dts/mt8127-moose.dts b/arch/arm/boot/dts/mt8127-moose.dts new file mode 100644 index 000000000000..13cba0e77e08 --- /dev/null +++ b/arch/arm/boot/dts/mt8127-moose.dts @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Joe.C <yingjoe.chen@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +#include "mt8127.dtsi" + +/ { + model = "MediaTek MT8127 Moose Board"; + compatible = "mediatek,mt8127-moose", "mediatek,mt8127"; + + memory { + reg = <0 0x80000000 0 0x40000000>; + }; +}; diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mt8127.dtsi new file mode 100644 index 000000000000..b24c0a2f3c44 --- /dev/null +++ b/arch/arm/boot/dts/mt8127.dtsi @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Joe.C <yingjoe.chen@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include "skeleton64.dtsi" + +/ { + compatible = "mediatek,mt8127"; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x0>; + }; + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x1>; + }; + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x2>; + }; + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x3>; + }; + + }; + + clocks { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + system_clk: dummy13m { + compatible = "fixed-clock"; + clock-frequency = <13000000>; + #clock-cells = <0>; + }; + + rtc_clk: dummy32k { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + timer: timer@10008000 { + compatible = "mediatek,mt8127-timer", + "mediatek,mt6577-timer"; + reg = <0 0x10008000 0 0x80>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&system_clk>, <&rtc_clk>; + clock-names = "system-clk", "rtc-clk"; + }; + + gic: interrupt-controller@10211000 { + compatible = "arm,cortex-a7-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0 0x10211000 0 0x1000>, + <0 0x10212000 0 0x1000>, + <0 0x10214000 0 0x2000>, + <0 0x10216000 0 0x2000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/mt8135-evbp1.dts b/arch/arm/boot/dts/mt8135-evbp1.dts new file mode 100644 index 000000000000..a5adf9742308 --- /dev/null +++ b/arch/arm/boot/dts/mt8135-evbp1.dts @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Joe.C <yingjoe.chen@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/dts-v1/; +#include "mt8135.dtsi" + +/ { + model = "MediaTek MT8135 evaluation board"; + compatible = "mediatek,mt8135-evbp1", "mediatek,mt8135"; + + memory { + reg = <0 0x80000000 0 0x40000000>; + }; +}; diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi new file mode 100644 index 000000000000..7d56a986358e --- /dev/null +++ b/arch/arm/boot/dts/mt8135.dtsi @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2014 MediaTek Inc. + * Author: Joe.C <yingjoe.chen@mediatek.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include "skeleton64.dtsi" + +/ { + compatible = "mediatek,mt8135"; + interrupt-parent = <&gic>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu2>; + }; + core1 { + cpu = <&cpu3>; + }; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0x001>; + }; + + cpu2: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x100>; + }; + + cpu3: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0x101>; + }; + }; + + clocks { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + system_clk: dummy13m { + compatible = "fixed-clock"; + clock-frequency = <13000000>; + #clock-cells = <0>; + }; + + rtc_clk: dummy32k { + compatible = "fixed-clock"; + clock-frequency = <32000>; + #clock-cells = <0>; + }; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + timer: timer@10008000 { + compatible = "mediatek,mt8135-timer", + "mediatek,mt6577-timer"; + reg = <0 0x10008000 0 0x80>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&system_clk>, <&rtc_clk>; + clock-names = "system-clk", "rtc-clk"; + }; + + gic: interrupt-controller@10211000 { + compatible = "arm,cortex-a15-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0 0x10211000 0 0x1000>, + <0 0x10212000 0 0x1000>, + <0 0x10214000 0 0x2000>, + <0 0x10216000 0 0x2000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi b/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi index 521c587acaee..445fafc73254 100644 --- a/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi +++ b/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi @@ -23,24 +23,29 @@ ethernet@gpmc { compatible = "smsc,lan9221", "smsc,lan9115"; bank-width = <2>; - gpmc,mux-add-data; - gpmc,cs-on-ns = <1>; - gpmc,cs-rd-off-ns = <180>; - gpmc,cs-wr-off-ns = <180>; - gpmc,adv-rd-off-ns = <18>; - gpmc,adv-wr-off-ns = <48>; - gpmc,oe-on-ns = <54>; - gpmc,oe-off-ns = <168>; - gpmc,we-on-ns = <54>; - gpmc,we-off-ns = <168>; - gpmc,rd-cycle-ns = <186>; - gpmc,wr-cycle-ns = <186>; - gpmc,access-ns = <144>; - gpmc,page-burst-access-ns = <24>; - gpmc,bus-turnaround-ns = <90>; - gpmc,cycle2cycle-delay-ns = <90>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-diffcsen; + gpmc,device-width = <1>; + gpmc,cycle2cycle-samecsen = <1>; + gpmc,cycle2cycle-diffcsen = <1>; + gpmc,cs-on-ns = <5>; + gpmc,cs-rd-off-ns = <150>; + gpmc,cs-wr-off-ns = <150>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <15>; + gpmc,adv-wr-off-ns = <40>; + gpmc,oe-on-ns = <45>; + gpmc,oe-off-ns = <140>; + gpmc,we-on-ns = <45>; + gpmc,we-off-ns = <140>; + gpmc,rd-cycle-ns = <155>; + gpmc,wr-cycle-ns = <155>; + gpmc,access-ns = <120>; + gpmc,page-burst-access-ns = <20>; + gpmc,bus-turnaround-ns = <75>; + gpmc,cycle2cycle-delay-ns = <75>; + gpmc,wait-monitoring-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-data-mux-bus-ns = <0>; + gpmc,wr-access-ns = <0>; vddvario-supply = <&vddvario>; vdd33a-supply = <&vdd33a>; reg-io-width = <4>; diff --git a/arch/arm/boot/dts/omap-zoom-common.dtsi b/arch/arm/boot/dts/omap-zoom-common.dtsi index 68221fab978d..46ef3e443861 100644 --- a/arch/arm/boot/dts/omap-zoom-common.dtsi +++ b/arch/arm/boot/dts/omap-zoom-common.dtsi @@ -5,7 +5,7 @@ #include "omap-gpmc-smsc911x.dtsi" &gpmc { - ranges = <3 0 0x10000000 0x00000400>, + ranges = <3 0 0x10000000 0x1000000>, /* CS3: 16MB for UART */ <7 0 0x2c000000 0x01000000>; /* @@ -15,7 +15,65 @@ */ uart@3,0 { compatible = "ns16550a"; - reg = <3 0 0x100>; + reg = <3 0 8>; /* CS3, offset 0, IO size 8 */ + bank-width = <2>; + reg-shift = <1>; + reg-io-width = <1>; + interrupt-parent = <&gpio4>; + interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */ + clock-frequency = <1843200>; + current-speed = <115200>; + gpmc,mux-add-data = <0>; + gpmc,device-width = <1>; + gpmc,wait-pin = <1>; + gpmc,cycle2cycle-samecsen = <1>; + gpmc,cycle2cycle-diffcsen = <1>; + gpmc,cs-on-ns = <5>; + gpmc,cs-rd-off-ns = <155>; + gpmc,cs-wr-off-ns = <155>; + gpmc,adv-on-ns = <15>; + gpmc,adv-rd-off-ns = <40>; + gpmc,adv-wr-off-ns = <40>; + gpmc,oe-on-ns = <45>; + gpmc,oe-off-ns = <145>; + gpmc,we-on-ns = <45>; + gpmc,we-off-ns = <145>; + gpmc,rd-cycle-ns = <155>; + gpmc,wr-cycle-ns = <155>; + gpmc,access-ns = <145>; + gpmc,page-burst-access-ns = <20>; + gpmc,bus-turnaround-ns = <20>; + gpmc,cycle2cycle-delay-ns = <20>; + gpmc,wait-monitoring-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-data-mux-bus-ns = <45>; + gpmc,wr-access-ns = <145>; + }; + uart@3,1 { + compatible = "ns16550a"; + reg = <3 0x100 8>; /* CS3, offset 0x100, IO size 8 */ + bank-width = <2>; + reg-shift = <1>; + reg-io-width = <1>; + interrupt-parent = <&gpio4>; + interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */ + clock-frequency = <1843200>; + current-speed = <115200>; + }; + uart@3,2 { + compatible = "ns16550a"; + reg = <3 0x200 8>; /* CS3, offset 0x200, IO size 8 */ + bank-width = <2>; + reg-shift = <1>; + reg-io-width = <1>; + interrupt-parent = <&gpio4>; + interrupts = <6 IRQ_TYPE_EDGE_RISING>; /* gpio102 */ + clock-frequency = <1843200>; + current-speed = <115200>; + }; + uart@3,3 { + compatible = "ns16550a"; + reg = <3 0x300 8>; /* CS3, offset 0x300, IO size 8 */ bank-width = <2>; reg-shift = <1>; reg-io-width = <1>; diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi index 8f8c07da4ac1..59d1c297bb30 100644 --- a/arch/arm/boot/dts/omap2.dtsi +++ b/arch/arm/boot/dts/omap2.dtsi @@ -75,7 +75,6 @@ compatible = "ti,omap2-intc"; interrupt-controller; #interrupt-cells = <1>; - ti,intc-size = <96>; reg = <0x480FE000 0x1000>; }; diff --git a/arch/arm/boot/dts/omap2420-n810.dts b/arch/arm/boot/dts/omap2420-n810.dts index 21baec154b78..b604d26bd48c 100644 --- a/arch/arm/boot/dts/omap2420-n810.dts +++ b/arch/arm/boot/dts/omap2420-n810.dts @@ -6,3 +6,10 @@ model = "Nokia N810"; compatible = "nokia,n810", "nokia,n8x0", "ti,omap2420", "ti,omap2"; }; + +&i2c2 { + aic3x@18 { + compatible = "tlv320aic3x"; + reg = <0x18>; + }; +}; diff --git a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi index 89608b206519..c9f1e93a95ae 100644 --- a/arch/arm/boot/dts/omap2420-n8x0-common.dtsi +++ b/arch/arm/boot/dts/omap2420-n8x0-common.dtsi @@ -27,6 +27,12 @@ &i2c1 { clock-frequency = <400000>; + + pmic@72 { + compatible = "menelaus"; + reg = <0x72>; + interrupts = <7 IRQ_TYPE_EDGE_RISING>; + }; }; &i2c2 { @@ -34,14 +40,14 @@ }; &gpmc { - ranges = <0 0 0x04000000 0x10000000>; + ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */ /* gpio-irq for dma: 26 */ onenand@0,0 { #address-cells = <1>; #size-cells = <1>; - reg = <0 0 0x10000000>; + reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ gpmc,sync-read; gpmc,burst-length = <16>; diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi index 9be3c1266378..e2b2e93d7b61 100644 --- a/arch/arm/boot/dts/omap2420.dtsi +++ b/arch/arm/boot/dts/omap2420.dtsi @@ -157,8 +157,17 @@ interrupts = <26>, <34>; interrupt-names = "dsp", "iva"; ti,hwmods = "mailbox"; + #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <6>; + mbox_dsp: dsp { + ti,mbox-tx = <0 0 0>; + ti,mbox-rx = <1 0 0>; + }; + mbox_iva: iva { + ti,mbox-tx = <2 1 3>; + ti,mbox-rx = <3 1 3>; + }; }; timer1: timer@48028000 { diff --git a/arch/arm/boot/dts/omap2430-sdp.dts b/arch/arm/boot/dts/omap2430-sdp.dts index 2c90d29b4cad..6b36ede58488 100644 --- a/arch/arm/boot/dts/omap2430-sdp.dts +++ b/arch/arm/boot/dts/omap2430-sdp.dts @@ -43,7 +43,31 @@ interrupts = <21 IRQ_TYPE_LEVEL_LOW>; /* gpio149 */ reg = <5 0x300 0xf>; bank-width = <2>; - gpmc,mux-add-data; - }; + gpmc,sync-clk-ps = <0>; + gpmc,mux-add-data = <2>; + gpmc,device-width = <1>; + gpmc,cycle2cycle-samecsen = <1>; + gpmc,cycle2cycle-diffcsen = <1>; + gpmc,cs-on-ns = <6>; + gpmc,cs-rd-off-ns = <187>; + gpmc,cs-wr-off-ns = <187>; + gpmc,adv-on-ns = <18>; + gpmc,adv-rd-off-ns = <48>; + gpmc,adv-wr-off-ns = <48>; + gpmc,oe-on-ns = <60>; + gpmc,oe-off-ns = <169>; + gpmc,we-on-ns = <66>; + gpmc,we-off-ns = <169>; + gpmc,rd-cycle-ns = <187>; + gpmc,wr-cycle-ns = <187>; + gpmc,access-ns = <187>; + gpmc,page-burst-access-ns = <24>; + gpmc,bus-turnaround-ns = <24>; + gpmc,cycle2cycle-delay-ns = <24>; + gpmc,wait-monitoring-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-data-mux-bus-ns = <0>; + gpmc,wr-access-ns = <0>; + }; }; diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi index 1a00f15d9096..0dc8de2782b1 100644 --- a/arch/arm/boot/dts/omap2430.dtsi +++ b/arch/arm/boot/dts/omap2430.dtsi @@ -247,8 +247,13 @@ reg = <0x48094000 0x200>; interrupts = <26>; ti,hwmods = "mailbox"; + #mbox-cells = <1>; ti,mbox-num-users = <4>; ti,mbox-num-fifos = <6>; + mbox_dsp: dsp { + ti,mbox-tx = <0 0 0>; + ti,mbox-rx = <1 0 0>; + }; }; timer1: timer@49018000 { diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts index 1becefce821b..25f7b0a22114 100644 --- a/arch/arm/boot/dts/omap3-beagle-xm.dts +++ b/arch/arm/boot/dts/omap3-beagle-xm.dts @@ -145,6 +145,34 @@ }; }; }; + + etb@5401b000 { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0x5401b000 0x1000>; + + coresight-default-sink; + clocks = <&emu_src_ck>; + clock-names = "apb_pclk"; + port { + etb_in: endpoint { + slave-mode; + remote-endpoint = <&etm_out>; + }; + }; + }; + + etm@54010000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x54010000 0x1000>; + + clocks = <&emu_src_ck>; + clock-names = "apb_pclk"; + port { + etm_out: endpoint { + remote-endpoint = <&etb_in>; + }; + }; + }; }; &omap3_pmx_wkup { @@ -174,8 +202,8 @@ uart3_pins: pinmux_uart3_pins { pinctrl-single,pins = < - 0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */ + 0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ + 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */ >; }; diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts index a9aae88b74f5..c792391ef090 100644 --- a/arch/arm/boot/dts/omap3-beagle.dts +++ b/arch/arm/boot/dts/omap3-beagle.dts @@ -140,6 +140,34 @@ }; }; }; + + etb@540000000 { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0x5401b000 0x1000>; + + coresight-default-sink; + clocks = <&emu_src_ck>; + clock-names = "apb_pclk"; + port { + etb_in: endpoint { + slave-mode; + remote-endpoint = <&etm_out>; + }; + }; + }; + + etm@54010000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0x54010000 0x1000>; + + clocks = <&emu_src_ck>; + clock-names = "apb_pclk"; + port { + etm_out: endpoint { + remote-endpoint = <&etb_in>; + }; + }; + }; }; &omap3_pmx_wkup { diff --git a/arch/arm/boot/dts/omap3-cm-t3517.dts b/arch/arm/boot/dts/omap3-cm-t3517.dts index d00502f4fd9b..0ab748cf7749 100644 --- a/arch/arm/boot/dts/omap3-cm-t3517.dts +++ b/arch/arm/boot/dts/omap3-cm-t3517.dts @@ -134,3 +134,14 @@ bus-width = <4>; cap-power-off-card; }; + +&dss { + status = "ok"; + + pinctrl-names = "default"; + pinctrl-0 = < + &dss_dpi_pins_common + &dss_dpi_pins_cm_t35x + >; +}; + diff --git a/arch/arm/boot/dts/omap3-cm-t3530.dts b/arch/arm/boot/dts/omap3-cm-t3530.dts index d1458496520e..8dd14fcf6825 100644 --- a/arch/arm/boot/dts/omap3-cm-t3530.dts +++ b/arch/arm/boot/dts/omap3-cm-t3530.dts @@ -46,3 +46,14 @@ bus-width = <4>; cap-power-off-card; }; + +&dss { + status = "ok"; + + pinctrl-names = "default"; + pinctrl-0 = < + &dss_dpi_pins_common + &dss_dpi_pins_cm_t35x + >; +}; + diff --git a/arch/arm/boot/dts/omap3-cm-t3730.dts b/arch/arm/boot/dts/omap3-cm-t3730.dts index b3f9a50b3bc8..46eadb21b5ef 100644 --- a/arch/arm/boot/dts/omap3-cm-t3730.dts +++ b/arch/arm/boot/dts/omap3-cm-t3730.dts @@ -31,6 +31,19 @@ }; }; +&omap3_pmx_wkup { + dss_dpi_pins_cm_t3730: pinmux_dss_dpi_pins_cm_t3730 { + pinctrl-single,pins = < + OMAP3_WKUP_IOPAD(0x2a08, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */ + OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */ + OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */ + OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */ + OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */ + OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */ + >; + }; +}; + &omap3_pmx_core { mmc2_pins: pinmux_mmc2_pins { @@ -61,3 +74,14 @@ bus-width = <4>; cap-power-off-card; }; + +&dss { + status = "ok"; + + pinctrl-names = "default"; + pinctrl-0 = < + &dss_dpi_pins_common + &dss_dpi_pins_cm_t3730 + >; +}; + diff --git a/arch/arm/boot/dts/omap3-cm-t3x.dtsi b/arch/arm/boot/dts/omap3-cm-t3x.dtsi index c671a2299ea8..6ea6d460db30 100644 --- a/arch/arm/boot/dts/omap3-cm-t3x.dtsi +++ b/arch/arm/boot/dts/omap3-cm-t3x.dtsi @@ -49,6 +49,24 @@ compatible = "usb-nop-xceiv"; vcc-supply = <&hsusb2_power>; }; + + ads7846reg: ads7846-reg { + compatible = "regulator-fixed"; + regulator-name = "ads7846-reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + tv0: connector@1 { + compatible = "svideo-connector"; + label = "tv"; + + port { + tv_connector_in: endpoint { + remote-endpoint = <&venc_out>; + }; + }; + }; }; &omap3_pmx_core { @@ -76,6 +94,76 @@ OMAP3_CORE1_IOPAD(0x21e2, PIN_OUTPUT | MUX_MODE4) /* sys_clkout2.gpio_186 */ >; }; + + dss_dpi_pins_common: pinmux_dss_dpi_pins_common { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ + OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ + OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ + OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ + OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ + OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ + >; + }; + + dss_dpi_pins_cm_t35x: pinmux_dss_dpi_pins_cm_t35x { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ + OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ + OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ + OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ + OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ + OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ + >; + }; + + ads7846_pins: pinmux_ads7846_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20ba, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_ncs6.gpio_57 */ + >; + }; + + mcspi1_pins: pinmux_mcspi1_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk */ + OMAP3_CORE1_IOPAD(0x21ca, PIN_INPUT | MUX_MODE0) /* mcspi1_simo */ + OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT | MUX_MODE0) /* mcspi1_somi */ + OMAP3_CORE1_IOPAD(0x21ce, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcspi1_cs0 */ + >; + }; + + i2c1_pins: pinmux_i2c1_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ + OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ + >; + }; + + mcbsp2_pins: pinmux_mcbsp2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x213c, PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx */ + OMAP3_CORE1_IOPAD(0x213e, PIN_INPUT | MUX_MODE0) /* mcbsp2_clkx */ + OMAP3_CORE1_IOPAD(0x2140, PIN_INPUT | MUX_MODE0) /* mcbsp2_dr */ + OMAP3_CORE1_IOPAD(0x2142, PIN_OUTPUT | MUX_MODE0) /* mcbsp2_dx */ + >; + }; }; &uart3 { @@ -94,12 +182,22 @@ }; &i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <400000>; + + at24@50 { + compatible = "at24,24c02"; + pagesize = <16>; + reg = <0x50>; + }; }; &i2c3 { clock-frequency = <400000>; }; + &usbhshost { port1-mode = "ehci-phy"; port2-mode = "ehci-phy"; @@ -108,3 +206,56 @@ &usbhsehci { phys = <&hsusb1_phy &hsusb2_phy>; }; + +&mcspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcspi1_pins>; + + /* touch controller */ + ads7846@0 { + pinctrl-names = "default"; + pinctrl-0 = <&ads7846_pins>; + + compatible = "ti,ads7846"; + vcc-supply = <&ads7846reg>; + + reg = <0>; /* CS0 */ + spi-max-frequency = <1500000>; + + interrupt-parent = <&gpio2>; + interrupts = <25 0>; /* gpio_57 */ + pendown-gpio = <&gpio2 25 0>; + + ti,x-min = /bits/ 16 <0x0>; + ti,x-max = /bits/ 16 <0x0fff>; + ti,y-min = /bits/ 16 <0x0>; + ti,y-max = /bits/ 16 <0x0fff>; + + ti,x-plate-ohms = /bits/ 16 <180>; + ti,pressure-max = /bits/ 16 <255>; + + ti,debounce-max = /bits/ 16 <30>; + ti,debounce-tol = /bits/ 16 <10>; + ti,debounce-rep = /bits/ 16 <1>; + + linux,wakeup; + }; +}; + +&venc { + status = "ok"; + + port { + venc_out: endpoint { + remote-endpoint = <&tv_connector_in>; + ti,channels = <2>; + }; + }; +}; + +&mcbsp2 { + status = "ok"; + + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp2_pins>; +}; diff --git a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi index 25ba08331d88..9a4a3ab9af78 100644 --- a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi +++ b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi @@ -10,6 +10,14 @@ cpu0-supply = <&vcc>; }; }; + + sound { + compatible = "ti,omap-twl4030"; + ti,model = "cm-t35"; + + ti,mcbsp = <&mcbsp2>; + ti,codec = <&twl_audio>; + }; }; &omap3_pmx_core { @@ -59,11 +67,22 @@ reg = <0x48>; interrupts = <7>; /* SYS_NIRQ cascaded to intc */ interrupt-parent = <&intc>; + + twl_audio: audio { + compatible = "ti,twl4030-audio"; + codec { + }; + }; }; }; #include "twl4030.dtsi" #include "twl4030_omap3.dtsi" +#include <dt-bindings/input/input.h> + +&venc { + vdda-supply = <&vdac>; +}; &mmc1 { vmmc-supply = <&vmmc1>; @@ -75,6 +94,22 @@ ti,pullups = <0x000001>; }; +&twl_keypad { + linux,keymap = < + MATRIX_KEY(0x00, 0x01, KEY_A) + MATRIX_KEY(0x00, 0x02, KEY_B) + MATRIX_KEY(0x00, 0x03, KEY_LEFT) + + MATRIX_KEY(0x01, 0x01, KEY_UP) + MATRIX_KEY(0x01, 0x02, KEY_ENTER) + MATRIX_KEY(0x01, 0x03, KEY_DOWN) + + MATRIX_KEY(0x02, 0x01, KEY_RIGHT) + MATRIX_KEY(0x02, 0x02, KEY_C) + MATRIX_KEY(0x02, 0x03, KEY_D) + >; +}; + &hsusb1_phy { reset-gpios = <&twl_gpio 6 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts index da402f0fdab4..169037e5ff53 100644 --- a/arch/arm/boot/dts/omap3-devkit8000.dts +++ b/arch/arm/boot/dts/omap3-devkit8000.dts @@ -106,10 +106,10 @@ }; &gpmc { - ranges = <0 0 0x30000000 0x04>; /* CS0: NAND */ + ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ nand@0,0 { - reg = <0 0 0>; /* CS0, offset 0 */ + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ nand-bus-width = <16>; gpmc,sync-clk-ps = <0>; diff --git a/arch/arm/boot/dts/omap3-evm-37xx.dts b/arch/arm/boot/dts/omap3-evm-37xx.dts index a8bd4349c7d2..16e8ce350dda 100644 --- a/arch/arm/boot/dts/omap3-evm-37xx.dts +++ b/arch/arm/boot/dts/omap3-evm-37xx.dts @@ -154,13 +154,14 @@ }; &gpmc { - ranges = <0 0 0x00000000 0x20000000>, + ranges = <0 0 0x00000000 0x1000000>, /* CS0: 16MB for NAND */ <5 0 0x2c000000 0x01000000>; nand@0,0 { linux,mtd-name= "hynix,h8kds0un0mer-4em"; - reg = <0 0 0>; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ nand-bus-width = <16>; + gpmc,device-width = <2>; ti,nand-ecc-opt = "bch8"; gpmc,sync-clk-ps = <0>; diff --git a/arch/arm/boot/dts/omap3-evm-common.dtsi b/arch/arm/boot/dts/omap3-evm-common.dtsi index c8747c7f1cc8..127f3e7c10c4 100644 --- a/arch/arm/boot/dts/omap3-evm-common.dtsi +++ b/arch/arm/boot/dts/omap3-evm-common.dtsi @@ -2,6 +2,7 @@ * Common support for omap3 EVM boards */ +#include <dt-bindings/input/input.h> #include "omap-gpmc-smsc911x.dtsi" / { @@ -111,6 +112,26 @@ ti,use-leds; }; +&twl_keypad { + linux,keymap = < + MATRIX_KEY(2, 2, KEY_1) + MATRIX_KEY(1, 1, KEY_2) + MATRIX_KEY(0, 0, KEY_3) + MATRIX_KEY(3, 2, KEY_4) + MATRIX_KEY(2, 1, KEY_5) + MATRIX_KEY(1, 0, KEY_6) + MATRIX_KEY(1, 3, KEY_7) + MATRIX_KEY(3, 1, KEY_8) + MATRIX_KEY(2, 0, KEY_9) + MATRIX_KEY(2, 3, KEY_KPASTERISK) + MATRIX_KEY(0, 2, KEY_0) + MATRIX_KEY(3, 0, KEY_KPDOT) + /* s4 not wired */ + MATRIX_KEY(1, 2, KEY_BACKSPACE) + MATRIX_KEY(0, 1, KEY_ENTER) + >; +}; + &usb_otg_hs { interface-type = <0>; usb-phy = <&usb2_phy>; diff --git a/arch/arm/boot/dts/omap3-gta04.dts b/arch/arm/boot/dts/omap3-gta04.dts deleted file mode 100644 index 021311f7964b..000000000000 --- a/arch/arm/boot/dts/omap3-gta04.dts +++ /dev/null @@ -1,311 +0,0 @@ -/* - * Copyright (C) 2013 Marek Belisko <marek@goldelico.com> - * - * Based on omap3-beagle-xm.dts - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ -/dts-v1/; - -#include "omap36xx.dtsi" - -/ { - model = "OMAP3 GTA04"; - compatible = "ti,omap3-gta04", "ti,omap36xx", "ti,omap3"; - - cpus { - cpu@0 { - cpu0-supply = <&vcc>; - }; - }; - - memory { - device_type = "memory"; - reg = <0x80000000 0x20000000>; /* 512 MB */ - }; - - gpio-keys { - compatible = "gpio-keys"; - - aux-button { - label = "aux"; - linux,code = <169>; - gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; - gpio-key,wakeup; - }; - }; - - sound { - compatible = "ti,omap-twl4030"; - ti,model = "gta04"; - - ti,mcbsp = <&mcbsp2>; - ti,codec = <&twl_audio>; - }; - - spi_lcd { - compatible = "spi-gpio"; - #address-cells = <0x1>; - #size-cells = <0x0>; - pinctrl-names = "default"; - pinctrl-0 = <&spi_gpio_pins>; - - gpio-sck = <&gpio1 12 0>; - gpio-miso = <&gpio1 18 0>; - gpio-mosi = <&gpio1 20 0>; - cs-gpios = <&gpio1 19 0>; - num-chipselects = <1>; - - /* lcd panel */ - lcd: td028ttec1@0 { - compatible = "toppoly,td028ttec1"; - reg = <0>; - spi-max-frequency = <100000>; - spi-cpol; - spi-cpha; - - label = "lcd"; - port { - lcd_in: endpoint { - remote-endpoint = <&dpi_out>; - }; - }; - }; - }; -}; - -&omap3_pmx_core { - uart1_pins: pinmux_uart1_pins { - pinctrl-single,pins = < - 0x152 (PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ - 0x14c (PIN_OUTPUT |MUX_MODE0) /* uart1_tx.uart1_tx */ - >; - }; - - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - 0x14a (PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ - 0x148 (PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ - >; - }; - - uart3_pins: pinmux_uart3_pins { - pinctrl-single,pins = < - 0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */ - 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */ - >; - }; - - mmc1_pins: pinmux_mmc1_pins { - pinctrl-single,pins = < - 0x114 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ - 0x116 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ - 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ - 0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ - 0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ - 0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ - >; - }; - - dss_dpi_pins: pinmux_dss_dpi_pins { - pinctrl-single,pins = < - 0x0a4 (PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - 0x0a6 (PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - 0x0a8 (PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - 0x0aa (PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - 0x0ac (PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - 0x0ae (PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - 0x0b0 (PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - 0x0b2 (PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - 0x0b4 (PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - 0x0b6 (PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - 0x0b8 (PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - 0x0ba (PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - 0x0bc (PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - 0x0be (PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - 0x0c0 (PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - 0x0c2 (PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - 0x0c4 (PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - 0x0c6 (PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - 0x0c8 (PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - 0x0ca (PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - 0x0cc (PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - 0x0ce (PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - 0x0d0 (PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - 0x0d2 (PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - 0x0d4 (PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - 0x0d6 (PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - 0x0d8 (PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - 0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ - >; - }; - - spi_gpio_pins: spi_gpio_pinmux { - pinctrl-single,pins = <0x5a8 (PIN_OUTPUT | MUX_MODE4) /* clk */ - 0x5b6 (PIN_OUTPUT | MUX_MODE4) /* cs */ - 0x5b8 (PIN_OUTPUT | MUX_MODE4) /* tx */ - 0x5b4 (PIN_INPUT | MUX_MODE4) /* rx */ - >; - }; -}; - -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - }; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - codec { - }; - }; -}; - -#include "twl4030.dtsi" -#include "twl4030_omap3.dtsi" - -&i2c2 { - clock-frequency = <400000>; - - /* pressure sensor */ - bmp085@77 { - compatible = "bosch,bmp085"; - reg = <0x77>; - interrupt-parent = <&gpio4>; - interrupts = <17 IRQ_TYPE_EDGE_RISING>; - }; - - /* accelerometer */ - bma180@41 { - compatible = "bosch,bma180"; - reg = <0x41>; - interrupt-parent = <&gpio3>; - interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; - }; - - /* leds */ - tca6507@45 { - compatible = "ti,tca6507"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x45>; - - gta04_led0: red_aux@0 { - label = "gta04:red:aux"; - reg = <0x0>; - }; - - gta04_led1: green_aux@1 { - label = "gta04:green:aux"; - reg = <0x1>; - }; - - gta04_led3: red_power@3 { - label = "gta04:red:power"; - reg = <0x3>; - linux,default-trigger = "default-on"; - }; - - gta04_led4: green_power@4 { - label = "gta04:green:power"; - reg = <0x4>; - }; - }; - - /* compass aka magnetometer */ - hmc5843@1e { - compatible = "honeywell,hmc5843"; - reg = <0x1e>; - }; - - /* touchscreen */ - tsc2007@48 { - compatible = "ti,tsc2007"; - reg = <0x48>; - interrupt-parent = <&gpio6>; - interrupts = <0 IRQ_TYPE_EDGE_FALLING>; - gpios = <&gpio6 0 GPIO_ACTIVE_LOW>; - ti,x-plate-ohms = <600>; - }; -}; - -&i2c3 { - clock-frequency = <100000>; -}; - -&usb_otg_hs { - interface-type = <0>; - usb-phy = <&usb2_phy>; - phys = <&usb2_phy>; - phy-names = "usb2-phy"; - mode = <3>; - power = <50>; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc1_pins>; - vmmc-supply = <&vmmc1>; - bus-width = <4>; - ti,non-removable; -}; - -&mmc2 { - vmmc-supply = <&vaux4>; - bus-width = <4>; - ti,non-removable; -}; - -&mmc3 { - status = "disabled"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins>; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&uart3_pins>; -}; - -&charger { - bb_uvolt = <3200000>; - bb_uamp = <150>; -}; - -&vaux4 { - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3150000>; -}; - -/* Needed to power the DPI pins */ -&vpll2 { - regulator-always-on; -}; - -&dss { - pinctrl-names = "default"; - pinctrl-0 = < &dss_dpi_pins >; - - status = "okay"; - - port { - dpi_out: endpoint { - remote-endpoint = <&lcd_in>; - data-lines = <24>; - }; - }; -}; diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi new file mode 100644 index 000000000000..655d6e920a86 --- /dev/null +++ b/arch/arm/boot/dts/omap3-gta04.dtsi @@ -0,0 +1,451 @@ +/* + * Copyright (C) 2013 Marek Belisko <marek@goldelico.com> + * + * Based on omap3-beagle-xm.dts + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "omap36xx.dtsi" + +/ { + model = "OMAP3 GTA04"; + compatible = "ti,omap3-gta04", "ti,omap36xx", "ti,omap3"; + + cpus { + cpu@0 { + cpu0-supply = <&vcc>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; /* 512 MB */ + }; + + aliases { + display0 = &lcd; + }; + + gpio-keys { + compatible = "gpio-keys"; + + aux-button { + label = "aux"; + linux,code = <169>; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + gpio-key,wakeup; + }; + }; + + sound { + compatible = "ti,omap-twl4030"; + ti,model = "gta04"; + + ti,mcbsp = <&mcbsp2>; + ti,codec = <&twl_audio>; + }; + + spi_lcd { + compatible = "spi-gpio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + pinctrl-names = "default"; + pinctrl-0 = <&spi_gpio_pins>; + + gpio-sck = <&gpio1 12 0>; + gpio-miso = <&gpio1 18 0>; + gpio-mosi = <&gpio1 20 0>; + cs-gpios = <&gpio1 19 0>; + num-chipselects = <1>; + + /* lcd panel */ + lcd: td028ttec1@0 { + compatible = "toppoly,td028ttec1"; + reg = <0>; + spi-max-frequency = <100000>; + spi-cpol; + spi-cpha; + + label = "lcd"; + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + }; + }; + + hsusb2_phy: hsusb2_phy { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; + }; +}; + +&omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusb2_pins + >; + + hsusb2_pins: pinmux_hsusb2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ + OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ + OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ + OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ + OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ + OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ + >; + }; + + uart1_pins: pinmux_uart1_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2182, PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */ + OMAP3_CORE1_IOPAD(0x217c, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_tx */ + >; + }; + + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ + OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ + >; + }; + + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */ + OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ + OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ + OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ + OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ + OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ + OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ + >; + }; + + dss_dpi_pins: pinmux_dss_dpi_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ + OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ + OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ + OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ + OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ + OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ + OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ + OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ + OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ + OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ + OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ + >; + }; +}; + +&omap3_pmx_core2 { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusb2_2_pins + >; + + hsusb2_2_pins: pinmux_hsusb2_2_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ + OMAP3630_CORE2_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ + OMAP3630_CORE2_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ + OMAP3630_CORE2_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ + OMAP3630_CORE2_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ + OMAP3630_CORE2_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ + >; + }; + + spi_gpio_pins: spi_gpio_pinmux { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE4) /* clk */ + OMAP3630_CORE2_IOPAD(0x25e6, PIN_OUTPUT | MUX_MODE4) /* cs */ + OMAP3630_CORE2_IOPAD(0x25e8, PIN_OUTPUT | MUX_MODE4) /* tx */ + OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT | MUX_MODE4) /* rx */ + >; + }; +}; + +&i2c1 { + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + }; + + twl_audio: audio { + compatible = "ti,twl4030-audio"; + codec { + }; + }; +}; + +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" + +&i2c2 { + clock-frequency = <400000>; + + /* pressure sensor */ + bmp085@77 { + compatible = "bosch,bmp085"; + reg = <0x77>; + interrupt-parent = <&gpio4>; + interrupts = <17 IRQ_TYPE_EDGE_RISING>; + }; + + /* accelerometer */ + bma180@41 { + compatible = "bosch,bma180"; + reg = <0x41>; + interrupt-parent = <&gpio3>; + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; + }; + + /* leds */ + tca6507@45 { + compatible = "ti,tca6507"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x45>; + + gpio-controller; + #gpio-cells = <2>; + + gta04_led0: red_aux@0 { + label = "gta04:red:aux"; + reg = <0x0>; + }; + + gta04_led1: green_aux@1 { + label = "gta04:green:aux"; + reg = <0x1>; + }; + + gta04_led3: red_power@3 { + label = "gta04:red:power"; + reg = <0x3>; + linux,default-trigger = "default-on"; + }; + + gta04_led4: green_power@4 { + label = "gta04:green:power"; + reg = <0x4>; + }; + + wifi_reset: wifi_reset@6 { + reg = <0x6>; + compatible = "gpio"; + }; + }; + + /* compass aka magnetometer */ + hmc5843@1e { + compatible = "honeywell,hmc5883l"; + reg = <0x1e>; + }; + + /* touchscreen */ + tsc2007@48 { + compatible = "ti,tsc2007"; + reg = <0x48>; + interrupt-parent = <&gpio6>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + gpios = <&gpio6 0 GPIO_ACTIVE_LOW>; + ti,x-plate-ohms = <600>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; +}; + +&usb_otg_hs { + interface-type = <0>; + usb-phy = <&usb2_phy>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + mode = <3>; + power = <50>; +}; + +&usbhshost { + port2-mode = "ehci-phy"; +}; + +&usbhsehci { + phys = <0 &hsusb2_phy>; +}; + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <&vmmc1>; + bus-width = <4>; + ti,non-removable; +}; + +&mmc2 { + vmmc-supply = <&vaux4>; + bus-width = <4>; + ti,non-removable; +}; + +&mmc3 { + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&charger { + bb_uvolt = <3200000>; + bb_uamp = <150>; +}; + +/* spare */ +&vaux1 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3000000>; +}; + +/* sensors */ +&vaux2 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; +}; + +/* camera */ +&vaux3 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; +}; + +/* WLAN/BT */ +&vaux4 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3150000>; +}; + +/* GPS LNA */ +&vsim { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3150000>; +}; + +/* Needed to power the DPI pins */ +&vpll2 { + regulator-always-on; +}; + +&dss { + pinctrl-names = "default"; + pinctrl-0 = < &dss_dpi_pins >; + + status = "okay"; + + port { + dpi_out: endpoint { + remote-endpoint = <&lcd_in>; + data-lines = <24>; + }; + }; +}; + +&gpmc { + ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */ + + nand@0,0 { + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + nand-bus-width = <16>; + ti,nand-ecc-opt = "bch8"; + + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-off-ns = <40>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + gpmc,device-width = <2>; + + #address-cells = <1>; + #size-cells = <1>; + + x-loader@0 { + label = "X-Loader"; + reg = <0 0x80000>; + }; + + bootloaders@80000 { + label = "U-Boot"; + reg = <0x80000 0x1e0000>; + }; + + bootloaders_env@260000 { + label = "U-Boot Env"; + reg = <0x260000 0x20000>; + }; + + kernel@280000 { + label = "Kernel"; + reg = <0x280000 0x400000>; + }; + + filesystem@680000 { + label = "File System"; + reg = <0x680000 0xf980000>; + }; + }; +}; diff --git a/arch/arm/boot/dts/omap3-gta04a3.dts b/arch/arm/boot/dts/omap3-gta04a3.dts new file mode 100644 index 000000000000..3099a892cf50 --- /dev/null +++ b/arch/arm/boot/dts/omap3-gta04a3.dts @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2014 H. Nikolaus Schaller <hns@goldelico.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "omap3-gta04.dtsi" + +/ { + model = "Goldelico GTA04A3"; +}; + +&i2c2 { + + /* alternate accelerometer that might be installed on some GTA04A3 boards */ + lis302@1d { + compatible = "st,lis331dlh", "st,lis3lv02d"; + reg = <0x1d>; + interrupt-parent = <&gpio3>; + interrupts = <18 (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)>; + Vdd-supply = <&vaux2>; + Vdd_IO-supply = <&vaux2>; + + st,click-single-x; + st,click-single-y; + st,click-single-z; + st,click-thresh-x = <8>; + st,click-thresh-y = <8>; + st,click-thresh-z = <10>; + st,click-click-time-limit = <9>; + st,click-latency = <50>; + st,irq1-click; + st,wakeup-x-lo; + st,wakeup-x-hi; + st,wakeup-y-lo; + st,wakeup-y-hi; + st,wakeup-z-lo; + st,wakeup-z-hi; + st,min-limit-x = <32>; + st,min-limit-y = <3>; + st,min-limit-z = <3>; + st,max-limit-x = <3>; + st,max-limit-y = <32>; + st,max-limit-z = <32>; + }; +}; diff --git a/arch/arm/boot/dts/omap3-gta04a4.dts b/arch/arm/boot/dts/omap3-gta04a4.dts new file mode 100644 index 000000000000..c918bb1f0529 --- /dev/null +++ b/arch/arm/boot/dts/omap3-gta04a4.dts @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2014 Marek Belisko <marek@goldelico.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "omap3-gta04.dtsi" + +/ { + model = "Goldelico GTA04A4"; +}; diff --git a/arch/arm/boot/dts/omap3-gta04a5.dts b/arch/arm/boot/dts/omap3-gta04a5.dts new file mode 100644 index 000000000000..52b386f6865b --- /dev/null +++ b/arch/arm/boot/dts/omap3-gta04a5.dts @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2014 H. Nikolaus Schaller <hns@goldelico.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "omap3-gta04.dtsi" + +/ { + model = "Goldelico GTA04A5"; + + sound { + ti,jack-det-gpio = <&twl_gpio 2 0>; /* GTA04A5 only */ + }; +}; diff --git a/arch/arm/boot/dts/omap3-ha-common.dtsi b/arch/arm/boot/dts/omap3-ha-common.dtsi new file mode 100644 index 000000000000..bd66545ef954 --- /dev/null +++ b/arch/arm/boot/dts/omap3-ha-common.dtsi @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014 Stefan Roese <sr@denx.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "omap3-tao3530.dtsi" + +/ { + gpio_poweroff { + pinctrl-names = "default"; + pinctrl-0 = <&poweroff_pins>; + + compatible = "gpio-poweroff"; + gpios = <&gpio6 8 GPIO_ACTIVE_LOW>; /* GPIO 168 */ + }; +}; + +&omap3_pmx_core { + sound2_pins: pinmux_sound2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x209e, PIN_OUTPUT | MUX_MODE4) /* gpmc_d8 gpio_44 */ + >; + }; + + led_blue_pins: pinmux_led_blue_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2110, PIN_OUTPUT | MUX_MODE4) /* cam_xclka gpio_96, LED blue */ + >; + }; + + led_green_pins: pinmux_led_green_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2126, PIN_OUTPUT | MUX_MODE4) /* cam_d8 gpio_107, LED green */ + >; + }; + + led_red_pins: pinmux_led_red_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x212e, PIN_OUTPUT_PULLUP | MUX_MODE4) /* cam_xclkb gpio_111, LED red */ + >; + }; + + poweroff_pins: pinmux_poweroff_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT_PULLUP | MUX_MODE4) /* i2c2_scl gpio_168 */ + >; + }; + + powerdown_input_pins: pinmux_powerdown_input_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c0, PIN_INPUT_PULLUP | MUX_MODE4) /* i2c2_sda gpio_183 */ + >; + }; + + fpga_boot0_pins: fpga_boot0_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x211a, PIN_INPUT | MUX_MODE4) /* cam_d2 gpio_101 */ + OMAP3_CORE1_IOPAD(0x211c, PIN_OUTPUT | MUX_MODE4) /* cam_d3 gpio_102 */ + OMAP3_CORE1_IOPAD(0x211e, PIN_OUTPUT | MUX_MODE4) /* cam_d4 gpio_103 */ + OMAP3_CORE1_IOPAD(0x2120, PIN_INPUT_PULLUP | MUX_MODE4) /* cam_d5 gpio_104 */ + >; + }; + + fpga_boot1_pins: fpga_boot1_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE4) /* gpmc_d10 gpio_46 */ + OMAP3_CORE1_IOPAD(0x20a4, PIN_OUTPUT | MUX_MODE4) /* gpmc_d11 gpio_47 */ + OMAP3_CORE1_IOPAD(0x20a6, PIN_OUTPUT | MUX_MODE4) /* gpmc_d12 gpio_48 */ + OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_d13 gpio_49 */ + >; + }; +}; + +/* I2C2: mux'ed with GPIO168 which is connected to nKILL_POWER */ +&i2c2 { + status = "disabled"; +}; + +&i2c3 { + clock-frequency = <100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; +}; diff --git a/arch/arm/boot/dts/omap3-ha-lcd.dts b/arch/arm/boot/dts/omap3-ha-lcd.dts new file mode 100644 index 000000000000..11aa28d73f3a --- /dev/null +++ b/arch/arm/boot/dts/omap3-ha-lcd.dts @@ -0,0 +1,165 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014 Stefan Roese <sr@denx.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "omap3-ha-common.dtsi" + +/ { + model = "TI OMAP3 HEAD acoustics LCD-baseboard with TAO3530 SOM"; + compatible = "headacoustics,omap3-ha-lcd", "technexion,omap3-tao3530", "ti,omap34xx", "ti,omap3"; +}; + +&omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusbb2_pins + &powerdown_input_pins + &fpga_boot0_pins + &fpga_boot1_pins + &led_blue_pins + &led_green_pins + &led_red_pins + &touchscreen_wake_pins + >; + + touchscreen_irq_pins: pinmux_touchscreen_irq_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio_136, Touchscreen IRQ */ + >; + }; + + touchscreen_wake_pins: pinmux_touchscreen_wake_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x212c, PIN_OUTPUT_PULLUP | MUX_MODE4) /* gpio_110, Touchscreen Wake */ + >; + }; + + dss_dpi_pins: pinmux_dss_dpi_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ + OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ + OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ + OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ + OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ + OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ + OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ + OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ + OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ + OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ + OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ + >; + }; + + lte430_pins: pinmux_lte430_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */ + >; + }; + + backlight_pins: pinmux_backlight_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */ + >; + }; +}; + +/* I2C2: mux'ed with GPIO168 which is connected to nKILL_POWER */ +&i2c2 { + status = "disabled"; +}; + +&i2c3 { + clock-frequency = <100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; +}; + +/* Needed to power the DPI pins */ +&vpll2 { + regulator-always-on; +}; + +&dss { + status = "ok"; + + pinctrl-names = "default"; + pinctrl-0 = <&dss_dpi_pins>; + + port { + dpi_out: endpoint { + remote-endpoint = <&lcd_in>; + data-lines = <24>; + }; + }; +}; + +/ { + aliases { + display0 = &lcd0; + }; + + lcd0: display@0 { + compatible = "panel-dpi"; + label = "lcd"; + + pinctrl-names = "default"; + pinctrl-0 = <<e430_pins>; + enable-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 */ + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + + panel-timing { + clock-frequency = <31250000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <40>; + hback-porch = <86>; + hsync-len = <1>; + vback-porch = <30>; + vfront-porch = <13>; + vsync-len = <3>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + + backlight { + compatible = "gpio-backlight"; + + pinctrl-names = "default"; + pinctrl-0 = <&backlight_pins>; + gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 */ + + default-on; + }; +}; diff --git a/arch/arm/boot/dts/omap3-ha.dts b/arch/arm/boot/dts/omap3-ha.dts new file mode 100644 index 000000000000..fde325688fb9 --- /dev/null +++ b/arch/arm/boot/dts/omap3-ha.dts @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014 Stefan Roese <sr@denx.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "omap3-ha-common.dtsi" + +/ { + model = "TI OMAP3 HEAD acoustics baseboard with TAO3530 SOM"; + compatible = "headacoustics,omap3-ha", "technexion,omap3-tao3530", "ti,omap34xx", "ti,omap3"; +}; + +&omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusbb2_pins + &powerdown_input_pins + &fpga_boot0_pins + &fpga_boot1_pins + &led_blue_pins + &led_green_pins + &led_red_pins + >; +}; diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi index e2d163bf0619..8a63ad2286aa 100644 --- a/arch/arm/boot/dts/omap3-igep.dtsi +++ b/arch/arm/boot/dts/omap3-igep.dtsi @@ -31,18 +31,6 @@ regulator-always-on; }; - lbee1usjyc_vmmc: lbee1usjyc_vmmc { - pinctrl-names = "default"; - pinctrl-0 = <&lbee1usjyc_pins>; - compatible = "regulator-fixed"; - regulator-name = "regulator-lbee1usjyc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; /* gpio_138 WIFI_PDN */ - startup-delay-us = <10000>; - enable-active-high; - vin-supply = <&vdd33>; - }; }; &omap3_pmx_core { @@ -53,13 +41,6 @@ >; }; - uart2_pins: pinmux_uart2_pins { - pinctrl-single,pins = < - 0x14a (PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ - 0x148 (PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ - >; - }; - uart3_pins: pinmux_uart3_pins { pinctrl-single,pins = < 0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */ @@ -67,15 +48,6 @@ >; }; - /* WiFi/BT combo */ - lbee1usjyc_pins: pinmux_lbee1usjyc_pins { - pinctrl-single,pins = < - 0x136 (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 */ - 0x138 (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */ - 0x13a (PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */ - >; - }; - mcbsp2_pins: pinmux_mcbsp2_pins { pinctrl-single,pins = < 0x10c (PIN_INPUT | MUX_MODE0) /* mcbsp2_fsx.mcbsp2_fsx */ @@ -120,13 +92,6 @@ >; }; - i2c2_pins: pinmux_i2c2_pins { - pinctrl-single,pins = < - 0x18e (PIN_INPUT | MUX_MODE0) /* i2c2_scl.i2c2_scl */ - 0x190 (PIN_INPUT | MUX_MODE0) /* i2c2_sda.i2c2_sda */ - >; - }; - i2c3_pins: pinmux_i2c3_pins { pinctrl-single,pins = < 0x192 (PIN_INPUT | MUX_MODE0) /* i2c3_scl.i2c3_scl */ @@ -135,6 +100,55 @@ }; }; +&gpmc { + nand@0,0 { + linux,mtd-name= "micron,mt29c4g96maz"; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + nand-bus-width = <16>; + gpmc,device-width = <2>; + ti,nand-ecc-opt = "bch8"; + + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <44>; + gpmc,cs-wr-off-ns = <44>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <34>; + gpmc,adv-wr-off-ns = <44>; + gpmc,we-off-ns = <40>; + gpmc,oe-off-ns = <54>; + gpmc,access-ns = <64>; + gpmc,rd-cycle-ns = <82>; + gpmc,wr-cycle-ns = <82>; + gpmc,wr-access-ns = <40>; + gpmc,wr-data-mux-bus-ns = <0>; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "SPL"; + reg = <0 0x100000>; + }; + partition@80000 { + label = "U-Boot"; + reg = <0x100000 0x180000>; + }; + partition@1c0000 { + label = "Environment"; + reg = <0x280000 0x100000>; + }; + partition@280000 { + label = "Kernel"; + reg = <0x380000 0x300000>; + }; + partition@780000 { + label = "Filesystem"; + reg = <0x680000 0x1f980000>; + }; + }; +}; + &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; @@ -156,12 +170,6 @@ #include "twl4030.dtsi" #include "twl4030_omap3.dtsi" -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_pins>; - clock-frequency = <400000>; -}; - &i2c3 { pinctrl-names = "default"; pinctrl-0 = <&i2c3_pins>; @@ -181,14 +189,6 @@ bus-width = <4>; }; -&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; - vmmc-supply = <&lbee1usjyc_vmmc>; - bus-width = <4>; - non-removable; -}; - &mmc3 { status = "disabled"; }; @@ -198,11 +198,6 @@ pinctrl-0 = <&uart1_pins>; }; -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&uart2_pins>; -}; - &uart3 { pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; diff --git a/arch/arm/boot/dts/omap3-igep0020-common.dtsi b/arch/arm/boot/dts/omap3-igep0020-common.dtsi new file mode 100644 index 000000000000..e458c2185e3c --- /dev/null +++ b/arch/arm/boot/dts/omap3-igep0020-common.dtsi @@ -0,0 +1,246 @@ +/* + * Common Device Tree Source for IGEPv2 + * + * Copyright (C) 2014 Javier Martinez Canillas <javier@collabora.co.uk> + * Copyright (C) 2014 Enric Balletbo i Serra <eballetbo@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "omap3-igep.dtsi" +#include "omap-gpmc-smsc9221.dtsi" + +/ { + + leds { + pinctrl-names = "default"; + pinctrl-0 = <&leds_pins>; + compatible = "gpio-leds"; + + boot { + label = "omap3:green:boot"; + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + user0 { + label = "omap3:red:user0"; + gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + user1 { + label = "omap3:red:user1"; + gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + user2 { + label = "omap3:green:user1"; + gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; + }; + }; + + /* HS USB Port 1 Power */ + hsusb1_power: hsusb1_power_reg { + compatible = "regulator-fixed"; + regulator-name = "hsusb1_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* GPIO LEDA */ + startup-delay-us = <70000>; + }; + + /* HS USB Host PHY on PORT 1 */ + hsusb1_phy: hsusb1_phy { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */ + vcc-supply = <&hsusb1_power>; + }; + + tfp410: encoder@0 { + compatible = "ti,tfp410"; + powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tfp410_in: endpoint@0 { + remote-endpoint = <&dpi_out>; + }; + }; + + port@1 { + reg = <1>; + + tfp410_out: endpoint@0 { + remote-endpoint = <&dvi_connector_in>; + }; + }; + }; + }; + + dvi0: connector@0 { + compatible = "dvi-connector"; + label = "dvi"; + + digital; + + ddc-i2c-bus = <&i2c3>; + + port { + dvi_connector_in: endpoint { + remote-endpoint = <&tfp410_out>; + }; + }; + }; +}; + +&omap3_pmx_core { + pinctrl-names = "default"; + pinctrl-0 = < + &tfp410_pins + &dss_dpi_pins + >; + + tfp410_pins: pinmux_tfp410_pins { + pinctrl-single,pins = < + 0x196 (PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ + >; + }; + + dss_dpi_pins: pinmux_dss_dpi_pins { + pinctrl-single,pins = < + 0x0a4 (PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + 0x0a6 (PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + 0x0a8 (PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + 0x0aa (PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + 0x0ac (PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ + 0x0ae (PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ + 0x0b0 (PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ + 0x0b2 (PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ + 0x0b4 (PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ + 0x0b6 (PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ + 0x0b8 (PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + 0x0ba (PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + 0x0bc (PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + 0x0be (PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + 0x0c0 (PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + 0x0c2 (PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + 0x0c4 (PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + 0x0c6 (PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + 0x0c8 (PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + 0x0ca (PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + 0x0cc (PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ + 0x0ce (PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + 0x0d0 (PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ + 0x0d2 (PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ + 0x0d4 (PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ + 0x0d6 (PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ + 0x0d8 (PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ + 0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ + >; + }; + + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */ + OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/ + OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ + OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ + >; + }; +}; + +&omap3_pmx_core2 { + pinctrl-names = "default"; + pinctrl-0 = < + &hsusbb1_pins + >; + + hsusbb1_pins: pinmux_hsusbb1_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */ + OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */ + OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d8.hsusb1_dir */ + OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d9.hsusb1_nxt */ + OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d0.hsusb1_data0 */ + OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d1.hsusb1_data1 */ + OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d2.hsusb1_data2 */ + OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d3.hsusb1_data7 */ + OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d4.hsusb1_data4 */ + OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d5.hsusb1_data5 */ + OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d6.hsusb1_data6 */ + OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */ + >; + }; + + leds_pins: pinmux_leds_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25f4, PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */ + OMAP3630_CORE2_IOPAD(0x25f6, PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */ + OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */ + >; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + + /* + * Display monitor features are burnt in the EEPROM + * as EDID data. + */ + eeprom@50 { + compatible = "ti,eeprom"; + reg = <0x50>; + }; +}; + +&gpmc { + ranges = <0 0 0x00000000 0x20000000>, + <5 0 0x2c000000 0x01000000>; + + ethernet@gpmc { + pinctrl-names = "default"; + pinctrl-0 = <&smsc9221_pins>; + reg = <5 0 0xff>; + interrupt-parent = <&gpio6>; + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; + +&usbhshost { + port1-mode = "ehci-phy"; +}; + +&usbhsehci { + phys = <&hsusb1_phy>; +}; + +&vpll2 { + /* Needed for DSS */ + regulator-name = "vdds_dsi"; +}; + +&dss { + status = "ok"; + + port { + dpi_out: endpoint { + remote-endpoint = <&tfp410_in>; + data-lines = <24>; + }; + }; +}; diff --git a/arch/arm/boot/dts/omap3-igep0020-rev-f.dts b/arch/arm/boot/dts/omap3-igep0020-rev-f.dts new file mode 100644 index 000000000000..cc8bd0cd8cf8 --- /dev/null +++ b/arch/arm/boot/dts/omap3-igep0020-rev-f.dts @@ -0,0 +1,45 @@ +/* + * Device Tree Source for IGEPv2 Rev. F (TI OMAP AM/DM37x) + * + * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk> + * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "omap3-igep0020-common.dtsi" + +/ { + model = "IGEPv2 Rev. F (TI OMAP AM/DM37x)"; + compatible = "isee,omap3-igep0020-rev-f", "ti,omap36xx", "ti,omap3"; + + /* Regulator to trigger the WL_EN signal of the Wifi module */ + lbep5clwmc_wlen: regulator-lbep5clwmc-wlen { + compatible = "regulator-fixed"; + regulator-name = "regulator-lbep5clwmc-wlen"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 - WL_EN */ + enable-active-high; + }; +}; + +&omap3_pmx_core { + lbep5clwmc_pins: pinmux_lbep5clwmc_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT | MUX_MODE4) /* mcspi1_cs3.gpio_177 - W_IRQ */ + OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - BT_EN */ + OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - WL_EN */ + >; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins &lbep5clwmc_pins>; + vmmc-supply = <&lbep5clwmc_wlen>; + bus-width = <4>; + non-removable; +}; diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts index b22caaaf774b..fea7f7edb45d 100644 --- a/arch/arm/boot/dts/omap3-igep0020.dts +++ b/arch/arm/boot/dts/omap3-igep0020.dts @@ -1,5 +1,5 @@ /* - * Device Tree Source for IGEPv2 Rev. (TI OMAP AM/DM37x) + * Device Tree Source for IGEPv2 Rev. C (TI OMAP AM/DM37x) * * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk> * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com> @@ -9,272 +9,59 @@ * published by the Free Software Foundation. */ -#include "omap3-igep.dtsi" -#include "omap-gpmc-smsc9221.dtsi" +#include "omap3-igep0020-common.dtsi" / { - model = "IGEPv2 (TI OMAP AM/DM37x)"; + model = "IGEPv2 Rev. C (TI OMAP AM/DM37x)"; compatible = "isee,omap3-igep0020", "ti,omap36xx", "ti,omap3"; - leds { - pinctrl-names = "default"; - pinctrl-0 = <&leds_pins>; - compatible = "gpio-leds"; - - boot { - label = "omap3:green:boot"; - gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; - default-state = "on"; - }; - - user0 { - label = "omap3:red:user0"; - gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - user1 { - label = "omap3:red:user1"; - gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; - default-state = "off"; - }; - - user2 { - label = "omap3:green:user1"; - gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; - }; + /* Regulator to trigger the WIFI_PDN signal of the Wifi module */ + lbee1usjyc_pdn: lbee1usjyc_pdn { + compatible = "regulator-fixed"; + regulator-name = "regulator-lbee1usjyc-pdn"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; /* gpio_138 - WIFI_PDN */ + startup-delay-us = <10000>; + enable-active-high; }; - /* HS USB Port 1 Power */ - hsusb1_power: hsusb1_power_reg { - compatible = "regulator-fixed"; - regulator-name = "hsusb1_vbus"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* GPIO LEDA */ - startup-delay-us = <70000>; - }; - - /* HS USB Host PHY on PORT 1 */ - hsusb1_phy: hsusb1_phy { - compatible = "usb-nop-xceiv"; - reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */ - vcc-supply = <&hsusb1_power>; - }; - - tfp410: encoder@0 { - compatible = "ti,tfp410"; - powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - tfp410_in: endpoint@0 { - remote-endpoint = <&dpi_out>; - }; - }; - - port@1 { - reg = <1>; - - tfp410_out: endpoint@0 { - remote-endpoint = <&dvi_connector_in>; - }; - }; - }; - }; - - dvi0: connector@0 { - compatible = "dvi-connector"; - label = "dvi"; - - digital; - - ddc-i2c-bus = <&i2c3>; - - port { - dvi_connector_in: endpoint { - remote-endpoint = <&tfp410_out>; - }; - }; + /* Regulator to trigger the RESET_N_W signal of the Wifi module */ + lbee1usjyc_reset_n_w: lbee1usjyc_reset_n_w { + compatible = "regulator-fixed"; + regulator-name = "regulator-lbee1usjyc-reset-n-w"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 - RESET_N_W */ + enable-active-high; }; }; &omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = < - &tfp410_pins - &dss_dpi_pins - >; - - tfp410_pins: pinmux_tfp410_pins { + lbee1usjyc_pins: pinmux_lbee1usjyc_pins { pinctrl-single,pins = < - 0x196 (PIN_OUTPUT | MUX_MODE4) /* hdq_sio.gpio_170 */ + OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - RESET_N_W */ + OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 - WIFI_PDN */ + OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - RST_N_B */ >; }; - dss_dpi_pins: pinmux_dss_dpi_pins { + uart2_pins: pinmux_uart2_pins { pinctrl-single,pins = < - 0x0a4 (PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ - 0x0a6 (PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ - 0x0a8 (PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ - 0x0aa (PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ - 0x0ac (PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ - 0x0ae (PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ - 0x0b0 (PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ - 0x0b2 (PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ - 0x0b4 (PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ - 0x0b6 (PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ - 0x0b8 (PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ - 0x0ba (PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ - 0x0bc (PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ - 0x0be (PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ - 0x0c0 (PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ - 0x0c2 (PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ - 0x0c4 (PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ - 0x0c6 (PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ - 0x0c8 (PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ - 0x0ca (PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ - 0x0cc (PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ - 0x0ce (PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ - 0x0d0 (PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ - 0x0d2 (PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ - 0x0d4 (PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ - 0x0d6 (PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ - 0x0d8 (PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ - 0x0da (PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ + OMAP3_CORE1_IOPAD(0x2174, PIN_INPUT | MUX_MODE0) /* uart2_cts.uart2_cts */ + OMAP3_CORE1_IOPAD(0x2176, PIN_OUTPUT | MUX_MODE0) /* uart2_rts .uart2_rts*/ + OMAP3_CORE1_IOPAD(0x2178, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */ + OMAP3_CORE1_IOPAD(0x217a, PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */ >; }; }; -&omap3_pmx_core2 { +/* On board Wifi module */ +&mmc2 { pinctrl-names = "default"; - pinctrl-0 = < - &hsusbb1_pins - >; - - hsusbb1_pins: pinmux_hsusbb1_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25da, PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */ - OMAP3630_CORE2_IOPAD(0x25d8, PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */ - OMAP3630_CORE2_IOPAD(0x25ec, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d8.hsusb1_dir */ - OMAP3630_CORE2_IOPAD(0x25ee, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d9.hsusb1_nxt */ - OMAP3630_CORE2_IOPAD(0x25dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d0.hsusb1_data0 */ - OMAP3630_CORE2_IOPAD(0x25de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d1.hsusb1_data1 */ - OMAP3630_CORE2_IOPAD(0x25e0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d2.hsusb1_data2 */ - OMAP3630_CORE2_IOPAD(0x25e2, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d3.hsusb1_data7 */ - OMAP3630_CORE2_IOPAD(0x25e4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d4.hsusb1_data4 */ - OMAP3630_CORE2_IOPAD(0x25e6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d5.hsusb1_data5 */ - OMAP3630_CORE2_IOPAD(0x25e8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d6.hsusb1_data6 */ - OMAP3630_CORE2_IOPAD(0x25ea, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */ - >; - }; - - leds_pins: pinmux_leds_pins { - pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25f4, PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */ - OMAP3630_CORE2_IOPAD(0x25f6, PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */ - OMAP3630_CORE2_IOPAD(0x25f8, PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */ - >; - }; -}; - -&i2c3 { - clock-frequency = <100000>; - - /* - * Display monitor features are burnt in the EEPROM - * as EDID data. - */ - eeprom@50 { - compatible = "ti,eeprom"; - reg = <0x50>; - }; -}; - -&gpmc { - ranges = <0 0 0x00000000 0x20000000>, - <5 0 0x2c000000 0x01000000>; - - nand@0,0 { - linux,mtd-name= "micron,mt29c4g96maz"; - reg = <0 0 0>; - nand-bus-width = <16>; - ti,nand-ecc-opt = "bch8"; - - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "SPL"; - reg = <0 0x100000>; - }; - partition@80000 { - label = "U-Boot"; - reg = <0x100000 0x180000>; - }; - partition@1c0000 { - label = "Environment"; - reg = <0x280000 0x100000>; - }; - partition@280000 { - label = "Kernel"; - reg = <0x380000 0x300000>; - }; - partition@780000 { - label = "Filesystem"; - reg = <0x680000 0x1f980000>; - }; - }; - - ethernet@gpmc { - pinctrl-names = "default"; - pinctrl-0 = <&smsc9221_pins>; - reg = <5 0 0xff>; - interrupt-parent = <&gpio6>; - interrupts = <16 IRQ_TYPE_LEVEL_LOW>; - }; -}; - -&usbhshost { - port1-mode = "ehci-phy"; -}; - -&usbhsehci { - phys = <&hsusb1_phy>; -}; - -&vpll2 { - /* Needed for DSS */ - regulator-name = "vdds_dsi"; -}; - -&dss { - status = "ok"; - - port { - dpi_out: endpoint { - remote-endpoint = <&tfp410_in>; - data-lines = <24>; - }; - }; + pinctrl-0 = <&mmc2_pins &lbee1usjyc_pins>; + vmmc-supply = <&lbee1usjyc_pdn>; + vmmc_aux-supply = <&lbee1usjyc_reset_n_w>; + bus-width = <4>; + non-removable; }; diff --git a/arch/arm/boot/dts/omap3-igep0030-common.dtsi b/arch/arm/boot/dts/omap3-igep0030-common.dtsi new file mode 100644 index 000000000000..0cb1527c39d4 --- /dev/null +++ b/arch/arm/boot/dts/omap3-igep0030-common.dtsi @@ -0,0 +1,60 @@ +/* + * Common Device Tree Source for IGEP COM MODULE + * + * Copyright (C) 2014 Javier Martinez Canillas <javier@collabora.co.uk> + * Copyright (C) 2014 Enric Balletbo i Serra <eballetbo@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "omap3-igep.dtsi" + +/ { + leds: gpio_leds { + compatible = "gpio-leds"; + + user0 { + label = "omap3:red:user0"; + gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */ + default-state = "off"; + }; + + user1 { + label = "omap3:green:user1"; + gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; /* LEDB */ + default-state = "off"; + }; + + user2 { + label = "omap3:red:user1"; + gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; /* gpio_16 */ + default-state = "off"; + }; + }; +}; + +&omap3_pmx_core { + uart2_pins: pinmux_uart2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x216c, PIN_INPUT | MUX_MODE1) /* mcbsp3_dx.uart2_cts */ + OMAP3_CORE1_IOPAD(0x216e, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_dr.uart2_rts */ + OMAP3_CORE1_IOPAD(0x2170, PIN_OUTPUT | MUX_MODE1) /* mcbsp3_clk.uart2_tx */ + OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE1) /* mcbsp3_fsx.uart2_rx */ + >; + }; +}; + +&omap3_pmx_core2 { + leds_core2_pins: pinmux_leds_core2_pins { + pinctrl-single,pins = < + OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */ + >; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; +}; diff --git a/arch/arm/boot/dts/omap3-igep0030-rev-g.dts b/arch/arm/boot/dts/omap3-igep0030-rev-g.dts new file mode 100644 index 000000000000..9326b282c94a --- /dev/null +++ b/arch/arm/boot/dts/omap3-igep0030-rev-g.dts @@ -0,0 +1,67 @@ +/* + * Device Tree Source for IGEP COM MODULE Rev. G (TI OMAP AM/DM37x) + * + * Copyright (C) 2014 Javier Martinez Canillas <javier@collabora.co.uk> + * Copyright (C) 2014 Enric Balletbo i Serra <eballetbo@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "omap3-igep0030-common.dtsi" + +/ { + model = "IGEP COM MODULE Rev. G (TI OMAP AM/DM37x)"; + compatible = "isee,omap3-igep0030-rev-g", "ti,omap36xx", "ti,omap3"; + + /* Regulator to trigger the WL_EN signal of the Wifi module */ + lbep5clwmc_wlen: regulator-lbep5clwmc-wlen { + compatible = "regulator-fixed"; + regulator-name = "regulator-lbep5clwmc-wlen"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 - WL_EN */ + enable-active-high; + }; +}; + +&omap3_pmx_core { + lbep5clwmc_pins: pinmux_lbep5clwmc_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2164, PIN_INPUT | MUX_MODE4) /* sdmmc2_dat4.gpio_136 - W_IRQ */ + OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - BT_EN */ + OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - WL_EN */ + >; + }; + + leds_pins: pinmux_leds_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21be, PIN_OUTPUT | MUX_MODE4) /* i2c2_scl.gpio_168 */ + >; + }; + +}; + +&i2c2 { + status = "disabled"; +}; + +&leds { + pinctrl-names = "default"; + pinctrl-0 = <&leds_pins &leds_core2_pins>; + + boot { + label = "omap3:green:boot"; + gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; +}; + +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins &lbep5clwmc_pins>; + vmmc-supply = <&lbep5clwmc_wlen>; + bus-width = <4>; + non-removable; +}; diff --git a/arch/arm/boot/dts/omap3-igep0030.dts b/arch/arm/boot/dts/omap3-igep0030.dts index 2793749eb1ba..8150f47ccdf5 100644 --- a/arch/arm/boot/dts/omap3-igep0030.dts +++ b/arch/arm/boot/dts/omap3-igep0030.dts @@ -1,5 +1,5 @@ /* - * Device Tree Source for IGEP COM MODULE (TI OMAP AM/DM37x) + * Device Tree Source for IGEP COM MODULE Rev. E (TI OMAP AM/DM37x) * * Copyright (C) 2012 Javier Martinez Canillas <javier@collabora.co.uk> * Copyright (C) 2012 Enric Balletbo i Serra <eballetbo@gmail.com> @@ -9,97 +9,62 @@ * published by the Free Software Foundation. */ -#include "omap3-igep.dtsi" +#include "omap3-igep0030-common.dtsi" / { - model = "IGEP COM MODULE (TI OMAP AM/DM37x)"; + model = "IGEP COM MODULE Rev. E (TI OMAP AM/DM37x)"; compatible = "isee,omap3-igep0030", "ti,omap36xx", "ti,omap3"; - leds { - pinctrl-names = "default"; - pinctrl-0 = <&leds_pins>; - compatible = "gpio-leds"; - - boot { - label = "omap3:green:boot"; - gpios = <&twl_gpio 13 GPIO_ACTIVE_LOW>; - default-state = "on"; - }; - - user0 { - label = "omap3:red:user0"; - gpios = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* LEDA */ - default-state = "off"; - }; - - user1 { - label = "omap3:green:user1"; - gpios = <&twl_gpio 19 GPIO_ACTIVE_LOW>; /* LEDB */ - default-state = "off"; - }; + /* Regulator to trigger the WIFI_PDN signal of the Wifi module */ + lbee1usjyc_pdn: lbee1usjyc_pdn { + compatible = "regulator-fixed"; + regulator-name = "regulator-lbee1usjyc-pdn"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>; /* gpio_138 - WIFI_PDN */ + startup-delay-us = <10000>; + enable-active-high; + }; - user2 { - label = "omap3:red:user1"; - gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; - default-state = "off"; - }; + /* Regulator to trigger the RESET_N_W signal of the Wifi module */ + lbee1usjyc_reset_n_w: lbee1usjyc_reset_n_w { + compatible = "regulator-fixed"; + regulator-name = "regulator-lbee1usjyc-reset-n-w"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 - RESET_N_W */ + enable-active-high; }; }; -&omap3_pmx_core2 { - leds_pins: pinmux_leds_pins { +&omap3_pmx_core { + lbee1usjyc_pins: pinmux_lbee1usjyc_pins { pinctrl-single,pins = < - OMAP3630_CORE2_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */ + OMAP3_CORE1_IOPAD(0x2166, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat5.gpio_137 - RESET_N_W */ + OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 - WIFI_PDN */ + OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 - RST_N_B */ >; }; }; -&gpmc { - ranges = <0 0 0x00000000 0x20000000>; - - nand@0,0 { - linux,mtd-name= "micron,mt29c4g96maz"; - reg = <0 0 0>; - nand-bus-width = <16>; - ti,nand-ecc-opt = "bch8"; +&leds { + pinctrl-names = "default"; + pinctrl-0 = <&leds_core2_pins>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-off-ns = <40>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "SPL"; - reg = <0 0x100000>; - }; - partition@80000 { - label = "U-Boot"; - reg = <0x100000 0x180000>; - }; - partition@1c0000 { - label = "Environment"; - reg = <0x280000 0x100000>; - }; - partition@280000 { - label = "Kernel"; - reg = <0x380000 0x300000>; - }; - partition@780000 { - label = "Filesystem"; - reg = <0x680000 0x1f980000>; - }; + boot { + label = "omap3:green:boot"; + gpios = <&twl_gpio 13 GPIO_ACTIVE_LOW>; /* LEDSYNC */ + default-state = "on"; }; }; + +/* On board Wifi module */ +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins &lbee1usjyc_pins>; + vmmc-supply = <&lbee1usjyc_pdn>; + vmmc_aux-supply = <&lbee1usjyc_reset_n_w>; + bus-width = <4>; + non-removable; +}; + diff --git a/arch/arm/boot/dts/omap3-ldp.dts b/arch/arm/boot/dts/omap3-ldp.dts index af272c156e21..b699bc48f242 100644 --- a/arch/arm/boot/dts/omap3-ldp.dts +++ b/arch/arm/boot/dts/omap3-ldp.dts @@ -7,6 +7,7 @@ */ /dts-v1/; +#include <dt-bindings/input/input.h> #include "omap34xx.dtsi" #include "omap-gpmc-smsc911x.dtsi" @@ -101,8 +102,9 @@ nand@0,0 { linux,mtd-name= "micron,nand"; - reg = <0 0 0>; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ nand-bus-width = <16>; + gpmc,device-width = <2>; ti,nand-ecc-opt = "bch8"; gpmc,sync-clk-ps = <0>; @@ -141,7 +143,7 @@ }; partition@2000000 { label = "Filesystem"; - reg = <0x2000000 0xe000000>; + reg = <0x2000000 0x6000000>; }; }; @@ -159,6 +161,11 @@ reg = <0x48>; interrupts = <7>; /* SYS_NIRQ cascaded to intc */ interrupt-parent = <&intc>; + + twl_power: power { + compatible = "ti,twl4030-power-idle"; + ti,use_poweroff; + }; }; }; @@ -258,6 +265,26 @@ }; }; +&twl_keypad { + linux,keymap = <MATRIX_KEY(0, 0, KEY_1) + MATRIX_KEY(0, 1, KEY_2) + MATRIX_KEY(0, 2, KEY_3) + MATRIX_KEY(1, 0, KEY_4) + MATRIX_KEY(1, 1, KEY_5) + MATRIX_KEY(1, 2, KEY_6) + MATRIX_KEY(1, 3, KEY_F5) + MATRIX_KEY(2, 0, KEY_7) + MATRIX_KEY(2, 1, KEY_8) + MATRIX_KEY(2, 2, KEY_9) + MATRIX_KEY(2, 3, KEY_F6) + MATRIX_KEY(3, 0, KEY_F7) + MATRIX_KEY(3, 1, KEY_0) + MATRIX_KEY(3, 2, KEY_F8) + MATRIX_KEY(5, 4, KEY_RESERVED) + MATRIX_KEY(4, 4, KEY_VOLUMEUP) + MATRIX_KEY(5, 5, KEY_VOLUMEDOWN)>; +}; + &uart3 { interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; }; diff --git a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi index d97308896f0c..e81fb651d5d0 100644 --- a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi +++ b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi @@ -363,7 +363,7 @@ <7 0 0x15000000 0x01000000>; nand@0,0 { - reg = <0 0 0x1000000>; + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ nand-bus-width = <16>; ti,nand-ecc-opt = "bch8"; /* no elm on omap3 */ diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index 4361777a08d8..53f3ca064140 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -115,6 +115,12 @@ eci-switch-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* 182 */ speaker-amplifier-gpios = <&twl_gpio 7 GPIO_ACTIVE_HIGH>; }; + + battery: n900-battery { + compatible = "nokia,n900-battery"; + io-channels = <&twl_madc 0>, <&twl_madc 4>, <&twl_madc 12>; + io-channel-names = "temp", "bsi", "vbat"; + }; }; &omap3_pmx_core { @@ -134,24 +140,59 @@ >; }; + ethernet_pins: pinmux_ethernet_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20b4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* gpmc_ncs3.gpio_54 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE4) /* dss_data16.gpio_86 */ + OMAP3_CORE1_IOPAD(0x219c, PIN_OUTPUT | MUX_MODE4) /* uart3_rts_sd.gpio_164 */ + >; + }; + + gpmc_pins: pinmux_gpmc_pins { + pinctrl-single,pins = < + + /* address lines */ + OMAP3_CORE1_IOPAD(0x207a, PIN_OUTPUT | MUX_MODE0) /* gpmc_a1.gpmc_a1 */ + OMAP3_CORE1_IOPAD(0x207c, PIN_OUTPUT | MUX_MODE0) /* gpmc_a2.gpmc_a2 */ + OMAP3_CORE1_IOPAD(0x207e, PIN_OUTPUT | MUX_MODE0) /* gpmc_a3.gpmc_a3 */ + + /* data lines, gpmc_d0..d7 not muxable according to TRM */ + OMAP3_CORE1_IOPAD(0x209e, PIN_INPUT | MUX_MODE0) /* gpmc_d8.gpmc_d8 */ + OMAP3_CORE1_IOPAD(0x20a0, PIN_INPUT | MUX_MODE0) /* gpmc_d9.gpmc_d9 */ + OMAP3_CORE1_IOPAD(0x20a2, PIN_INPUT | MUX_MODE0) /* gpmc_d10.gpmc_d10 */ + OMAP3_CORE1_IOPAD(0x20a4, PIN_INPUT | MUX_MODE0) /* gpmc_d11.gpmc_d11 */ + OMAP3_CORE1_IOPAD(0x20a6, PIN_INPUT | MUX_MODE0) /* gpmc_d12.gpmc_d12 */ + OMAP3_CORE1_IOPAD(0x20a8, PIN_INPUT | MUX_MODE0) /* gpmc_d13.gpmc_d13 */ + OMAP3_CORE1_IOPAD(0x20aa, PIN_INPUT | MUX_MODE0) /* gpmc_d14.gpmc_d14 */ + OMAP3_CORE1_IOPAD(0x20ac, PIN_INPUT | MUX_MODE0) /* gpmc_d15.gpmc_d15 */ + + /* + * gpmc_ncs0, gpmc_nadv_ale, gpmc_noe, gpmc_nwe, gpmc_wait0 not muxable + * according to TRM. OneNAND seems to require PIN_INPUT on clock. + */ + OMAP3_CORE1_IOPAD(0x20b0, PIN_OUTPUT | MUX_MODE0) /* gpmc_ncs1.gpmc_ncs1 */ + OMAP3_CORE1_IOPAD(0x20be, PIN_INPUT | MUX_MODE0) /* gpmc_clk.gpmc_clk */ + >; + }; + i2c1_pins: pinmux_i2c1_pins { pinctrl-single,pins = < - 0x18a (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */ - 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */ + 0x18a (PIN_INPUT | MUX_MODE0) /* i2c1_scl */ + 0x18c (PIN_INPUT | MUX_MODE0) /* i2c1_sda */ >; }; i2c2_pins: pinmux_i2c2_pins { pinctrl-single,pins = < - 0x18e (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */ - 0x190 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */ + 0x18e (PIN_INPUT | MUX_MODE0) /* i2c2_scl */ + 0x190 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */ >; }; i2c3_pins: pinmux_i2c3_pins { pinctrl-single,pins = < - 0x192 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ - 0x194 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ + 0x192 (PIN_INPUT | MUX_MODE0) /* i2c3_scl */ + 0x194 (PIN_INPUT | MUX_MODE0) /* i2c3_sda */ >; }; @@ -532,6 +573,16 @@ power-gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>; /* 98 */ }; + si4713: si4713@63 { + compatible = "silabs,si4713"; + reg = <0x63>; + + interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_FALLING>; /* 53 */ + reset-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; /* 163 */ + vio-supply = <&vio>; + vdd-supply = <&vaux1>; + }; + bq24150a: bq24150a@6b { compatible = "ti,bq24150a"; reg = <0x6b>; @@ -577,14 +628,16 @@ }; &gpmc { - ranges = <0 0 0x04000000 0x10000000>; /* 256MB */ - - /* gpio-irq for dma: 65 */ + ranges = <0 0 0x01000000 0x01000000>, /* 16 MB for OneNAND */ + <1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */ + pinctrl-names = "default"; + pinctrl-0 = <&gpmc_pins>; + /* sys_ndmareq1 could be used by the driver, not as gpio65 though */ onenand@0,0 { #address-cells = <1>; #size-cells = <1>; - reg = <0 0 0x10000000>; + reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ gpmc,sync-read; gpmc,sync-write; @@ -646,6 +699,43 @@ reg = <0x004c0000 0x0fb40000>; }; }; + + ethernet@gpmc { + compatible = "smsc,lan91c94"; + + status = "disabled"; + + interrupt-parent = <&gpio2>; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */ + reg = <1 0x300 0xf>; /* 16 byte IO range at offset 0x300 */ + bank-width = <2>; + pinctrl-names = "default"; + pinctrl-0 = <ðernet_pins>; + power-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* gpio86 */ + reset-gpios = <&gpio6 4 GPIO_ACTIVE_HIGH>; /* gpio164 */ + gpmc,device-width = <2>; + gpmc,sync-clk-ps = <0>; + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <48>; + gpmc,cs-wr-off-ns = <24>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <0>; + gpmc,adv-wr-off-ns = <0>; + gpmc,we-on-ns = <12>; + gpmc,we-off-ns = <18>; + gpmc,oe-on-ns = <12>; + gpmc,oe-off-ns = <48>; + gpmc,page-burst-access-ns = <0>; + gpmc,access-ns = <42>; + gpmc,rd-cycle-ns = <180>; + gpmc,wr-cycle-ns = <180>; + gpmc,bus-turnaround-ns = <0>; + gpmc,cycle2cycle-delay-ns = <0>; + gpmc,wait-monitoring-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-access-ns = <0>; + gpmc,wr-data-mux-bus-ns = <12>; + }; }; &mcspi1 { diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi index 70addcba37c5..1e49dfe7e212 100644 --- a/arch/arm/boot/dts/omap3-n950-n9.dtsi +++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi @@ -115,12 +115,12 @@ }; &gpmc { - ranges = <0 0 0x04000000 0x20000000>; + ranges = <0 0 0x04000000 0x1000000>; /* CS0: 16MB for OneNAND */ onenand@0,0 { #address-cells = <1>; #size-cells = <1>; - reg = <0 0 0x20000000>; + reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */ gpmc,sync-read; gpmc,sync-write; diff --git a/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi b/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi index 5831bcc52966..520453d95704 100644 --- a/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi +++ b/arch/arm/boot/dts/omap3-overo-common-peripherals.dtsi @@ -36,8 +36,8 @@ uart3_pins: pinmux_uart3_pins { pinctrl-single,pins = < - OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ - OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ + OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ + OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ >; }; }; @@ -88,6 +88,7 @@ }; &uart3 { + interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; }; diff --git a/arch/arm/boot/dts/omap3-sb-t35.dtsi b/arch/arm/boot/dts/omap3-sb-t35.dtsi index d59e3de1441e..827f614261f6 100644 --- a/arch/arm/boot/dts/omap3-sb-t35.dtsi +++ b/arch/arm/boot/dts/omap3-sb-t35.dtsi @@ -2,6 +2,59 @@ * Common support for CompuLab SB-T35 used on SBC-T3530, SBC-T3517 and SBC-T3730 */ +/ { + tfp410: encoder@0 { + compatible = "ti,tfp410"; + + powerdown-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>; /* gpio_54 */ + + pinctrl-names = "default"; + pinctrl-0 = <&tfp410_pins>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tfp410_in: endpoint@0 { + remote-endpoint = <&dpi_out>; + }; + }; + + port@1 { + reg = <1>; + + tfp410_out: endpoint@0 { + remote-endpoint = <&dvi_connector_in>; + }; + }; + }; + }; + + dvi0: connector@0 { + compatible = "dvi-connector"; + label = "dvi"; + + port { + dvi_connector_in: endpoint { + remote-endpoint = <&tfp410_out>; + }; + }; + }; + + audio_amp: audio_amp { + compatible = "regulator-fixed"; + regulator-name = "audio_amp"; + pinctrl-names = "default"; + pinctrl-0 = <&sb_t35_audio_amp>; + gpio = <&gpio2 29 GPIO_ACTIVE_LOW>; /* gpio_61 */ + enable-active-low; + regulator-always-on; + }; +}; + &omap3_pmx_core { smsc2_pins: pinmux_smsc2_pins { pinctrl-single,pins = < @@ -9,6 +62,38 @@ OMAP3_CORE1_IOPAD(0x20d2, PIN_INPUT_PULLUP | MUX_MODE4) /* gpmc_wait3.gpio_65 */ >; }; + + tfp410_pins: pinmux_tfp410_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20b4, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs3.gpio_54 */ + >; + }; + + i2c3_pins: pinmux_i2c3_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */ + OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */ + >; + }; + + sb_t35_audio_amp: pinmux_sb_t35_audio_amp { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20c8, PIN_OUTPUT | MUX_MODE4) /* gpmc_nbe1.gpio_61 */ + >; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + + clock-frequency = <400000>; + + at24@50 { + compatible = "at24,24c02"; + pagesize = <16>; + reg = <0x50>; + }; }; &gpmc { @@ -22,24 +107,29 @@ interrupts = <1 IRQ_TYPE_LEVEL_LOW>; reg = <4 0 0xff>; bank-width = <2>; - gpmc,mux-add-data; - gpmc,cs-on-ns = <1>; - gpmc,cs-rd-off-ns = <180>; - gpmc,cs-wr-off-ns = <180>; - gpmc,adv-rd-off-ns = <18>; - gpmc,adv-wr-off-ns = <48>; - gpmc,oe-on-ns = <54>; - gpmc,oe-off-ns = <168>; - gpmc,we-on-ns = <54>; - gpmc,we-off-ns = <168>; - gpmc,rd-cycle-ns = <186>; - gpmc,wr-cycle-ns = <186>; - gpmc,access-ns = <144>; - gpmc,page-burst-access-ns = <24>; - gpmc,bus-turnaround-ns = <90>; - gpmc,cycle2cycle-delay-ns = <90>; - gpmc,cycle2cycle-samecsen; - gpmc,cycle2cycle-diffcsen; + gpmc,device-width = <1>; + gpmc,cycle2cycle-samecsen = <1>; + gpmc,cycle2cycle-diffcsen = <1>; + gpmc,cs-on-ns = <5>; + gpmc,cs-rd-off-ns = <150>; + gpmc,cs-wr-off-ns = <150>; + gpmc,adv-on-ns = <0>; + gpmc,adv-rd-off-ns = <15>; + gpmc,adv-wr-off-ns = <40>; + gpmc,oe-on-ns = <45>; + gpmc,oe-off-ns = <140>; + gpmc,we-on-ns = <45>; + gpmc,we-off-ns = <140>; + gpmc,rd-cycle-ns = <155>; + gpmc,wr-cycle-ns = <155>; + gpmc,access-ns = <120>; + gpmc,page-burst-access-ns = <20>; + gpmc,bus-turnaround-ns = <75>; + gpmc,cycle2cycle-delay-ns = <75>; + gpmc,wait-monitoring-ns = <0>; + gpmc,clk-activation-ns = <0>; + gpmc,wr-data-mux-bus-ns = <0>; + gpmc,wr-access-ns = <0>; vddvario-supply = <&vddvario>; vdd33a-supply = <&vdd33a>; reg-io-width = <4>; diff --git a/arch/arm/boot/dts/omap3-sbc-t3517.dts b/arch/arm/boot/dts/omap3-sbc-t3517.dts index 42189b65d393..17986536c61f 100644 --- a/arch/arm/boot/dts/omap3-sbc-t3517.dts +++ b/arch/arm/boot/dts/omap3-sbc-t3517.dts @@ -9,6 +9,11 @@ model = "CompuLab SBC-T3517 with CM-T3517"; compatible = "compulab,omap3-sbc-t3517", "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3"; + aliases { + display0 = &dvi0; + display1 = &tv0; + }; + /* Only one GPMC smsc9220 on SBC-T3517, CM-T3517 uses am35x Ethernet */ vddvario: regulator-vddvario-sb-t35 { compatible = "regulator-fixed"; @@ -54,3 +59,13 @@ wp-gpios = <&gpio2 27 GPIO_ACTIVE_HIGH>; /* gpio_59 */ cd-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>; /* gpio_144 */ }; + +&dss { + port { + dpi_out: endpoint { + remote-endpoint = <&tfp410_in>; + data-lines = <24>; + }; + }; +}; + diff --git a/arch/arm/boot/dts/omap3-sbc-t3530.dts b/arch/arm/boot/dts/omap3-sbc-t3530.dts index bbbeea6b1988..c994f0f7e38a 100644 --- a/arch/arm/boot/dts/omap3-sbc-t3530.dts +++ b/arch/arm/boot/dts/omap3-sbc-t3530.dts @@ -8,6 +8,11 @@ / { model = "CompuLab SBC-T3530 with CM-T3530"; compatible = "compulab,omap3-sbc-t3530", "compulab,omap3-cm-t3530", "ti,omap34xx", "ti,omap3"; + + aliases { + display0 = &dvi0; + display1 = &tv0; + }; }; &omap3_pmx_core { @@ -34,3 +39,13 @@ &mmc1 { cd-gpios = <&twl_gpio 0 GPIO_ACTIVE_HIGH>; }; + +&dss { + port { + dpi_out: endpoint { + remote-endpoint = <&tfp410_in>; + data-lines = <24>; + }; + }; +}; + diff --git a/arch/arm/boot/dts/omap3-sbc-t3730.dts b/arch/arm/boot/dts/omap3-sbc-t3730.dts index 08e4a7086f22..5bdddf29341d 100644 --- a/arch/arm/boot/dts/omap3-sbc-t3730.dts +++ b/arch/arm/boot/dts/omap3-sbc-t3730.dts @@ -8,6 +8,11 @@ / { model = "CompuLab SBC-T3730 with CM-T3730"; compatible = "compulab,omap3-sbc-t3730", "compulab,omap3-cm-t3730", "ti,omap36xx", "ti,omap3"; + + aliases { + display0 = &dvi0; + display1 = &tv0; + }; }; &omap3_pmx_core { @@ -25,3 +30,13 @@ ranges = <5 0 0x2c000000 0x01000000>, <4 0 0x2d000000 0x01000000>; }; + +&dss { + port { + dpi_out: endpoint { + remote-endpoint = <&tfp410_in>; + data-lines = <24>; + }; + }; +}; + diff --git a/arch/arm/boot/dts/omap3-tao3530.dtsi b/arch/arm/boot/dts/omap3-tao3530.dtsi new file mode 100644 index 000000000000..e89820a6776e --- /dev/null +++ b/arch/arm/boot/dts/omap3-tao3530.dtsi @@ -0,0 +1,337 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014 Stefan Roese <sr@denx.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "omap34xx-hs.dtsi" + +/ { + cpus { + cpu@0 { + cpu0-supply = <&vcc>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + /* HS USB Port 2 Power */ + hsusb2_power: hsusb2_power_reg { + compatible = "regulator-fixed"; + regulator-name = "hsusb2_vbus"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&twl_gpio 18 0>; /* GPIO LEDA */ + startup-delay-us = <70000>; + }; + + /* HS USB Host PHY on PORT 2 */ + hsusb2_phy: hsusb2_phy { + compatible = "usb-nop-xceiv"; + reset-gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* gpio_162 */ + vcc-supply = <&hsusb2_power>; + }; + + sound { + compatible = "ti,omap-twl4030"; + ti,model = "omap3beagle"; + + /* McBSP2 is used for onboard sound, same as on beagle */ + ti,mcbsp = <&mcbsp2>; + ti,codec = <&twl_audio>; + }; + + /* Regulator to enable/switch the vcc of the Wifi module */ + mmc2_sdio_poweron: regulator-mmc2-sdio-poweron { + compatible = "regulator-fixed"; + regulator-name = "regulator-mmc2-sdio-poweron"; + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3150000>; + gpio = <&gpio5 29 GPIO_ACTIVE_LOW>; /* gpio_157 */ + enable-active-low; + startup-delay-us = <10000>; + }; +}; + +&omap3_pmx_core { + hsusbb2_pins: pinmux_hsusbb2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x25f0, PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */ + OMAP3_CORE1_IOPAD(0x25f2, PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */ + OMAP3_CORE1_IOPAD(0x25f4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */ + OMAP3_CORE1_IOPAD(0x25f6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */ + OMAP3_CORE1_IOPAD(0x25f8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */ + OMAP3_CORE1_IOPAD(0x25fa, PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */ + OMAP3_CORE1_IOPAD(0x21d4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */ + OMAP3_CORE1_IOPAD(0x21d6, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */ + OMAP3_CORE1_IOPAD(0x21d8, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */ + OMAP3_CORE1_IOPAD(0x21da, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */ + OMAP3_CORE1_IOPAD(0x21dc, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */ + OMAP3_CORE1_IOPAD(0x21de, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */ + >; + }; + + mmc1_pins: pinmux_mmc1_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2144, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ + OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ + OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ + OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ + OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ + OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ + OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */ + OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */ + OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */ + OMAP3_CORE1_IOPAD(0x2156, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */ + >; + }; + + mmc2_pins: pinmux_mmc2_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ + OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ + OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ + OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ + OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ + OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ + >; + }; + + /* wlan GPIO output for WLAN_EN */ + wlan_gpio: pinmux_wlan_gpio { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x218e, PIN_OUTPUT | MUX_MODE4) /* mcbsp1_fsr gpio_157 */ + >; + }; + + uart3_pins: pinmux_uart3_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x219e, PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ + OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ + >; + }; + + i2c3_pins: pinmux_i2c3_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl.i2c3_scl */ + OMAP3_CORE1_IOPAD(0x21c4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda.i2c3_sda */ + >; + }; + + mcspi1_pins: pinmux_mcspi1_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21c8, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */ + OMAP3_CORE1_IOPAD(0x21ca, PIN_OUTPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */ + OMAP3_CORE1_IOPAD(0x21cc, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */ + OMAP3_CORE1_IOPAD(0x21ce, PIN_OUTPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */ + >; + }; + + mcspi3_pins: pinmux_mcspi3_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x25dc, PIN_OUTPUT | MUX_MODE1) /* etk_d0.mcspi3_simo gpio14 INPUT | MODE1 */ + OMAP3_CORE1_IOPAD(0x25de, PIN_INPUT_PULLUP | MUX_MODE1) /* etk_d1.mcspi3_somi gpio15 INPUT | MODE1 */ + OMAP3_CORE1_IOPAD(0x25e0, PIN_OUTPUT | MUX_MODE1) /* etk_d2.mcspi3_cs0 gpio16 INPUT | MODE1 */ + OMAP3_CORE1_IOPAD(0x25e2, PIN_INPUT | MUX_MODE1) /* etk_d3.mcspi3_clk gpio17 INPUT | MODE1 */ + >; + }; + + mcbsp3_pins: pinmux_mcbsp3_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x216c, PIN_OUTPUT | MUX_MODE0) /* mcbsp3_dx.uart2_cts */ + OMAP3_CORE1_IOPAD(0x216e, PIN_INPUT | MUX_MODE0) /* mcbsp3_dr.uart2_rts */ + OMAP3_CORE1_IOPAD(0x2170, PIN_INPUT | MUX_MODE0) /* mcbsp3_clk.uart2_tx */ + OMAP3_CORE1_IOPAD(0x2172, PIN_INPUT | MUX_MODE0) /* mcbsp3_fsx.uart2_rx */ + >; + }; +}; + +/* McBSP1: mux'ed with GPIO158 as clock for HA-DSP */ +&mcbsp1 { + status = "disabled"; +}; + +&mcbsp2 { + status = "okay"; +}; + +&i2c1 { + clock-frequency = <2600000>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + + twl_audio: audio { + compatible = "ti,twl4030-audio"; + codec { + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; +}; + +&mcspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&mcspi1_pins>; + + spidev@0 { + compatible = "spidev"; + spi-max-frequency = <48000000>; + reg = <0>; + spi-cpha; + }; +}; + +&mcspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&mcspi3_pins>; + + spidev@0 { + compatible = "spidev"; + spi-max-frequency = <48000000>; + reg = <0>; + spi-cpha; + }; +}; + +#include "twl4030.dtsi" +#include "twl4030_omap3.dtsi" + +&mmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc1_pins>; + vmmc-supply = <&vmmc1>; + vmmc_aux-supply = <&vsim>; + cd-gpios = <&twl_gpio 0 0>; + bus-width = <8>; +}; + +// WiFi (Marvell 88W8686) on MMC2/SDIO +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; + vmmc-supply = <&mmc2_sdio_poweron>; + non-removable; + bus-width = <4>; + cap-power-off-card; +}; + +&mmc3 { + status = "disabled"; +}; + +&usbhshost { + port2-mode = "ehci-phy"; +}; + +&usbhsehci { + phys = <0 &hsusb2_phy>; +}; + +&twl_gpio { + ti,use-leds; + /* pullups: BIT(1) */ + ti,pullups = <0x000002>; + /* + * pulldowns: + * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13) + * BIT(15), BIT(16), BIT(17) + */ + ti,pulldowns = <0x03a1c4>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; +}; + +&mcbsp3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcbsp3_pins>; +}; + +&gpmc { + ranges = <0 0 0x00000000 0x01000000>; + + nand@0,0 { + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ + nand-bus-width = <16>; + gpmc,device-width = <2>; /* GPMC_DEVWIDTH_16BIT */ + ti,nand-ecc-opt = "sw"; + + gpmc,cs-on-ns = <0>; + gpmc,cs-rd-off-ns = <36>; + gpmc,cs-wr-off-ns = <36>; + gpmc,adv-on-ns = <6>; + gpmc,adv-rd-off-ns = <24>; + gpmc,adv-wr-off-ns = <36>; + gpmc,oe-on-ns = <6>; + gpmc,oe-off-ns = <48>; + gpmc,we-on-ns = <6>; + gpmc,we-off-ns = <30>; + gpmc,rd-cycle-ns = <72>; + gpmc,wr-cycle-ns = <72>; + gpmc,access-ns = <54>; + gpmc,wr-access-ns = <30>; + + #address-cells = <1>; + #size-cells = <1>; + + x-loader@0 { + label = "X-Loader"; + reg = <0 0x80000>; + }; + + bootloaders@80000 { + label = "U-Boot"; + reg = <0x80000 0x1e0000>; + }; + + bootloaders_env@260000 { + label = "U-Boot Env"; + reg = <0x260000 0x20000>; + }; + + kernel@280000 { + label = "Kernel"; + reg = <0x280000 0x400000>; + }; + + filesystem@680000 { + label = "File System"; + reg = <0x680000 0xf980000>; + }; + }; +}; + +&usb_otg_hs { + interface-type = <0>; + usb-phy = <&usb2_phy>; + phys = <&usb2_phy>; + phy-names = "usb2-phy"; + mode = <3>; + power = <50>; +}; + +&vaux2 { + regulator-name = "vdd_ehci"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; +}; diff --git a/arch/arm/boot/dts/omap3-thunder.dts b/arch/arm/boot/dts/omap3-thunder.dts new file mode 100644 index 000000000000..d659515ab9b8 --- /dev/null +++ b/arch/arm/boot/dts/omap3-thunder.dts @@ -0,0 +1,129 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2014 Stefan Roese <sr@denx.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "omap3-tao3530.dtsi" + +/ { + model = "TI OMAP3 Thunder baseboard with TAO3530 SOM"; + compatible = "technexion,omap3-thunder", "technexion,omap3-tao3530", "ti,omap34xx", "ti,omap3"; +}; + +&omap3_pmx_core { + dss_dpi_pins: pinmux_dss_dpi_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ + OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ + OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ + OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ + OMAP3_CORE1_IOPAD(0x20dc, PIN_OUTPUT | MUX_MODE0) /* dss_data0.dss_data0 */ + OMAP3_CORE1_IOPAD(0x20de, PIN_OUTPUT | MUX_MODE0) /* dss_data1.dss_data1 */ + OMAP3_CORE1_IOPAD(0x20e0, PIN_OUTPUT | MUX_MODE0) /* dss_data2.dss_data2 */ + OMAP3_CORE1_IOPAD(0x20e2, PIN_OUTPUT | MUX_MODE0) /* dss_data3.dss_data3 */ + OMAP3_CORE1_IOPAD(0x20e4, PIN_OUTPUT | MUX_MODE0) /* dss_data4.dss_data4 */ + OMAP3_CORE1_IOPAD(0x20e6, PIN_OUTPUT | MUX_MODE0) /* dss_data5.dss_data5 */ + OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ + OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ + OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ + OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ + OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ + OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ + OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ + OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ + OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ + OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ + OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ + OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ + OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE0) /* dss_data18.dss_data18 */ + OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE0) /* dss_data19.dss_data19 */ + OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE0) /* dss_data20.dss_data20 */ + OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE0) /* dss_data21.dss_data21 */ + OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE0) /* dss_data22.dss_data22 */ + OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE0) /* dss_data23.dss_data23 */ + >; + }; + + lte430_pins: pinmux_lte430_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2168, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat6.gpio_138 */ + >; + }; + + backlight_pins: pinmux_backlight_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x216a, PIN_OUTPUT | MUX_MODE4) /* sdmmc2_dat7.gpio_139 */ + >; + }; +}; + +/* Needed to power the DPI pins */ +&vpll2 { + regulator-always-on; +}; + +&dss { + status = "ok"; + + pinctrl-names = "default"; + pinctrl-0 = <&dss_dpi_pins>; + + port { + dpi_out: endpoint { + remote-endpoint = <&lcd_in>; + data-lines = <24>; + }; + }; +}; + +/ { + aliases { + display0 = &lcd0; + }; + + lcd0: display@0 { + compatible = "samsung,lte430wq-f0c", "panel-dpi"; + label = "lcd"; + + pinctrl-names = "default"; + pinctrl-0 = <<e430_pins>; + enable-gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; /* gpio_138 */ + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_out>; + }; + }; + + panel-timing { + clock-frequency = <9000000>; + hactive = <480>; + vactive = <272>; + hfront-porch = <3>; + hback-porch = <2>; + hsync-len = <42>; + vback-porch = <2>; + vfront-porch = <3>; + vsync-len = <11>; + + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + }; + + backlight { + compatible = "gpio-backlight"; + + pinctrl-names = "default"; + pinctrl-0 = <&backlight_pins>; + gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* gpio_139 */ + + default-on; + }; +}; diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi index 575a49bf968d..01b71111bd55 100644 --- a/arch/arm/boot/dts/omap3.dtsi +++ b/arch/arm/boot/dts/omap3.dtsi @@ -79,7 +79,7 @@ * hierarchy. */ ocp { - compatible = "simple-bus"; + compatible = "ti,omap3-l3-smx", "simple-bus"; reg = <0x68000000 0x10000>; interrupts = <9 10>; #address-cells = <1>; @@ -97,6 +97,7 @@ prm: prm@48306000 { compatible = "ti,omap3-prm"; reg = <0x48306000 0x4000>; + interrupts = <11>; prm_clocks: clocks { #address-cells = <1>; @@ -140,10 +141,9 @@ }; intc: interrupt-controller@48200000 { - compatible = "ti,omap2-intc"; + compatible = "ti,omap3-intc"; interrupt-controller; #interrupt-cells = <1>; - ti,intc-size = <96>; reg = <0x48200000 0x1000>; }; @@ -332,8 +332,13 @@ ti,hwmods = "mailbox"; reg = <0x48094000 0x200>; interrupts = <26>; + #mbox-cells = <1>; ti,mbox-num-users = <2>; ti,mbox-num-fifos = <2>; + mbox_dsp: dsp { + ti,mbox-tx = <0 0 0>; + ti,mbox-rx = <1 0 0>; + }; }; mcspi1: spi@48098000 { diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts index 9bad94efe1c8..16b0cdfbee9c 100644 --- a/arch/arm/boot/dts/omap3430-sdp.dts +++ b/arch/arm/boot/dts/omap3430-sdp.dts @@ -51,8 +51,8 @@ &gpmc { ranges = <0 0 0x10000000 0x08000000>, - <1 0 0x28000000 0x08000000>, - <2 0 0x20000000 0x10000000>; + <1 0 0x28000000 0x1000000>, /* CS1: 16MB for NAND */ + <2 0 0x20000000 0x1000000>; /* CS2: 16MB for OneNAND */ nor@0,0 { compatible = "cfi-flash"; @@ -106,7 +106,7 @@ linux,mtd-name= "micron,mt29f1g08abb"; #address-cells = <1>; #size-cells = <1>; - reg = <1 0 0x08000000>; + reg = <1 0 4>; /* CS1, offset 0, IO size 4 */ ti,nand-ecc-opt = "sw"; nand-bus-width = <8>; gpmc,cs-on-ns = <0>; @@ -150,7 +150,7 @@ linux,mtd-name= "samsung,kfm2g16q2m-deb8"; #address-cells = <1>; #size-cells = <1>; - reg = <2 0 0x10000000>; + reg = <2 0 0x20000>; /* CS2, offset 0, IO size 4 */ gpmc,device-width = <2>; gpmc,mux-add-data = <2>; diff --git a/arch/arm/boot/dts/omap4-duovero-parlor.dts b/arch/arm/boot/dts/omap4-duovero-parlor.dts index 6dc84d9f9b4c..1a78f013f37a 100644 --- a/arch/arm/boot/dts/omap4-duovero-parlor.dts +++ b/arch/arm/boot/dts/omap4-duovero-parlor.dts @@ -177,6 +177,7 @@ &hdmi { status = "ok"; + vdda-supply = <&vdac>; pinctrl-names = "default"; pinctrl-0 = <&dss_hdmi_pins>; diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index 8cfa3c8a72b0..150513506c19 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -8,9 +8,6 @@ #include "elpida_ecb240abacn.dtsi" / { - model = "TI OMAP4 PandaBoard"; - compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4"; - memory { device_type = "memory"; reg = <0x80000000 0x40000000>; /* 1 GB */ diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts index 816d1c95b592..2f1dabcc6adf 100644 --- a/arch/arm/boot/dts/omap4-panda-es.dts +++ b/arch/arm/boot/dts/omap4-panda-es.dts @@ -10,6 +10,11 @@ #include "omap4460.dtsi" #include "omap4-panda-common.dtsi" +/ { + model = "TI OMAP4 PandaBoard-ES"; + compatible = "ti,omap4-panda-es", "ti,omap4-panda", "ti,omap4460", "ti,omap4430", "ti,omap4"; +}; + /* Audio routing is differnet between PandaBoard4430 and PandaBoardES */ &sound { ti,model = "PandaBoardES"; diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts index 6189a8b77d7f..a0e28b2e254e 100644 --- a/arch/arm/boot/dts/omap4-panda.dts +++ b/arch/arm/boot/dts/omap4-panda.dts @@ -9,3 +9,8 @@ #include "omap443x.dtsi" #include "omap4-panda-common.dtsi" + +/ { + model = "TI OMAP4 PandaBoard"; + compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4"; +}; diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 69408b53200d..074147cebae4 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -81,6 +81,7 @@ mpu { compatible = "ti,omap4-mpu"; ti,hwmods = "mpu"; + sram = <&ocmcram>; }; dsp { @@ -129,6 +130,7 @@ prm: prm@4a306000 { compatible = "ti,omap4-prm"; reg = <0x4a306000 0x3000>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; prm_clocks: clocks { #address-cells = <1>; @@ -208,6 +210,11 @@ }; }; + ocmcram: ocmcram@40304000 { + compatible = "mmio-sram"; + reg = <0x40304000 0xa000>; /* 40k */ + }; + sdma: dma-controller@4a056000 { compatible = "ti,omap4430-sdma"; reg = <0x4a056000 0x1000>; @@ -654,8 +661,17 @@ reg = <0x4a0f4000 0x200>; interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "mailbox"; + #mbox-cells = <1>; ti,mbox-num-users = <3>; ti,mbox-num-fifos = <8>; + mbox_ipu: mbox_ipu { + ti,mbox-tx = <0 0 0>; + ti,mbox-rx = <1 0 0>; + }; + mbox_dsp: mbox_dsp { + ti,mbox-tx = <3 0 0>; + ti,mbox-rx = <2 0 0>; + }; }; timer1: timer@4a318000 { @@ -880,7 +896,7 @@ reg = <0x58002000 0x1000>; status = "disabled"; ti,hwmods = "dss_rfbi"; - clocks = <&dss_dss_clk>, <&dss_fck>; + clocks = <&dss_dss_clk>, <&l3_div_ck>; clock-names = "fck", "ick"; }; diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi index c821ff5e9b8d..f2c48f09824e 100644 --- a/arch/arm/boot/dts/omap44xx-clocks.dtsi +++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi @@ -1018,14 +1018,6 @@ reg = <0x1120>; }; - dss_fck: dss_fck { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&l3_div_ck>; - ti,bit-shift = <1>; - reg = <0x1120>; - }; - fdif_fck: fdif_fck { #clock-cells = <0>; compatible = "ti,divider-clock"; diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts index 429471aa7a1f..b54b271e153b 100644 --- a/arch/arm/boot/dts/omap5-cm-t54.dts +++ b/arch/arm/boot/dts/omap5-cm-t54.dts @@ -16,6 +16,12 @@ reg = <0x80000000 0x7F000000>; /* 2048 MB */ }; + aliases { + display0 = &hdmi0; + display1 = &dvi0; + display2 = &lcd0; + }; + vmmcsd_fixed: fixed-regulator-mmcsd { compatible = "regulator-fixed"; regulator-name = "vmmcsd_fixed"; @@ -45,6 +51,13 @@ enable-active-high; }; + ads7846reg: ads7846-reg { + compatible = "regulator-fixed"; + regulator-name = "ads7846-reg"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + /* HS USB Host PHY on PORT 2 */ hsusb2_phy: hsusb2_phy { compatible = "usb-nop-xceiv"; @@ -66,6 +79,105 @@ default-state = "off"; }; }; + + lcd0: display { + compatible = "startek,startek-kd050c", "panel-dpi"; + label = "lcd"; + + pinctrl-names = "default"; + pinctrl-0 = <&lcd_pins>; + + enable-gpios = <&gpio8 3 GPIO_ACTIVE_HIGH>; + + panel-timing { + clock-frequency = <33000000>; + hactive = <800>; + vactive = <480>; + hfront-porch = <40>; + hback-porch = <40>; + hsync-len = <43>; + vback-porch = <29>; + vfront-porch = <13>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <1>; + }; + + port { + lcd_in: endpoint { + remote-endpoint = <&dpi_lcd_out>; + }; + }; + }; + + hdmi0: connector@0 { + compatible = "hdmi-connector"; + label = "hdmi"; + + type = "a"; + + pinctrl-names = "default"; + pinctrl-0 = <&hdmi_conn_pins>; + + hpd-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; /* GPIO 193, HPD */ + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_out>; + }; + }; + }; + + tfp410: encoder@0 { + compatible = "ti,tfp410"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + tfp410_in: endpoint@0 { + remote-endpoint = <&dpi_dvi_out>; + }; + }; + + port@1 { + reg = <1>; + + tfp410_out: endpoint@0 { + remote-endpoint = <&dvi_connector_in>; + }; + }; + }; + }; + + dvi0: connector@1 { + compatible = "dvi-connector"; + label = "dvi"; + + digital; + + ddc-i2c-bus = <&i2c2>; + + port { + dvi_connector_in: endpoint { + remote-endpoint = <&tfp410_out>; + }; + }; + }; +}; + +&omap5_pmx_wkup { + + ads7846_pins: pinmux_ads7846_pins { + pinctrl-single,pins = < + 0x02 (PIN_INPUT_PULLDOWN | MUX_MODE6) /* llib_wakereqin.gpio1_wk15 */ + >; + }; }; &omap5_pmx_core { @@ -88,6 +200,13 @@ >; }; + i2c2_pins: pinmux_i2c2_pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x01b8, PIN_INPUT | MUX_MODE0) /* i2c2_scl */ + OMAP5_IOPAD(0x01ba, PIN_INPUT | MUX_MODE0) /* i2c2_sda */ + >; + }; + mmc1_pins: pinmux_mmc1_pins { pinctrl-single,pins = < OMAP5_IOPAD(0x01e2, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_clk */ @@ -127,8 +246,8 @@ wlan_gpios_pins: pinmux_wlan_gpios_pins { pinctrl-single,pins = < - OMAP5_IOPAD(0x019c, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* gpio4_109 */ - OMAP5_IOPAD(0x019e, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* gpio4_110 */ + OMAP5_IOPAD(0x019c, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* abemcpdm_ul_data.gpio4_109 */ + OMAP5_IOPAD(0x019e, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* abemcpdm_dl_data.gpio4_110 */ >; }; @@ -144,6 +263,104 @@ OMAP5_IOPAD(0x00b6, PIN_OUTPUT | MUX_MODE6) /* hsi2_acdata.gpio3_83 */ >; }; + + dss_hdmi_pins: pinmux_dss_hdmi_pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x013c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_cec */ + OMAP5_IOPAD(0x0140, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_scl */ + OMAP5_IOPAD(0x0142, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_sda */ + >; + }; + + lcd_pins: pinmux_lcd_pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x0172, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* timer11_pwm_evt.gpio8_227 */ + >; + }; + + hdmi_conn_pins: pinmux_hdmi_conn_pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x013e, PIN_INPUT | MUX_MODE6) /* hdmi_hpd.gpio7_193 */ + >; + }; + + dss_dpi_pins: pinmux_dss_dpi_pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x0104, PIN_OUTPUT | MUX_MODE3) /* rfbi_data15.dispc_data15 */ + OMAP5_IOPAD(0x0106, PIN_OUTPUT | MUX_MODE3) /* rfbi_data14.dispc_data14 */ + OMAP5_IOPAD(0x0108, PIN_OUTPUT | MUX_MODE3) /* rfbi_data13.dispc_data13 */ + OMAP5_IOPAD(0x010a, PIN_OUTPUT | MUX_MODE3) /* rfbi_data12.dispc_data12 */ + OMAP5_IOPAD(0x010c, PIN_OUTPUT | MUX_MODE3) /* rfbi_data11.dispc_data11 */ + OMAP5_IOPAD(0x010e, PIN_OUTPUT | MUX_MODE3) /* rfbi_data10.dispc_data10 */ + OMAP5_IOPAD(0x0110, PIN_OUTPUT | MUX_MODE3) /* rfbi_data9.dispc_data9 */ + OMAP5_IOPAD(0x0112, PIN_OUTPUT | MUX_MODE3) /* rfbi_data8.dispc_data8 */ + OMAP5_IOPAD(0x0114, PIN_OUTPUT | MUX_MODE3) /* rfbi_data7.dispc_data7 */ + OMAP5_IOPAD(0x0116, PIN_OUTPUT | MUX_MODE3) /* rfbi_data6.dispc_data6 */ + OMAP5_IOPAD(0x0118, PIN_OUTPUT | MUX_MODE3) /* rfbi_data5.dispc_data5 */ + OMAP5_IOPAD(0x011a, PIN_OUTPUT | MUX_MODE3) /* rfbi_data4.dispc_data4 */ + OMAP5_IOPAD(0x011c, PIN_OUTPUT | MUX_MODE3) /* rfbi_data3.dispc_data3 */ + OMAP5_IOPAD(0x011e, PIN_OUTPUT | MUX_MODE3) /* rfbi_data2.dispc_data2 */ + OMAP5_IOPAD(0x0120, PIN_OUTPUT | MUX_MODE3) /* rfbi_data1.dispc_data1 */ + OMAP5_IOPAD(0x0122, PIN_OUTPUT | MUX_MODE3) /* rfbi_data0.dispc_data0 */ + OMAP5_IOPAD(0x0124, PIN_OUTPUT | MUX_MODE3) /* rfbi_we.dispc_vsync */ + OMAP5_IOPAD(0x0126, PIN_OUTPUT | MUX_MODE3) /* rfbi_cs0.dispc_hsync */ + OMAP5_IOPAD(0x0128, PIN_OUTPUT | MUX_MODE3) /* rfbi_a0.dispc_de */ + OMAP5_IOPAD(0x012a, PIN_OUTPUT | MUX_MODE3) /* rfbi_re.dispc_pclk */ + OMAP5_IOPAD(0x012c, PIN_OUTPUT | MUX_MODE3) /* rfbi_hsync0.dispc_data17 */ + OMAP5_IOPAD(0x012e, PIN_OUTPUT | MUX_MODE3) /* rfbi_te_vsync0.dispc_data16 */ + OMAP5_IOPAD(0x0130, PIN_OUTPUT | MUX_MODE3) /* gpio6_182.dispc_data18 */ + OMAP5_IOPAD(0x0132, PIN_OUTPUT | MUX_MODE3) /* gpio6_183.dispc_data19 */ + OMAP5_IOPAD(0x0134, PIN_OUTPUT | MUX_MODE3) /* gpio6_184.dispc_data20 */ + OMAP5_IOPAD(0x0136, PIN_OUTPUT | MUX_MODE3) /* gpio6_185.dispc_data21 */ + OMAP5_IOPAD(0x0138, PIN_OUTPUT | MUX_MODE3) /* gpio6_186.dispc_data22 */ + OMAP5_IOPAD(0x013a, PIN_OUTPUT | MUX_MODE3) /* gpio6_187.dispc_data23 */ + >; + }; + + mcspi2_pins: pinmux_mcspi1_pins { + pinctrl-single,pins = < + OMAP5_IOPAD(0x00fc, PIN_INPUT | MUX_MODE0) /* mcspi2_clk */ + OMAP5_IOPAD(0x00fe, PIN_INPUT | MUX_MODE0) /* mcspi2_simo */ + OMAP5_IOPAD(0x0100, PIN_INPUT | MUX_MODE0) /* mcspi2_somi */ + OMAP5_IOPAD(0x0102, PIN_INPUT | MUX_MODE0) /* mcspi2_cs0 */ + >; + }; +}; + +&mcspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&mcspi2_pins>; + + /* touch controller */ + ads7846@0 { + pinctrl-names = "default"; + pinctrl-0 = <&ads7846_pins>; + + compatible = "ti,ads7846"; + vcc-supply = <&ads7846reg>; + + reg = <0>; /* CS0 */ + spi-max-frequency = <1500000>; + + interrupt-parent = <&gpio1>; + interrupts = <15 0>; /* gpio1_wk15 */ + pendown-gpio = <&gpio1 15 0>; + + + ti,x-min = /bits/ 16 <0x0>; + ti,x-max = /bits/ 16 <0x0fff>; + ti,y-min = /bits/ 16 <0x0>; + ti,y-max = /bits/ 16 <0x0fff>; + + ti,x-plate-ohms = /bits/ 16 <180>; + ti,pressure-max = /bits/ 16 <255>; + + ti,debounce-max = /bits/ 16 <30>; + ti,debounce-tol = /bits/ 16 <10>; + ti,debounce-rep = /bits/ 16 <1>; + + linux,wakeup; + }; }; &mmc1 { @@ -398,6 +615,13 @@ }; }; +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + + clock-frequency = <100000>; +}; + &usbhshost { port2-mode = "ehci-hsic"; port3-mode = "ehci-hsic"; @@ -407,6 +631,50 @@ phys = <0 &hsusb2_phy &hsusb3_phy>; }; +&usb3 { + extcon = <&extcon_usb3>; + vbus-supply = <&smps10_out1_reg>; +}; + &cpu0 { cpu0-supply = <&smps123_reg>; }; + +&dss { + status = "ok"; + + pinctrl-names = "default"; + pinctrl-0 = <&dss_dpi_pins>; + + port { + dpi_dvi_out: endpoint@0 { + remote-endpoint = <&tfp410_in>; + data-lines = <24>; + }; + + dpi_lcd_out: endpoint@1 { + remote-endpoint = <&lcd_in>; + data-lines = <24>; + }; + }; +}; + +&dsi2 { + status = "ok"; + vdd-supply = <&ldo4_reg>; +}; + +&hdmi { + status = "ok"; + vdda-supply = <&ldo4_reg>; + + pinctrl-names = "default"; + pinctrl-0 = <&dss_hdmi_pins>; + + port { + hdmi_out: endpoint { + remote-endpoint = <&hdmi_connector_in>; + lanes = <1 0 3 2 5 4 7 6>; + }; + }; +}; diff --git a/arch/arm/boot/dts/omap5-sbc-t54.dts b/arch/arm/boot/dts/omap5-sbc-t54.dts index aa98fea3f2b3..337bbbc01a35 100644 --- a/arch/arm/boot/dts/omap5-sbc-t54.dts +++ b/arch/arm/boot/dts/omap5-sbc-t54.dts @@ -1,11 +1,11 @@ /* - * Suppport for CompuLab SBC-T54 with CM-T54 + * Suppport for CompuLab CM-T54 on SB-T54 baseboard */ #include "omap5-cm-t54.dts" / { - model = "CompuLab SBC-T54 with CM-T54"; + model = "CompuLab CM-T54 on SB-T54"; compatible = "compulab,omap5-sbc-t54", "compulab,omap5-cm-t54", "ti,omap5"; }; @@ -19,8 +19,8 @@ mmc1_aux_pins: pinmux_mmc1_aux_pins { pinctrl-single,pins = < - OMAP5_IOPAD(0x0174, PIN_INPUT_PULLUP | MUX_MODE6) /* gpio8_228 */ - OMAP5_IOPAD(0x0176, PIN_INPUT_PULLUP | MUX_MODE6) /* gpio8_229 */ + OMAP5_IOPAD(0x0174, PIN_INPUT_PULLUP | MUX_MODE6) /* timer5_pwm_evt.gpio8_228 */ + OMAP5_IOPAD(0x0176, PIN_INPUT_PULLUP | MUX_MODE6) /* timer6_pwm_evt.gpio8_229 */ >; }; }; diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index fc8df1739f39..b321fdf42c9f 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -104,8 +104,9 @@ soc { compatible = "ti,omap-infra"; mpu { - compatible = "ti,omap5-mpu"; + compatible = "ti,omap4-mpu"; ti,hwmods = "mpu"; + sram = <&ocmcram>; }; }; @@ -131,6 +132,7 @@ prm: prm@4ae06000 { compatible = "ti,omap5-prm"; reg = <0x4ae06000 0x3000>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; prm_clocks: clocks { #address-cells = <1>; @@ -187,18 +189,22 @@ }; omap5_pmx_core: pinmux@4a002840 { - compatible = "ti,omap4-padconf", "pinctrl-single"; + compatible = "ti,omap5-padconf", "pinctrl-single"; reg = <0x4a002840 0x01b6>; #address-cells = <1>; #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; pinctrl-single,register-width = <16>; pinctrl-single,function-mask = <0x7fff>; }; omap5_pmx_wkup: pinmux@4ae0c840 { - compatible = "ti,omap4-padconf", "pinctrl-single"; + compatible = "ti,omap5-padconf", "pinctrl-single"; reg = <0x4ae0c840 0x0038>; #address-cells = <1>; #size-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; pinctrl-single,register-width = <16>; pinctrl-single,function-mask = <0x7fff>; }; @@ -219,6 +225,11 @@ }; }; + ocmcram: ocmcram@40300000 { + compatible = "mmio-sram"; + reg = <0x40300000 0x20000>; /* 128k */ + }; + sdma: dma-controller@4a056000 { compatible = "ti,omap4430-sdma"; reg = <0x4a056000 0x1000>; @@ -447,7 +458,7 @@ uart1: serial@4806a000 { compatible = "ti,omap4-uart"; reg = <0x4806a000 0x100>; - interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart1"; clock-frequency = <48000000>; }; @@ -455,7 +466,7 @@ uart2: serial@4806c000 { compatible = "ti,omap4-uart"; reg = <0x4806c000 0x100>; - interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart2"; clock-frequency = <48000000>; }; @@ -463,7 +474,7 @@ uart3: serial@48020000 { compatible = "ti,omap4-uart"; reg = <0x48020000 0x100>; - interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart3"; clock-frequency = <48000000>; }; @@ -471,7 +482,7 @@ uart4: serial@4806e000 { compatible = "ti,omap4-uart"; reg = <0x4806e000 0x100>; - interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart4"; clock-frequency = <48000000>; }; @@ -479,7 +490,7 @@ uart5: serial@48066000 { compatible = "ti,omap4-uart"; reg = <0x48066000 0x100>; - interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart5"; clock-frequency = <48000000>; }; @@ -487,7 +498,7 @@ uart6: serial@48068000 { compatible = "ti,omap4-uart"; reg = <0x48068000 0x100>; - interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + interrupts-extended = <&gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "uart6"; clock-frequency = <48000000>; }; @@ -640,8 +651,17 @@ reg = <0x4a0f4000 0x200>; interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; ti,hwmods = "mailbox"; + #mbox-cells = <1>; ti,mbox-num-users = <3>; ti,mbox-num-fifos = <8>; + mbox_ipu: mbox_ipu { + ti,mbox-tx = <0 0 0>; + ti,mbox-rx = <1 0 0>; + }; + mbox_dsp: mbox_dsp { + ti,mbox-tx = <3 0 0>; + ti,mbox-rx = <2 0 0>; + }; }; timer1: timer@4ae18000 { @@ -945,6 +965,15 @@ clock-names = "fck"; }; + rfbi: encoder@58002000 { + compatible = "ti,omap5-rfbi"; + reg = <0x58002000 0x100>; + status = "disabled"; + ti,hwmods = "dss_rfbi"; + clocks = <&dss_dss_clk>, <&l3_iclk_div>; + clock-names = "fck", "ick"; + }; + dsi1: encoder@58004000 { compatible = "ti,omap5-dsi"; reg = <0x58004000 0x200>, diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi index 963b7e54ab15..1ca1a9aa953f 100644 --- a/arch/arm/boot/dts/prima2.dtsi +++ b/arch/arm/boot/dts/prima2.dtsi @@ -41,6 +41,11 @@ }; }; + arm-pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <29>; + }; + axi { compatible = "simple-bus"; #address-cells = <1>; @@ -132,6 +137,7 @@ reg = <0x90020000 0x10000>; interrupts = <31>; clocks = <&clks 35>; + resets = <&rstc 6>; }; }; @@ -173,6 +179,7 @@ compatible = "sirf,prima2-dspif"; reg = <0xa8000000 0x10000>; interrupts = <9>; + resets = <&rstc 1>; }; gps@a8010000 { @@ -180,6 +187,7 @@ reg = <0xa8010000 0x10000>; interrupts = <7>; clocks = <&clks 9>; + resets = <&rstc 2>; }; dsp@a9000000 { @@ -187,6 +195,7 @@ reg = <0xa9000000 0x1000000>; interrupts = <8>; clocks = <&clks 8>; + resets = <&rstc 0>; }; }; @@ -524,12 +533,36 @@ sirf,function = "sdmmc5"; }; }; + i2s_mclk_pins_a: i2s_mclk@0 { + i2s_mclk { + sirf,pins = "i2smclkgrp"; + sirf,function = "i2s_mclk"; + }; + }; + i2s_ext_clk_input_pins_a: i2s_ext_clk_input@0 { + i2s_ext_clk_input { + sirf,pins = "i2s_ext_clk_inputgrp"; + sirf,function = "i2s_ext_clk_input"; + }; + }; i2s_pins_a: i2s@0 { i2s { sirf,pins = "i2sgrp"; sirf,function = "i2s"; }; }; + i2s_no_din_pins_a: i2s_no_din@0 { + i2s_no_din { + sirf,pins = "i2s_no_dingrp"; + sirf,function = "i2s_no_din"; + }; + }; + i2s_6chn_pins_a: i2s_6chn@0 { + i2s_6chn { + sirf,pins = "i2s_6chngrp"; + sirf,function = "i2s_6chn"; + }; + }; ac97_pins_a: ac97@0 { ac97 { sirf,pins = "ac97grp"; diff --git a/arch/arm/boot/dts/pxa168-aspenite.dts b/arch/arm/boot/dts/pxa168-aspenite.dts index e762facb3fa4..0a988b3fb248 100644 --- a/arch/arm/boot/dts/pxa168-aspenite.dts +++ b/arch/arm/boot/dts/pxa168-aspenite.dts @@ -8,7 +8,7 @@ */ /dts-v1/; -/include/ "pxa168.dtsi" +#include "pxa168.dtsi" / { model = "Marvell PXA168 Aspenite Development Board"; diff --git a/arch/arm/boot/dts/pxa168.dtsi b/arch/arm/boot/dts/pxa168.dtsi index 975dad21ac38..b899e25cbb1b 100644 --- a/arch/arm/boot/dts/pxa168.dtsi +++ b/arch/arm/boot/dts/pxa168.dtsi @@ -7,7 +7,8 @@ * publishhed by the Free Software Foundation. */ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" +#include <dt-bindings/clock/marvell,pxa168.h> / { aliases { @@ -59,6 +60,8 @@ compatible = "mrvl,mmp-uart"; reg = <0xd4017000 0x1000>; interrupts = <27>; + clocks = <&soc_clocks PXA168_CLK_UART0>; + resets = <&soc_clocks PXA168_CLK_UART0>; status = "disabled"; }; @@ -66,6 +69,8 @@ compatible = "mrvl,mmp-uart"; reg = <0xd4018000 0x1000>; interrupts = <28>; + clocks = <&soc_clocks PXA168_CLK_UART1>; + resets = <&soc_clocks PXA168_CLK_UART1>; status = "disabled"; }; @@ -73,6 +78,8 @@ compatible = "mrvl,mmp-uart"; reg = <0xd4026000 0x1000>; interrupts = <29>; + clocks = <&soc_clocks PXA168_CLK_UART2>; + resets = <&soc_clocks PXA168_CLK_UART2>; status = "disabled"; }; @@ -84,6 +91,8 @@ gpio-controller; #gpio-cells = <2>; interrupts = <49>; + clocks = <&soc_clocks PXA168_CLK_GPIO>; + resets = <&soc_clocks PXA168_CLK_GPIO>; interrupt-names = "gpio_mux"; interrupt-controller; #interrupt-cells = <1>; @@ -110,6 +119,8 @@ compatible = "mrvl,mmp-twsi"; reg = <0xd4011000 0x1000>; interrupts = <7>; + clocks = <&soc_clocks PXA168_CLK_TWSI0>; + resets = <&soc_clocks PXA168_CLK_TWSI0>; mrvl,i2c-fast-mode; status = "disabled"; }; @@ -118,6 +129,8 @@ compatible = "mrvl,mmp-twsi"; reg = <0xd4025000 0x1000>; interrupts = <58>; + clocks = <&soc_clocks PXA168_CLK_TWSI1>; + resets = <&soc_clocks PXA168_CLK_TWSI1>; status = "disabled"; }; @@ -126,8 +139,20 @@ reg = <0xd4010000 0x1000>; interrupts = <5 6>; interrupt-names = "rtc 1Hz", "rtc alarm"; + clocks = <&soc_clocks PXA168_CLK_RTC>; + resets = <&soc_clocks PXA168_CLK_RTC>; status = "disabled"; }; }; + + soc_clocks: clocks{ + compatible = "marvell,pxa168-clock"; + reg = <0xd4050000 0x1000>, + <0xd4282800 0x400>, + <0xd4015000 0x1000>; + reg-names = "mpmu", "apmu", "apbc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; }; }; diff --git a/arch/arm/boot/dts/pxa27x.dtsi b/arch/arm/boot/dts/pxa27x.dtsi index a70546945985..80fc5d7e9ef9 100644 --- a/arch/arm/boot/dts/pxa27x.dtsi +++ b/arch/arm/boot/dts/pxa27x.dtsi @@ -1,5 +1,6 @@ /* The pxa3xx skeleton simply augments the 2xx version */ -/include/ "pxa2xx.dtsi" +#include "pxa2xx.dtsi" +#include "dt-bindings/clock/pxa2xx-clock.h" / { model = "Marvell PXA27x familiy SoC"; @@ -35,4 +36,21 @@ #pwm-cells = <1>; }; }; + + clocks { + /* + * The muxing of external clocks/internal dividers for osc* clock + * sources has been hidden under the carpet by now. + */ + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pxa2xx_clks: pxa2xx_clks@41300004 { + compatible = "marvell,pxa-clocks"; + #clock-cells = <1>; + status = "okay"; + }; + }; + }; diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi index a5e90f078aa9..c08f84629aa9 100644 --- a/arch/arm/boot/dts/pxa2xx.dtsi +++ b/arch/arm/boot/dts/pxa2xx.dtsi @@ -113,14 +113,14 @@ }; usb0: ohci@4c000000 { - compatible = "mrvl,pxa-ohci"; + compatible = "marvell,pxa-ohci"; reg = <0x4c000000 0x10000>; interrupts = <3>; status = "disabled"; }; mmc0: mmc@41100000 { - compatible = "mrvl,pxa-mmc"; + compatible = "marvell,pxa-mmc"; reg = <0x41100000 0x1000>; interrupts = <23>; status = "disabled"; diff --git a/arch/arm/boot/dts/pxa910-dkb.dts b/arch/arm/boot/dts/pxa910-dkb.dts index 595492aa5053..c82f2810ec73 100644 --- a/arch/arm/boot/dts/pxa910-dkb.dts +++ b/arch/arm/boot/dts/pxa910-dkb.dts @@ -8,7 +8,7 @@ */ /dts-v1/; -/include/ "pxa910.dtsi" +#include "pxa910.dtsi" / { model = "Marvell PXA910 DKB Development Board"; diff --git a/arch/arm/boot/dts/pxa910.dtsi b/arch/arm/boot/dts/pxa910.dtsi index 0247c622f580..0868f6729be1 100644 --- a/arch/arm/boot/dts/pxa910.dtsi +++ b/arch/arm/boot/dts/pxa910.dtsi @@ -7,7 +7,8 @@ * publishhed by the Free Software Foundation. */ -/include/ "skeleton.dtsi" +#include "skeleton.dtsi" +#include <dt-bindings/clock/marvell,pxa910.h> / { aliases { @@ -71,6 +72,8 @@ compatible = "mrvl,mmp-uart"; reg = <0xd4017000 0x1000>; interrupts = <27>; + clocks = <&soc_clocks PXA910_CLK_UART0>; + resets = <&soc_clocks PXA910_CLK_UART0>; status = "disabled"; }; @@ -78,6 +81,8 @@ compatible = "mrvl,mmp-uart"; reg = <0xd4018000 0x1000>; interrupts = <28>; + clocks = <&soc_clocks PXA910_CLK_UART1>; + resets = <&soc_clocks PXA910_CLK_UART1>; status = "disabled"; }; @@ -85,6 +90,8 @@ compatible = "mrvl,mmp-uart"; reg = <0xd4036000 0x1000>; interrupts = <59>; + clocks = <&soc_clocks PXA910_CLK_UART2>; + resets = <&soc_clocks PXA910_CLK_UART2>; status = "disabled"; }; @@ -97,6 +104,8 @@ #gpio-cells = <2>; interrupts = <49>; interrupt-names = "gpio_mux"; + clocks = <&soc_clocks PXA910_CLK_GPIO>; + resets = <&soc_clocks PXA910_CLK_GPIO>; interrupt-controller; #interrupt-cells = <1>; ranges; @@ -124,6 +133,8 @@ #size-cells = <0>; reg = <0xd4011000 0x1000>; interrupts = <7>; + clocks = <&soc_clocks PXA910_CLK_TWSI0>; + resets = <&soc_clocks PXA910_CLK_TWSI0>; mrvl,i2c-fast-mode; status = "disabled"; }; @@ -134,6 +145,8 @@ #size-cells = <0>; reg = <0xd4037000 0x1000>; interrupts = <54>; + clocks = <&soc_clocks PXA910_CLK_TWSI1>; + resets = <&soc_clocks PXA910_CLK_TWSI1>; status = "disabled"; }; @@ -142,8 +155,21 @@ reg = <0xd4010000 0x1000>; interrupts = <5 6>; interrupt-names = "rtc 1Hz", "rtc alarm"; + clocks = <&soc_clocks PXA910_CLK_RTC>; + resets = <&soc_clocks PXA910_CLK_RTC>; status = "disabled"; }; }; + + soc_clocks: clocks{ + compatible = "marvell,pxa910-clock"; + reg = <0xd4050000 0x1000>, + <0xd4282800 0x400>, + <0xd4015000 0x1000>, + <0xd403b000 0x1000>; + reg-names = "mpmu", "apmu", "apbc", "apbcp"; + #clock-cells = <1>; + #reset-cells = <1>; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts new file mode 100644 index 000000000000..5d75666f7f6c --- /dev/null +++ b/arch/arm/boot/dts/qcom-apq8064-cm-qs600.dts @@ -0,0 +1,59 @@ +#include "qcom-apq8064-v2.0.dtsi" + +/ { + model = "CompuLab CM-QS600"; + compatible = "qcom,apq8064-cm-qs600", "qcom,apq8064"; + + soc { + pinctrl@800000 { + i2c1_pins: i2c1 { + mux { + pins = "gpio20", "gpio21"; + function = "gsbi1"; + }; + }; + }; + + gsbi@12440000 { + status = "okay"; + qcom,mode = <GSBI_PROT_I2C>; + + i2c@12460000 { + status = "okay"; + clock-frequency = <200000>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + + eeprom: eeprom@50 { + compatible = "24c02"; + reg = <0x50>; + pagesize = <32>; + }; + }; + }; + + gsbi@16600000 { + status = "ok"; + qcom,mode = <GSBI_PROT_I2C_UART>; + serial@16640000 { + status = "ok"; + }; + }; + + amba { + /* eMMC */ + sdcc1: sdcc@12400000 { + status = "okay"; + }; + + /* External micro SD card */ + sdcc3: sdcc@12180000 { + status = "okay"; + }; + /* WLAN */ + sdcc4: sdcc@121c0000 { + status = "okay"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts index 7c2441d526bc..b396c8311b27 100644 --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -5,6 +5,33 @@ compatible = "qcom,apq8064-ifc6410", "qcom,apq8064"; soc { + pinctrl@800000 { + i2c1_pins: i2c1 { + mux { + pins = "gpio20", "gpio21"; + function = "gsbi1"; + }; + }; + }; + + gsbi@12440000 { + status = "okay"; + qcom,mode = <GSBI_PROT_I2C>; + + i2c@12460000 { + status = "okay"; + clock-frequency = <200000>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + + eeprom: eeprom@52 { + compatible = "atmel,24c128"; + reg = <0x52>; + pagesize = <32>; + }; + }; + }; + gsbi@16600000 { status = "ok"; qcom,mode = <GSBI_PROT_I2C_UART>; @@ -12,5 +39,21 @@ status = "ok"; }; }; + + amba { + /* eMMC */ + sdcc1: sdcc@12400000 { + status = "okay"; + }; + + /* External micro SD card */ + sdcc3: sdcc@12180000 { + status = "okay"; + }; + /* WLAN */ + sdcc4: sdcc@121c0000 { + status = "okay"; + }; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 92bf793622c3..b3154c071652 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -2,7 +2,9 @@ #include "skeleton.dtsi" #include <dt-bindings/clock/qcom,gcc-msm8960.h> +#include <dt-bindings/clock/qcom,mmcc-msm8960.h> #include <dt-bindings/soc/qcom,gsbi.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> / { model = "Qualcomm APQ8064"; @@ -70,6 +72,34 @@ ranges; compatible = "simple-bus"; + tlmm_pinmux: pinctrl@800000 { + compatible = "qcom,apq8064-pinctrl"; + reg = <0x800000 0x4000>; + + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&ps_hold>; + + sdc4_gpios: sdc4-gpios { + pios { + pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68"; + function = "sdc4"; + }; + }; + + ps_hold: ps_hold { + mux { + pins = "gpio78"; + function = "ps_hold"; + }; + }; + }; + intc: interrupt-controller@2000000 { compatible = "qcom,msm-qgic2"; interrupt-controller; @@ -133,6 +163,48 @@ regulator; }; + gsbi1: gsbi@12440000 { + status = "disabled"; + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x12440000 0x100>; + clocks = <&gcc GSBI1_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + i2c1: i2c@12460000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x12460000 0x1000>; + interrupts = <0 194 IRQ_TYPE_NONE>; + clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + gsbi2: gsbi@12480000 { + status = "disabled"; + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x12480000 0x100>; + clocks = <&gcc GSBI2_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + i2c2: i2c@124a0000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x124a0000 0x1000>; + interrupts = <0 196 IRQ_TYPE_NONE>; + clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + gsbi7: gsbi@16600000 { status = "disabled"; compatible = "qcom,gsbi-v1.0.0"; @@ -166,5 +238,116 @@ #clock-cells = <1>; #reset-cells = <1>; }; + + mmcc: clock-controller@4000000 { + compatible = "qcom,mmcc-apq8064"; + reg = <0x4000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + /* Temporary fixed regulator */ + vsdcc_fixed: vsdcc-regulator { + compatible = "regulator-fixed"; + regulator-name = "SDCC Power"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + regulator-always-on; + }; + + sdcc1bam:dma@12402000{ + compatible = "qcom,bam-v1.3.0"; + reg = <0x12402000 0x8000>; + interrupts = <0 98 0>; + clocks = <&gcc SDC1_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + sdcc3bam:dma@12182000{ + compatible = "qcom,bam-v1.3.0"; + reg = <0x12182000 0x8000>; + interrupts = <0 96 0>; + clocks = <&gcc SDC3_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + sdcc4bam:dma@121c2000{ + compatible = "qcom,bam-v1.3.0"; + reg = <0x121c2000 0x8000>; + interrupts = <0 95 0>; + clocks = <&gcc SDC4_H_CLK>; + clock-names = "bam_clk"; + #dma-cells = <1>; + qcom,ee = <0>; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + sdcc1: sdcc@12400000 { + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + reg = <0x12400000 0x2000>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <96000000>; + non-removable; + cap-sd-highspeed; + cap-mmc-highspeed; + vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; + dma-names = "tx", "rx"; + }; + + sdcc3: sdcc@12180000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + status = "disabled"; + reg = <0x12180000 0x2000>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <192000000>; + no-1-8-v; + vmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; + dma-names = "tx", "rx"; + }; + + sdcc4: sdcc@121c0000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + status = "disabled"; + reg = <0x121c0000 0x2000>; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <48000000>; + vmmc-supply = <&vsdcc_fixed>; + vqmmc-supply = <&vsdcc_fixed>; + dmas = <&sdcc4bam 2>, <&sdcc4bam 1>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&sdc4_gpios>; + }; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts index b4dfb01fe6fb..47370494d0f8 100644 --- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts @@ -22,6 +22,13 @@ pinctrl@fd510000 { + i2c11_pins: i2c11 { + mux { + pins = "gpio83", "gpio84"; + function = "blsp_i2c11"; + }; + }; + spi8_default: spi8_default { mosi { pins = "gpio45"; @@ -41,5 +48,19 @@ }; }; }; + + i2c@f9967000 { + status = "okay"; + clock-frequency = <200000>; + pinctrl-0 = <&i2c11_pins>; + pinctrl-names = "default"; + + eeprom: eeprom@52 { + compatible = "atmel,24c128"; + reg = <0x52>; + pagesize = <32>; + read-only; + }; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts new file mode 100644 index 000000000000..c9ff10821ad9 --- /dev/null +++ b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts @@ -0,0 +1,23 @@ +#include "qcom-apq8084.dtsi" + +/ { + model = "Qualcomm APQ8084/IFC6540"; + compatible = "qcom,apq8084-ifc6540", "qcom,apq8084"; + + soc { + serial@f995e000 { + status = "okay"; + }; + + sdhci@f9824900 { + bus-width = <8>; + non-removable; + status = "okay"; + }; + + sdhci@f98a4900 { + cd-gpios = <&tlmm 122 GPIO_ACTIVE_LOW>; + bus-width = <4>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-apq8084-mtp.dts b/arch/arm/boot/dts/qcom-apq8084-mtp.dts index 9dae3878b71d..8ecec58a9ff6 100644 --- a/arch/arm/boot/dts/qcom-apq8084-mtp.dts +++ b/arch/arm/boot/dts/qcom-apq8084-mtp.dts @@ -3,4 +3,10 @@ / { model = "Qualcomm APQ 8084-MTP"; compatible = "qcom,apq8084-mtp", "qcom,apq8084"; + + soc { + serial@f995e000 { + status = "okay"; + }; + }; }; diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index e3e009a5912b..1f130bc16858 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -2,6 +2,9 @@ #include "skeleton.dtsi" +#include <dt-bindings/clock/qcom,gcc-apq8084.h> +#include <dt-bindings/gpio/gpio.h> + / { model = "Qualcomm APQ 8084"; compatible = "qcom,apq8084"; @@ -175,5 +178,53 @@ compatible = "qcom,pshold"; reg = <0xfc4ab000 0x4>; }; + + gcc: clock-controller@fc400000 { + compatible = "qcom,gcc-apq8084"; + #clock-cells = <1>; + #reset-cells = <1>; + reg = <0xfc400000 0x4000>; + }; + + tlmm: pinctrl@fd510000 { + compatible = "qcom,apq8084-pinctrl"; + reg = <0xfd510000 0x4000>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 208 0>; + }; + + serial@f995e000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xf995e000 0x1000>; + interrupts = <0 114 0x0>; + clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + sdhci@f9824900 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; + reg-names = "hc_mem", "core_mem"; + interrupts = <0 123 0>, <0 138 0>; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + sdhci@f98a4900 { + compatible = "qcom,sdhci-msm-v4"; + reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; + reg-names = "hc_mem", "core_mem"; + interrupts = <0 125 0>, <0 221 0>; + interrupt-names = "hc_irq", "pwr_irq"; + clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts new file mode 100644 index 000000000000..55b2910efd87 --- /dev/null +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts @@ -0,0 +1,93 @@ +#include "qcom-ipq8064-v1.0.dtsi" + +/ { + model = "Qualcomm IPQ8064/AP148"; + compatible = "qcom,ipq8064-ap148", "qcom,ipq8064"; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + rsvd@41200000 { + reg = <0x41200000 0x300000>; + no-map; + }; + }; + + soc { + pinmux@800000 { + i2c4_pins: i2c4_pinmux { + pins = "gpio12", "gpio13"; + function = "gsbi4"; + bias-disable; + }; + + spi_pins: spi_pins { + mux { + pins = "gpio18", "gpio19", "gpio21"; + function = "gsbi5"; + drive-strength = <10>; + bias-none; + }; + }; + }; + + gsbi@16300000 { + qcom,mode = <GSBI_PROT_I2C_UART>; + status = "ok"; + serial@16340000 { + status = "ok"; + }; + + i2c4: i2c@16380000 { + status = "ok"; + + clock-frequency = <200000>; + + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "default"; + }; + }; + + gsbi5: gsbi@1a200000 { + qcom,mode = <GSBI_PROT_SPI>; + status = "ok"; + + spi4: spi@1a280000 { + status = "ok"; + spi-max-frequency = <50000000>; + + pinctrl-0 = <&spi_pins>; + pinctrl-names = "default"; + + cs-gpios = <&qcom_pinmux 20 0>; + + flash: m25p80@0 { + compatible = "s25fl256s1"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <50000000>; + reg = <0>; + + partition@0 { + label = "rootfs"; + reg = <0x0 0x1000000>; + }; + + partition@1 { + label = "scratch"; + reg = <0x1000000 0x1000000>; + }; + }; + }; + }; + + sata-phy@1b400000 { + status = "ok"; + }; + + sata@29000000 { + status = "ok"; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi new file mode 100644 index 000000000000..7093b075e408 --- /dev/null +++ b/arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi @@ -0,0 +1 @@ +#include "qcom-ipq8064.dtsi" diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi new file mode 100644 index 000000000000..63b2146f563b --- /dev/null +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -0,0 +1,283 @@ +/dts-v1/; + +#include "skeleton.dtsi" +#include <dt-bindings/clock/qcom,gcc-ipq806x.h> +#include <dt-bindings/soc/qcom,gsbi.h> + +/ { + model = "Qualcomm IPQ8064"; + compatible = "qcom,ipq8064"; + interrupt-parent = <&intc>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v1"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + qcom,acc = <&acc0>; + qcom,saw = <&saw0>; + }; + + cpu@1 { + compatible = "qcom,krait"; + enable-method = "qcom,kpss-acc-v1"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + qcom,acc = <&acc1>; + qcom,saw = <&saw1>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + }; + }; + + cpu-pmu { + compatible = "qcom,krait-pmu"; + interrupts = <1 10 0x304>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + nss@40000000 { + reg = <0x40000000 0x1000000>; + no-map; + }; + + smem@41000000 { + reg = <0x41000000 0x200000>; + no-map; + }; + }; + + soc: soc { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "simple-bus"; + + qcom_pinmux: pinmux@800000 { + compatible = "qcom,ipq8064-pinctrl"; + reg = <0x800000 0x4000>; + + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 32 0x4>; + }; + + intc: interrupt-controller@2000000 { + compatible = "qcom,msm-qgic2"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x02000000 0x1000>, + <0x02002000 0x1000>; + }; + + timer@200a000 { + compatible = "qcom,kpss-timer", "qcom,msm-timer"; + interrupts = <1 1 0x301>, + <1 2 0x301>, + <1 3 0x301>; + reg = <0x0200a000 0x100>; + clock-frequency = <25000000>, + <32768>; + cpu-offset = <0x80000>; + }; + + acc0: clock-controller@2088000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02088000 0x1000>, <0x02008000 0x1000>; + }; + + acc1: clock-controller@2098000 { + compatible = "qcom,kpss-acc-v1"; + reg = <0x02098000 0x1000>, <0x02008000 0x1000>; + }; + + saw0: regulator@2089000 { + compatible = "qcom,saw2"; + reg = <0x02089000 0x1000>, <0x02009000 0x1000>; + regulator; + }; + + saw1: regulator@2099000 { + compatible = "qcom,saw2"; + reg = <0x02099000 0x1000>, <0x02009000 0x1000>; + regulator; + }; + + gsbi2: gsbi@12480000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x12480000 0x100>; + clocks = <&gcc GSBI2_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + serial@12490000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x12490000 0x1000>, + <0x12480000 0x1000>; + interrupts = <0 195 0x0>; + clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + i2c@124a0000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x124a0000 0x1000>; + interrupts = <0 196 0>; + + clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + + }; + + gsbi4: gsbi@16300000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x16300000 0x100>; + clocks = <&gcc GSBI4_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + serial@16340000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16340000 0x1000>, + <0x16300000 0x1000>; + interrupts = <0 152 0x0>; + clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + i2c@16380000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x16380000 0x1000>; + interrupts = <0 153 0>; + + clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + gsbi5: gsbi@1a200000 { + compatible = "qcom,gsbi-v1.0.0"; + reg = <0x1a200000 0x100>; + clocks = <&gcc GSBI5_H_CLK>; + clock-names = "iface"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + serial@1a240000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x1a240000 0x1000>, + <0x1a200000 0x1000>; + interrupts = <0 154 0x0>; + clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + }; + + i2c@1a280000 { + compatible = "qcom,i2c-qup-v1.1.1"; + reg = <0x1a280000 0x1000>; + interrupts = <0 155 0>; + + clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + + spi@1a280000 { + compatible = "qcom,spi-qup-v1.1.1"; + reg = <0x1a280000 0x1000>; + interrupts = <0 155 0>; + + clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; + clock-names = "core", "iface"; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + sata_phy: sata-phy@1b400000 { + compatible = "qcom,ipq806x-sata-phy"; + reg = <0x1b400000 0x200>; + + clocks = <&gcc SATA_PHY_CFG_CLK>; + clock-names = "cfg"; + + #phy-cells = <0>; + status = "disabled"; + }; + + sata@29000000 { + compatible = "qcom,ipq806x-ahci", "generic-ahci"; + reg = <0x29000000 0x180>; + + interrupts = <0 209 0x0>; + + clocks = <&gcc SFAB_SATA_S_H_CLK>, + <&gcc SATA_H_CLK>, + <&gcc SATA_A_CLK>, + <&gcc SATA_RXOOB_CLK>, + <&gcc SATA_PMALIVE_CLK>; + clock-names = "slave_face", "iface", "core", + "rxoob", "pmalive"; + + assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>; + assigned-clock-rates = <100000000>, <100000000>; + + phys = <&sata_phy>; + phy-names = "sata-phy"; + status = "disabled"; + }; + + qcom,ssbi@500000 { + compatible = "qcom,ssbi"; + reg = <0x00500000 0x1000>; + qcom,controller-type = "pmic-arbiter"; + }; + + gcc: clock-controller@900000 { + compatible = "qcom,gcc-ipq8064"; + reg = <0x00900000 0x4000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts b/arch/arm/boot/dts/qcom-msm8660-surf.dts index 45180adfadf1..e0883c376248 100644 --- a/arch/arm/boot/dts/qcom-msm8660-surf.dts +++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts @@ -1,3 +1,5 @@ +#include <dt-bindings/input/input.h> + #include "qcom-msm8660.dtsi" / { @@ -12,5 +14,45 @@ status = "ok"; }; }; + + amba { + /* eMMC */ + sdcc1: sdcc@12400000 { + status = "okay"; + }; + + /* External micro SD card */ + sdcc3: sdcc@12180000 { + status = "okay"; + }; + }; + }; +}; + +&pmicintc { + keypad@148 { + linux,keymap = < + MATRIX_KEY(0, 0, KEY_FN_F1) + MATRIX_KEY(0, 1, KEY_UP) + MATRIX_KEY(0, 2, KEY_LEFT) + MATRIX_KEY(0, 3, KEY_VOLUMEUP) + MATRIX_KEY(1, 0, KEY_FN_F2) + MATRIX_KEY(1, 1, KEY_RIGHT) + MATRIX_KEY(1, 2, KEY_DOWN) + MATRIX_KEY(1, 3, KEY_VOLUMEDOWN) + MATRIX_KEY(2, 3, KEY_ENTER) + MATRIX_KEY(4, 0, KEY_CAMERA_FOCUS) + MATRIX_KEY(4, 1, KEY_UP) + MATRIX_KEY(4, 2, KEY_LEFT) + MATRIX_KEY(4, 3, KEY_HOME) + MATRIX_KEY(4, 4, KEY_FN_F3) + MATRIX_KEY(5, 0, KEY_CAMERA) + MATRIX_KEY(5, 1, KEY_RIGHT) + MATRIX_KEY(5, 2, KEY_DOWN) + MATRIX_KEY(5, 3, KEY_BACK) + MATRIX_KEY(5, 4, KEY_MENU) + >; + keypad,num-rows = <6>; + keypad,num-columns = <5>; }; }; diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi index 53837aaa2f72..0affd6193f56 100644 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi @@ -2,6 +2,7 @@ /include/ "skeleton.dtsi" +#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,gcc-msm8660.h> #include <dt-bindings/soc/qcom,gsbi.h> @@ -103,6 +104,98 @@ compatible = "qcom,ssbi"; reg = <0x500000 0x1000>; qcom,controller-type = "pmic-arbiter"; + + pmicintc: pmic@0 { + compatible = "qcom,pm8058"; + interrupt-parent = <&msmgpio>; + interrupts = <88 8>; + #interrupt-cells = <2>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + + pwrkey@1c { + compatible = "qcom,pm8058-pwrkey"; + reg = <0x1c>; + interrupt-parent = <&pmicintc>; + interrupts = <50 1>, <51 1>; + debounce = <15625>; + pull-up; + }; + + keypad@148 { + compatible = "qcom,pm8058-keypad"; + reg = <0x148>; + interrupt-parent = <&pmicintc>; + interrupts = <74 1>, <75 1>; + debounce = <15>; + scan-delay = <32>; + row-hold = <91500>; + }; + + rtc@11d { + compatible = "qcom,pm8058-rtc"; + interrupt-parent = <&pmicintc>; + interrupts = <39 1>; + reg = <0x11d>; + allow-set-time; + }; + + vibrator@4a { + compatible = "qcom,pm8058-vib"; + reg = <0x4a>; + }; + }; + }; + + /* Temporary fixed regulator */ + vsdcc_fixed: vsdcc-regulator { + compatible = "regulator-fixed"; + regulator-name = "SDCC Power"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + regulator-always-on; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + sdcc1: sdcc@12400000 { + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + reg = <0x12400000 0x8000>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <48000000>; + non-removable; + cap-sd-highspeed; + cap-mmc-highspeed; + vmmc-supply = <&vsdcc_fixed>; + }; + + sdcc3: sdcc@12180000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + status = "disabled"; + reg = <0x12180000 0x8000>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <48000000>; + no-1-8-v; + vmmc-supply = <&vsdcc_fixed>; + }; }; }; + }; diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom-msm8960-cdp.dts index 8f75cc4c8340..7f70fae90959 100644 --- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts +++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts @@ -1,3 +1,5 @@ +#include <dt-bindings/input/input.h> + #include "qcom-msm8960.dtsi" / { @@ -12,5 +14,30 @@ status = "ok"; }; }; + + amba { + /* eMMC */ + sdcc1: sdcc@12400000 { + status = "okay"; + }; + + /* External micro SD card */ + sdcc3: sdcc@12180000 { + status = "okay"; + }; + }; + }; +}; + +&pmicintc { + keypad@148 { + linux,keymap = < + MATRIX_KEY(0, 0, KEY_VOLUMEUP) + MATRIX_KEY(0, 1, KEY_VOLUMEDOWN) + MATRIX_KEY(0, 2, KEY_CAMERA_FOCUS) + MATRIX_KEY(0, 3, KEY_CAMERA) + >; + keypad,num-rows = <1>; + keypad,num-columns = <5>; }; }; diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index 5303e53e34dc..e1b0d5cd9e3c 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -2,6 +2,7 @@ /include/ "skeleton.dtsi" +#include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/qcom,gcc-msm8960.h> #include <dt-bindings/soc/qcom,gsbi.h> @@ -143,6 +144,43 @@ compatible = "qcom,ssbi"; reg = <0x500000 0x1000>; qcom,controller-type = "pmic-arbiter"; + + pmicintc: pmic@0 { + compatible = "qcom,pm8921"; + interrupt-parent = <&msmgpio>; + interrupts = <104 8>; + #interrupt-cells = <2>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + + pwrkey@1c { + compatible = "qcom,pm8921-pwrkey"; + reg = <0x1c>; + interrupt-parent = <&pmicintc>; + interrupts = <50 1>, <51 1>; + debounce = <15625>; + pull-up; + }; + + keypad@148 { + compatible = "qcom,pm8921-keypad"; + reg = <0x148>; + interrupt-parent = <&pmicintc>; + interrupts = <74 1>, <75 1>; + debounce = <15>; + scan-delay = <32>; + row-hold = <91500>; + }; + + rtc@11d { + compatible = "qcom,pm8921-rtc"; + interrupt-parent = <&pmicintc>; + interrupts = <39 1>; + reg = <0x11d>; + allow-set-time; + }; + }; }; rng@1a500000 { @@ -151,5 +189,54 @@ clocks = <&gcc PRNG_CLK>; clock-names = "core"; }; + + /* Temporary fixed regulator */ + vsdcc_fixed: vsdcc-regulator { + compatible = "regulator-fixed"; + regulator-name = "SDCC Power"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + regulator-always-on; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + sdcc1: sdcc@12400000 { + status = "disabled"; + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + reg = <0x12400000 0x8000>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <8>; + max-frequency = <96000000>; + non-removable; + cap-sd-highspeed; + cap-mmc-highspeed; + vmmc-supply = <&vsdcc_fixed>; + }; + + sdcc3: sdcc@12180000 { + compatible = "arm,pl18x", "arm,primecell"; + arm,primecell-periphid = <0x00051180>; + status = "disabled"; + reg = <0x12180000 0x8000>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cmd_irq"; + clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; + clock-names = "mclk", "apb_pclk"; + bus-width = <4>; + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <192000000>; + no-1-8-v; + vmmc-supply = <&vsdcc_fixed>; + }; + }; }; }; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts new file mode 100644 index 000000000000..cccc21b7c8fd --- /dev/null +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts @@ -0,0 +1,17 @@ +#include "qcom-msm8974.dtsi" + +/ { + model = "Sony Xperia Z1"; + compatible = "sony,xperia-honami", "qcom,msm8974"; + + memory@0 { + reg = <0 0x40000000>, <0x40000000 0x40000000>; + device_type = "memory"; + }; +}; + +&soc { + serial@f991e000 { + status = "ok"; + }; +}; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 69dca2aca25a..e265ec16a787 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -1,8 +1,8 @@ /dts-v1/; -#include "skeleton.dtsi" - +#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/clock/qcom,gcc-msm8974.h> +#include "skeleton.dtsi" / { model = "Qualcomm MSM8974"; @@ -236,5 +236,16 @@ #interrupt-cells = <2>; interrupts = <0 208 0>; }; + + blsp_i2c11: i2c@f9967000 { + status = "disable"; + compatible = "qcom,i2c-qup-v2.1.1"; + reg = <0xf9967000 0x1000>; + interrupts = <0 105 IRQ_TYPE_NONE>; + clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; + clock-names = "core", "iface"; + #address-cells = <1>; + #size-cells = <0>; + }; }; }; diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts index 20705467f4c9..1518c5bcca33 100644 --- a/arch/arm/boot/dts/r7s72100-genmai.dts +++ b/arch/arm/boot/dts/r7s72100-genmai.dts @@ -21,7 +21,8 @@ }; chosen { - bootargs = "console=ttySC2,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + stdout-path = &scif2; }; memory { @@ -43,6 +44,10 @@ clock-frequency = <48000000>; }; +&mtu2 { + status = "ok"; +}; + &i2c2 { status = "okay"; clock-frequency = <400000>; diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index bdee22541189..277e73c110e5 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi @@ -52,16 +52,6 @@ clock-output-names = "usb_x1"; }; - /* Special CPG clocks */ - cpg_clocks: cpg_clocks@fcfe0000 { - #clock-cells = <1>; - compatible = "renesas,r7s72100-cpg-clocks", - "renesas,rz-cpg-clocks"; - reg = <0xfcfe0000 0x18>; - clocks = <&extal_clk>, <&usb_x1_clk>; - clock-output-names = "pll", "i", "g"; - }; - /* Fixed factor clocks */ b_clk: b_clk { #clock-cells = <0>; @@ -88,6 +78,16 @@ clock-output-names = "p0"; }; + /* Special CPG clocks */ + cpg_clocks: cpg_clocks@fcfe0000 { + #clock-cells = <1>; + compatible = "renesas,r7s72100-cpg-clocks", + "renesas,rz-cpg-clocks"; + reg = <0xfcfe0000 0x18>; + clocks = <&extal_clk>, <&usb_x1_clk>; + clock-output-names = "pll", "i", "g"; + }; + /* MSTP clocks */ mstp3_clks: mstp3_clks@fcfe0420 { #clock-cells = <1>; @@ -148,87 +148,6 @@ }; }; - gic: interrupt-controller@e8201000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0xe8201000 0x1000>, - <0xe8202000 0x1000>; - }; - - i2c0: i2c@fcfee000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; - reg = <0xfcfee000 0x44>; - interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>, - <0 158 IRQ_TYPE_EDGE_RISING>, - <0 159 IRQ_TYPE_EDGE_RISING>, - <0 160 IRQ_TYPE_LEVEL_HIGH>, - <0 161 IRQ_TYPE_LEVEL_HIGH>, - <0 162 IRQ_TYPE_LEVEL_HIGH>, - <0 163 IRQ_TYPE_LEVEL_HIGH>, - <0 164 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R7S72100_CLK_I2C0>; - clock-frequency = <100000>; - status = "disabled"; - }; - - i2c1: i2c@fcfee400 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; - reg = <0xfcfee400 0x44>; - interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>, - <0 166 IRQ_TYPE_EDGE_RISING>, - <0 167 IRQ_TYPE_EDGE_RISING>, - <0 168 IRQ_TYPE_LEVEL_HIGH>, - <0 169 IRQ_TYPE_LEVEL_HIGH>, - <0 170 IRQ_TYPE_LEVEL_HIGH>, - <0 171 IRQ_TYPE_LEVEL_HIGH>, - <0 172 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R7S72100_CLK_I2C1>; - clock-frequency = <100000>; - status = "disabled"; - }; - - i2c2: i2c@fcfee800 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; - reg = <0xfcfee800 0x44>; - interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>, - <0 174 IRQ_TYPE_EDGE_RISING>, - <0 175 IRQ_TYPE_EDGE_RISING>, - <0 176 IRQ_TYPE_LEVEL_HIGH>, - <0 177 IRQ_TYPE_LEVEL_HIGH>, - <0 178 IRQ_TYPE_LEVEL_HIGH>, - <0 179 IRQ_TYPE_LEVEL_HIGH>, - <0 180 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R7S72100_CLK_I2C2>; - clock-frequency = <100000>; - status = "disabled"; - }; - - i2c3: i2c@fcfeec00 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; - reg = <0xfcfeec00 0x44>; - interrupts = <0 181 IRQ_TYPE_LEVEL_HIGH>, - <0 182 IRQ_TYPE_EDGE_RISING>, - <0 183 IRQ_TYPE_EDGE_RISING>, - <0 184 IRQ_TYPE_LEVEL_HIGH>, - <0 185 IRQ_TYPE_LEVEL_HIGH>, - <0 186 IRQ_TYPE_LEVEL_HIGH>, - <0 187 IRQ_TYPE_LEVEL_HIGH>, - <0 188 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R7S72100_CLK_I2C3>; - clock-frequency = <100000>; - status = "disabled"; - }; - scif0: serial@e8007000 { compatible = "renesas,scif-r7s72100", "renesas,scif"; reg = <0xe8007000 64>; @@ -394,4 +313,95 @@ #size-cells = <0>; status = "disabled"; }; + + gic: interrupt-controller@e8201000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0xe8201000 0x1000>, + <0xe8202000 0x1000>; + }; + + i2c0: i2c@fcfee000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; + reg = <0xfcfee000 0x44>; + interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>, + <0 158 IRQ_TYPE_EDGE_RISING>, + <0 159 IRQ_TYPE_EDGE_RISING>, + <0 160 IRQ_TYPE_LEVEL_HIGH>, + <0 161 IRQ_TYPE_LEVEL_HIGH>, + <0 162 IRQ_TYPE_LEVEL_HIGH>, + <0 163 IRQ_TYPE_LEVEL_HIGH>, + <0 164 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R7S72100_CLK_I2C0>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c1: i2c@fcfee400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; + reg = <0xfcfee400 0x44>; + interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>, + <0 166 IRQ_TYPE_EDGE_RISING>, + <0 167 IRQ_TYPE_EDGE_RISING>, + <0 168 IRQ_TYPE_LEVEL_HIGH>, + <0 169 IRQ_TYPE_LEVEL_HIGH>, + <0 170 IRQ_TYPE_LEVEL_HIGH>, + <0 171 IRQ_TYPE_LEVEL_HIGH>, + <0 172 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R7S72100_CLK_I2C1>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c2: i2c@fcfee800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; + reg = <0xfcfee800 0x44>; + interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>, + <0 174 IRQ_TYPE_EDGE_RISING>, + <0 175 IRQ_TYPE_EDGE_RISING>, + <0 176 IRQ_TYPE_LEVEL_HIGH>, + <0 177 IRQ_TYPE_LEVEL_HIGH>, + <0 178 IRQ_TYPE_LEVEL_HIGH>, + <0 179 IRQ_TYPE_LEVEL_HIGH>, + <0 180 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R7S72100_CLK_I2C2>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c3: i2c@fcfeec00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,riic-r7s72100", "renesas,riic-rz"; + reg = <0xfcfeec00 0x44>; + interrupts = <0 181 IRQ_TYPE_LEVEL_HIGH>, + <0 182 IRQ_TYPE_EDGE_RISING>, + <0 183 IRQ_TYPE_EDGE_RISING>, + <0 184 IRQ_TYPE_LEVEL_HIGH>, + <0 185 IRQ_TYPE_LEVEL_HIGH>, + <0 186 IRQ_TYPE_LEVEL_HIGH>, + <0 187 IRQ_TYPE_LEVEL_HIGH>, + <0 188 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R7S72100_CLK_I2C3>; + clock-frequency = <100000>; + status = "disabled"; + }; + + mtu2: timer@fcff0000 { + compatible = "renesas,mtu2-r7s72100", "renesas,mtu2"; + reg = <0xfcff0000 0x400>; + interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "tgi0a"; + clocks = <&mstp3_clks R7S72100_CLK_MTU2>; + clock-names = "fck"; + status = "disabled"; + }; }; diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts index a860f32bca27..84e05f713c54 100644 --- a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts +++ b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts @@ -21,7 +21,8 @@ }; chosen { - bootargs = "console=ttySC0,115200 ignore_loglevel rw"; + bootargs = "ignore_loglevel rw"; + stdout-path = &scifa0; }; memory@40000000 { @@ -93,6 +94,10 @@ voltage-tolerance = <1>; /* 1% */ }; +&cmt1 { + status = "okay"; +}; + &pfc { scifa0_pins: serial0 { renesas,groups = "scifa0_data"; diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi index d8ec5058c351..5ac57babc3b9 100644 --- a/arch/arm/boot/dts/r8a73a4.dtsi +++ b/arch/arm/boot/dts/r8a73a4.dtsi @@ -30,18 +30,6 @@ }; }; - gic: interrupt-controller@f1001000 { - compatible = "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - #address-cells = <0>; - interrupt-controller; - reg = <0 0xf1001000 0 0x1000>, - <0 0xf1002000 0 0x1000>, - <0 0xf1004000 0 0x2000>, - <0 0xf1006000 0 0x2000>; - interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; - }; - timer { compatible = "arm,armv7-timer"; interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, @@ -50,8 +38,93 @@ <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; + dmac: dma-multiplexer { + compatible = "renesas,shdma-mux"; + #dma-cells = <1>; + dma-channels = <20>; + dma-requests = <256>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dma0: dma-controller@e6700020 { + compatible = "renesas,shdma-r8a73a4"; + reg = <0 0xe6700020 0 0x89e0>; + interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH + 0 200 IRQ_TYPE_LEVEL_HIGH + 0 201 IRQ_TYPE_LEVEL_HIGH + 0 202 IRQ_TYPE_LEVEL_HIGH + 0 203 IRQ_TYPE_LEVEL_HIGH + 0 204 IRQ_TYPE_LEVEL_HIGH + 0 205 IRQ_TYPE_LEVEL_HIGH + 0 206 IRQ_TYPE_LEVEL_HIGH + 0 207 IRQ_TYPE_LEVEL_HIGH + 0 208 IRQ_TYPE_LEVEL_HIGH + 0 209 IRQ_TYPE_LEVEL_HIGH + 0 210 IRQ_TYPE_LEVEL_HIGH + 0 211 IRQ_TYPE_LEVEL_HIGH + 0 212 IRQ_TYPE_LEVEL_HIGH + 0 213 IRQ_TYPE_LEVEL_HIGH + 0 214 IRQ_TYPE_LEVEL_HIGH + 0 215 IRQ_TYPE_LEVEL_HIGH + 0 216 IRQ_TYPE_LEVEL_HIGH + 0 217 IRQ_TYPE_LEVEL_HIGH + 0 218 IRQ_TYPE_LEVEL_HIGH + 0 219 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19"; + }; + }; + + pfc: pfc@e6050000 { + compatible = "renesas,pfc-r8a73a4"; + reg = <0 0xe6050000 0 0x9000>; + gpio-controller; + #gpio-cells = <2>; + interrupts-extended = + <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>, + <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>, + <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>, + <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>, + <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>, + <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>, + <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>, + <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>, + <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>, + <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>, + <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>, + <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>, + <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>, + <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>, + <&irqc1 24 0>, <&irqc1 25 0>; + }; + + i2c5: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x428>; + interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>; + + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,cmt-48-r8a73a4", "renesas,cmt-48-gen2"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; + + renesas,channels-mask = <0xff>; + + status = "disabled"; + }; + irqc0: interrupt-controller@e61c0000 { - compatible = "renesas,irqc"; + compatible = "renesas,irqc-r8a73a4", "renesas,irqc"; #interrupt-cells = <2>; interrupt-controller; reg = <0 0xe61c0000 0 0x200>; @@ -90,7 +163,7 @@ }; irqc1: interrupt-controller@e61c0200 { - compatible = "renesas,irqc"; + compatible = "renesas,irqc-r8a73a4", "renesas,irqc"; #interrupt-cells = <2>; interrupt-controller; reg = <0 0xe61c0200 0 0x200>; @@ -122,50 +195,8 @@ <0 57 IRQ_TYPE_LEVEL_HIGH>; }; - dmac: dma-multiplexer@0 { - compatible = "renesas,shdma-mux"; - #dma-cells = <1>; - dma-channels = <20>; - dma-requests = <256>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - dma0: dma-controller@e6700020 { - compatible = "renesas,shdma-r8a73a4"; - reg = <0 0xe6700020 0 0x89e0>; - interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH - 0 200 IRQ_TYPE_LEVEL_HIGH - 0 201 IRQ_TYPE_LEVEL_HIGH - 0 202 IRQ_TYPE_LEVEL_HIGH - 0 203 IRQ_TYPE_LEVEL_HIGH - 0 204 IRQ_TYPE_LEVEL_HIGH - 0 205 IRQ_TYPE_LEVEL_HIGH - 0 206 IRQ_TYPE_LEVEL_HIGH - 0 207 IRQ_TYPE_LEVEL_HIGH - 0 208 IRQ_TYPE_LEVEL_HIGH - 0 209 IRQ_TYPE_LEVEL_HIGH - 0 210 IRQ_TYPE_LEVEL_HIGH - 0 211 IRQ_TYPE_LEVEL_HIGH - 0 212 IRQ_TYPE_LEVEL_HIGH - 0 213 IRQ_TYPE_LEVEL_HIGH - 0 214 IRQ_TYPE_LEVEL_HIGH - 0 215 IRQ_TYPE_LEVEL_HIGH - 0 216 IRQ_TYPE_LEVEL_HIGH - 0 217 IRQ_TYPE_LEVEL_HIGH - 0 218 IRQ_TYPE_LEVEL_HIGH - 0 219 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "error", - "ch0", "ch1", "ch2", "ch3", - "ch4", "ch5", "ch6", "ch7", - "ch8", "ch9", "ch10", "ch11", - "ch12", "ch13", "ch14", "ch15", - "ch16", "ch17", "ch18", "ch19"; - }; - }; - thermal@e61f0000 { - compatible = "renesas,rcar-thermal"; + compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal"; reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; @@ -174,7 +205,7 @@ i2c0: i2c@e6500000 { #address-cells = <1>; #size-cells = <0>; - compatible = "renesas,rmobile-iic"; + compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; reg = <0 0xe6500000 0 0x428>; interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -183,7 +214,7 @@ i2c1: i2c@e6510000 { #address-cells = <1>; #size-cells = <0>; - compatible = "renesas,rmobile-iic"; + compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; reg = <0 0xe6510000 0 0x428>; interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -192,7 +223,7 @@ i2c2: i2c@e6520000 { #address-cells = <1>; #size-cells = <0>; - compatible = "renesas,rmobile-iic"; + compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; reg = <0 0xe6520000 0 0x428>; interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -201,7 +232,7 @@ i2c3: i2c@e6530000 { #address-cells = <1>; #size-cells = <0>; - compatible = "renesas,rmobile-iic"; + compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; reg = <0 0xe6530000 0 0x428>; interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -210,25 +241,16 @@ i2c4: i2c@e6540000 { #address-cells = <1>; #size-cells = <0>; - compatible = "renesas,rmobile-iic"; + compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; reg = <0 0xe6540000 0 0x428>; interrupts = <0 178 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; - i2c5: i2c@e60b0000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "renesas,rmobile-iic"; - reg = <0 0xe60b0000 0 0x428>; - interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - i2c6: i2c@e6550000 { #address-cells = <1>; #size-cells = <0>; - compatible = "renesas,rmobile-iic"; + compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; reg = <0 0xe6550000 0 0x428>; interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -237,7 +259,7 @@ i2c7: i2c@e6560000 { #address-cells = <1>; #size-cells = <0>; - compatible = "renesas,rmobile-iic"; + compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; reg = <0 0xe6560000 0 0x428>; interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -246,12 +268,26 @@ i2c8: i2c@e6570000 { #address-cells = <1>; #size-cells = <0>; - compatible = "renesas,rmobile-iic"; + compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; reg = <0 0xe6570000 0 0x428>; interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; + scifb0: serial@e6c20000 { + compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; + reg = <0 0xe6c20000 0 0x100>; + interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + scifb1: serial@e6c30000 { + compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; + reg = <0 0xe6c30000 0 0x100>; + interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + scifa0: serial@e6c40000 { compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; reg = <0 0xe6c40000 0 0x100>; @@ -266,73 +302,20 @@ status = "disabled"; }; - scifb2: serial@e6c20000 { - compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; - reg = <0 0xe6c20000 0 0x100>; - interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - scifb3: serial@e6c30000 { - compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; - reg = <0 0xe6c30000 0 0x100>; - interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - scifb4: serial@e6ce0000 { + scifb2: serial@e6ce0000 { compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; reg = <0 0xe6ce0000 0 0x100>; interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; - scifb5: serial@e6cf0000 { + scifb3: serial@e6cf0000 { compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; reg = <0 0xe6cf0000 0 0x100>; interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; - mmcif0: mmc@ee200000 { - compatible = "renesas,sh-mmcif"; - reg = <0 0xee200000 0 0x80>; - interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; - reg-io-width = <4>; - status = "disabled"; - }; - - mmcif1: mmc@ee220000 { - compatible = "renesas,sh-mmcif"; - reg = <0 0xee220000 0 0x80>; - interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; - reg-io-width = <4>; - status = "disabled"; - }; - - pfc: pfc@e6050000 { - compatible = "renesas,pfc-r8a73a4"; - reg = <0 0xe6050000 0 0x9000>; - gpio-controller; - #gpio-cells = <2>; - interrupts-extended = - <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>, - <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>, - <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>, - <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>, - <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>, - <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>, - <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>, - <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>, - <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>, - <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>, - <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>, - <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>, - <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>, - <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>, - <&irqc1 24 0>, <&irqc1 25 0>; - }; - sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a73a4"; reg = <0 0xee100000 0 0x100>; @@ -356,4 +339,32 @@ cap-sd-highspeed; status = "disabled"; }; + + mmcif0: mmc@ee200000 { + compatible = "renesas,sh-mmcif"; + reg = <0 0xee200000 0 0x80>; + interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <4>; + status = "disabled"; + }; + + mmcif1: mmc@ee220000 { + compatible = "renesas,sh-mmcif"; + reg = <0 0xee220000 0 0x80>; + interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; + reg-io-width = <4>; + status = "disabled"; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, + <0 0xf1002000 0 0x1000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; }; diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts deleted file mode 100644 index ee9e7d5c97a9..000000000000 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts +++ /dev/null @@ -1,283 +0,0 @@ -/* - * Reference Device Tree Source for the armadillo 800 eva board - * - * Copyright (C) 2012 Renesas Solutions Corp. - * - * This file is licensed under the terms of the GNU General Public License - * version 2. This program is licensed "as is" without any warranty of any - * kind, whether express or implied. - */ - -/dts-v1/; -#include "r8a7740.dtsi" -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/input/input.h> -#include <dt-bindings/interrupt-controller/irq.h> -#include <dt-bindings/pwm/pwm.h> - -/ { - model = "armadillo 800 eva reference"; - compatible = "renesas,armadillo800eva-reference", "renesas,r8a7740"; - - aliases { - serial1 = &scifa1; - }; - - chosen { - bootargs = "console=tty0 console=ttySC1,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw"; - }; - - memory { - device_type = "memory"; - reg = <0x40000000 0x20000000>; - }; - - reg_3p3v: regulator@0 { - compatible = "regulator-fixed"; - regulator-name = "fixed-3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; - }; - - vcc_sdhi0: regulator@1 { - compatible = "regulator-fixed"; - - regulator-name = "SDHI0 Vcc"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - - gpio = <&pfc 75 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; - - vccq_sdhi0: regulator@2 { - compatible = "regulator-gpio"; - - regulator-name = "SDHI0 VccQ"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc_sdhi0>; - - enable-gpio = <&pfc 74 GPIO_ACTIVE_HIGH>; - gpios = <&pfc 17 GPIO_ACTIVE_HIGH>; - states = <3300000 0 - 1800000 1>; - - enable-active-high; - }; - - reg_5p0v: regulator@3 { - compatible = "regulator-fixed"; - regulator-name = "fixed-5.0V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - regulator-boot-on; - }; - - gpio-keys { - compatible = "gpio-keys"; - - power-key { - gpios = <&pfc 99 GPIO_ACTIVE_LOW>; - linux,code = <KEY_POWER>; - label = "SW3"; - gpio-key,wakeup; - }; - - back-key { - gpios = <&pfc 100 GPIO_ACTIVE_LOW>; - linux,code = <KEY_BACK>; - label = "SW4"; - }; - - menu-key { - gpios = <&pfc 97 GPIO_ACTIVE_LOW>; - linux,code = <KEY_MENU>; - label = "SW5"; - }; - - home-key { - gpios = <&pfc 98 GPIO_ACTIVE_LOW>; - linux,code = <KEY_HOME>; - label = "SW6"; - }; - }; - - leds { - compatible = "gpio-leds"; - led3 { - gpios = <&pfc 102 GPIO_ACTIVE_HIGH>; - label = "LED3"; - }; - led4 { - gpios = <&pfc 111 GPIO_ACTIVE_HIGH>; - label = "LED4"; - }; - led5 { - gpios = <&pfc 110 GPIO_ACTIVE_HIGH>; - label = "LED5"; - }; - led6 { - gpios = <&pfc 177 GPIO_ACTIVE_HIGH>; - label = "LED6"; - }; - }; - - i2c2: i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "i2c-gpio"; - gpios = <&pfc 208 GPIO_ACTIVE_HIGH /* sda */ - &pfc 91 GPIO_ACTIVE_HIGH /* scl */ - >; - i2c-gpio,delay-us = <5>; - }; - - backlight { - compatible = "pwm-backlight"; - pwms = <&tpu 2 33333 PWM_POLARITY_INVERTED>; - brightness-levels = <0 1 2 4 8 16 32 64 128 255>; - default-brightness-level = <9>; - pinctrl-0 = <&backlight_pins>; - pinctrl-names = "default"; - power-supply = <®_5p0v>; - enable-gpios = <&pfc 61 GPIO_ACTIVE_HIGH>; - }; - - sound { - compatible = "simple-audio-card"; - - simple-audio-card,format = "i2s"; - - simple-audio-card,cpu { - sound-dai = <&sh_fsi2 0>; - bitclock-inversion; - }; - - simple-audio-card,codec { - sound-dai = <&wm8978>; - bitclock-master; - frame-master; - system-clock-frequency = <12288000>; - }; - }; -}; - -ðer { - pinctrl-0 = <ðer_pins>; - pinctrl-names = "default"; - - phy-handle = <&phy0>; - status = "ok"; - - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&i2c0 { - status = "okay"; - touchscreen@55 { - compatible = "sitronix,st1232"; - reg = <0x55>; - interrupt-parent = <&irqpin1>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - pinctrl-0 = <&st1232_pins>; - pinctrl-names = "default"; - gpios = <&pfc 166 GPIO_ACTIVE_LOW>; - }; - - wm8978: wm8978@1a { - #sound-dai-cells = <0>; - compatible = "wlf,wm8978"; - reg = <0x1a>; - }; -}; - -&i2c2 { - status = "okay"; - rtc@30 { - compatible = "sii,s35390a"; - reg = <0x30>; - }; -}; - -&pfc { - ether_pins: ether { - renesas,groups = "gether_mii", "gether_int"; - renesas,function = "gether"; - }; - - scifa1_pins: serial1 { - renesas,groups = "scifa1_data"; - renesas,function = "scifa1"; - }; - - st1232_pins: touchscreen { - renesas,groups = "intc_irq10"; - renesas,function = "intc"; - }; - - backlight_pins: backlight { - renesas,groups = "tpu0_to2_1"; - renesas,function = "tpu0"; - }; - - mmc0_pins: mmc0 { - renesas,groups = "mmc0_data8_1", "mmc0_ctrl_1"; - renesas,function = "mmc0"; - }; - - sdhi0_pins: sd0 { - renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp"; - renesas,function = "sdhi0"; - }; - - fsia_pins: sounda { - renesas,groups = "fsia_sclk_in", "fsia_mclk_out", - "fsia_data_in_1", "fsia_data_out_0"; - renesas,function = "fsia"; - }; -}; - -&tpu { - status = "okay"; -}; - -&mmcif0 { - pinctrl-0 = <&mmc0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <®_3p3v>; - bus-width = <8>; - non-removable; - status = "okay"; -}; - -&scifa1 { - pinctrl-0 = <&scifa1_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&sdhi0 { - pinctrl-0 = <&sdhi0_pins>; - pinctrl-names = "default"; - - vmmc-supply = <&vcc_sdhi0>; - vqmmc-supply = <&vccq_sdhi0>; - bus-width = <4>; - cd-gpios = <&pfc 167 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&sh_fsi2 { - pinctrl-0 = <&fsia_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts index a06a11e1a840..d4af4d86c6b0 100644 --- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts +++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts @@ -10,17 +10,296 @@ /dts-v1/; #include "r8a7740.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pwm/pwm.h> / { model = "armadillo 800 eva"; - compatible = "renesas,armadillo800eva"; + compatible = "renesas,armadillo800eva", "renesas,r8a7740"; + + aliases { + serial1 = &scifa1; + }; chosen { bootargs = "console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw"; + stdout-path = &scifa1; }; memory { device_type = "memory"; reg = <0x40000000 0x20000000>; }; + + reg_3p3v: regulator@0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vcc_sdhi0: regulator@1 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pfc 75 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi0: regulator@2 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_sdhi0>; + + enable-gpio = <&pfc 74 GPIO_ACTIVE_HIGH>; + gpios = <&pfc 17 GPIO_ACTIVE_HIGH>; + states = <3300000 0 + 1800000 1>; + + enable-active-high; + }; + + reg_5p0v: regulator@3 { + compatible = "regulator-fixed"; + regulator-name = "fixed-5.0V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + + keyboard { + compatible = "gpio-keys"; + + power-key { + gpios = <&pfc 99 GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + label = "SW3"; + gpio-key,wakeup; + }; + + back-key { + gpios = <&pfc 100 GPIO_ACTIVE_LOW>; + linux,code = <KEY_BACK>; + label = "SW4"; + }; + + menu-key { + gpios = <&pfc 97 GPIO_ACTIVE_LOW>; + linux,code = <KEY_MENU>; + label = "SW5"; + }; + + home-key { + gpios = <&pfc 98 GPIO_ACTIVE_LOW>; + linux,code = <KEY_HOME>; + label = "SW6"; + }; + }; + + leds { + compatible = "gpio-leds"; + led3 { + gpios = <&pfc 102 GPIO_ACTIVE_HIGH>; + label = "LED3"; + }; + led4 { + gpios = <&pfc 111 GPIO_ACTIVE_HIGH>; + label = "LED4"; + }; + led5 { + gpios = <&pfc 110 GPIO_ACTIVE_HIGH>; + label = "LED5"; + }; + led6 { + gpios = <&pfc 177 GPIO_ACTIVE_HIGH>; + label = "LED6"; + }; + }; + + i2c2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + gpios = <&pfc 208 GPIO_ACTIVE_HIGH /* sda */ + &pfc 91 GPIO_ACTIVE_HIGH /* scl */ + >; + i2c-gpio,delay-us = <5>; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&tpu 2 33333 PWM_POLARITY_INVERTED>; + brightness-levels = <0 1 2 4 8 16 32 64 128 255>; + default-brightness-level = <9>; + pinctrl-0 = <&backlight_pins>; + pinctrl-names = "default"; + power-supply = <®_5p0v>; + enable-gpios = <&pfc 61 GPIO_ACTIVE_HIGH>; + }; + + sound { + compatible = "simple-audio-card"; + + simple-audio-card,format = "i2s"; + + simple-audio-card,cpu { + sound-dai = <&sh_fsi2 0>; + bitclock-inversion; + }; + + simple-audio-card,codec { + sound-dai = <&wm8978>; + bitclock-master; + frame-master; + system-clock-frequency = <12288000>; + }; + }; +}; + +ðer { + pinctrl-0 = <ðer_pins>; + pinctrl-names = "default"; + + phy-handle = <&phy0>; + status = "ok"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&extal1_clk { + clock-frequency = <25000000>; +}; +&extal2_clk { + clock-frequency = <48000000>; +}; +&fsibck_clk { + clock-frequency = <12288000>; +}; +&cpg_clocks { + renesas,mode = <0x05>; /* MD_CK0 | MD_CK2 */ +}; + +&cmt1 { + status = "ok"; +}; + +&i2c0 { + status = "okay"; + touchscreen@55 { + compatible = "sitronix,st1232"; + reg = <0x55>; + interrupt-parent = <&irqpin1>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&st1232_pins>; + pinctrl-names = "default"; + gpios = <&pfc 166 GPIO_ACTIVE_LOW>; + }; + + wm8978: wm8978@1a { + #sound-dai-cells = <0>; + compatible = "wlf,wm8978"; + reg = <0x1a>; + }; +}; + +&i2c2 { + status = "okay"; + rtc@30 { + compatible = "sii,s35390a"; + reg = <0x30>; + }; +}; + +&pfc { + ether_pins: ether { + renesas,groups = "gether_mii", "gether_int"; + renesas,function = "gether"; + }; + + scifa1_pins: serial1 { + renesas,groups = "scifa1_data"; + renesas,function = "scifa1"; + }; + + st1232_pins: touchscreen { + renesas,groups = "intc_irq10"; + renesas,function = "intc"; + }; + + backlight_pins: backlight { + renesas,groups = "tpu0_to2_1"; + renesas,function = "tpu0"; + }; + + mmc0_pins: mmc0 { + renesas,groups = "mmc0_data8_1", "mmc0_ctrl_1"; + renesas,function = "mmc0"; + }; + + sdhi0_pins: sd0 { + renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_wp"; + renesas,function = "sdhi0"; + }; + + fsia_pins: sounda { + renesas,groups = "fsia_sclk_in", "fsia_mclk_out", + "fsia_data_in_1", "fsia_data_out_0"; + renesas,function = "fsia"; + }; +}; + +&tpu { + status = "okay"; +}; + +&mmcif0 { + pinctrl-0 = <&mmc0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <®_3p3v>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&scifa1 { + pinctrl-0 = <&scifa1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + bus-width = <4>; + cd-gpios = <&pfc 167 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&sh_fsi2 { + pinctrl-0 = <&fsia_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&tmu0 { + status = "okay"; }; diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index bda18fb3d9e5..a8a674bafa67 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -10,6 +10,7 @@ /include/ "skeleton.dtsi" +#include <dt-bindings/clock/r8a7740-clock.h> #include <dt-bindings/interrupt-controller/irq.h> / { @@ -40,6 +41,18 @@ interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; }; + cmt1: timer@e6138000 { + compatible = "renesas,cmt-48-r8a7740", "renesas,cmt-48"; + reg = <0xe6138000 0x170>; + interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7740_CLK_CMT1>; + clock-names = "fck"; + + renesas,channels-mask = <0x3f>; + + status = "disabled"; + }; + /* irqpin0: IRQ0 - IRQ7 */ irqpin0: irqpin@e6900000 { compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin"; @@ -58,6 +71,7 @@ 0 149 IRQ_TYPE_LEVEL_HIGH 0 149 IRQ_TYPE_LEVEL_HIGH 0 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7740_CLK_INTCA>; }; /* irqpin1: IRQ8 - IRQ15 */ @@ -78,6 +92,7 @@ 0 149 IRQ_TYPE_LEVEL_HIGH 0 149 IRQ_TYPE_LEVEL_HIGH 0 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7740_CLK_INTCA>; }; /* irqpin2: IRQ16 - IRQ23 */ @@ -98,6 +113,7 @@ 0 149 IRQ_TYPE_LEVEL_HIGH 0 149 IRQ_TYPE_LEVEL_HIGH 0 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7740_CLK_INTCA>; }; /* irqpin3: IRQ24 - IRQ31 */ @@ -118,6 +134,7 @@ 0 149 IRQ_TYPE_LEVEL_HIGH 0 149 IRQ_TYPE_LEVEL_HIGH 0 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7740_CLK_INTCA>; }; ether: ethernet@e9a00000 { @@ -125,7 +142,7 @@ reg = <0xe9a00000 0x800>, <0xe9a01800 0x800>; interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; - /* clocks = <&mstp3_clks R8A7740_CLK_GETHER>; */ + clocks = <&mstp3_clks R8A7740_CLK_GETHER>; phy-mode = "mii"; #address-cells = <1>; #size-cells = <0>; @@ -141,6 +158,7 @@ 0 202 IRQ_TYPE_LEVEL_HIGH 0 203 IRQ_TYPE_LEVEL_HIGH 0 204 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7740_CLK_IIC0>; status = "disabled"; }; @@ -153,6 +171,7 @@ 0 71 IRQ_TYPE_LEVEL_HIGH 0 72 IRQ_TYPE_LEVEL_HIGH 0 73 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7740_CLK_IIC1>; status = "disabled"; }; @@ -160,6 +179,8 @@ compatible = "renesas,scifa-r8a7740", "renesas,scifa"; reg = <0xe6c40000 0x100>; interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7740_CLK_SCIFA0>; + clock-names = "sci_ick"; status = "disabled"; }; @@ -167,6 +188,8 @@ compatible = "renesas,scifa-r8a7740", "renesas,scifa"; reg = <0xe6c50000 0x100>; interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7740_CLK_SCIFA1>; + clock-names = "sci_ick"; status = "disabled"; }; @@ -174,6 +197,8 @@ compatible = "renesas,scifa-r8a7740", "renesas,scifa"; reg = <0xe6c60000 0x100>; interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7740_CLK_SCIFA2>; + clock-names = "sci_ick"; status = "disabled"; }; @@ -181,6 +206,8 @@ compatible = "renesas,scifa-r8a7740", "renesas,scifa"; reg = <0xe6c70000 0x100>; interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7740_CLK_SCIFA3>; + clock-names = "sci_ick"; status = "disabled"; }; @@ -188,6 +215,8 @@ compatible = "renesas,scifa-r8a7740", "renesas,scifa"; reg = <0xe6c80000 0x100>; interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7740_CLK_SCIFA4>; + clock-names = "sci_ick"; status = "disabled"; }; @@ -195,6 +224,8 @@ compatible = "renesas,scifa-r8a7740", "renesas,scifa"; reg = <0xe6cb0000 0x100>; interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7740_CLK_SCIFA5>; + clock-names = "sci_ick"; status = "disabled"; }; @@ -202,6 +233,8 @@ compatible = "renesas,scifa-r8a7740", "renesas,scifa"; reg = <0xe6cc0000 0x100>; interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7740_CLK_SCIFA6>; + clock-names = "sci_ick"; status = "disabled"; }; @@ -209,6 +242,8 @@ compatible = "renesas,scifa-r8a7740", "renesas,scifa"; reg = <0xe6cd0000 0x100>; interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7740_CLK_SCIFA7>; + clock-names = "sci_ick"; status = "disabled"; }; @@ -216,6 +251,8 @@ compatible = "renesas,scifb-r8a7740", "renesas,scifb"; reg = <0xe6c30000 0x100>; interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7740_CLK_SCIFB>; + clock-names = "sci_ick"; status = "disabled"; }; @@ -239,6 +276,7 @@ tpu: pwm@e6600000 { compatible = "renesas,tpu-r8a7740", "renesas,tpu"; reg = <0xe6600000 0x100>; + clocks = <&mstp3_clks R8A7740_CLK_TPU0>; status = "disabled"; #pwm-cells = <3>; }; @@ -248,6 +286,7 @@ reg = <0xe6bd0000 0x100>; interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH 0 57 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7740_CLK_MMC>; status = "disabled"; }; @@ -257,6 +296,7 @@ interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH 0 118 IRQ_TYPE_LEVEL_HIGH 0 119 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7740_CLK_SDHI0>; cap-sd-highspeed; cap-sdio-irq; status = "disabled"; @@ -268,6 +308,7 @@ interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH 0 122 IRQ_TYPE_LEVEL_HIGH 0 123 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7740_CLK_SDHI1>; cap-sd-highspeed; cap-sdio-irq; status = "disabled"; @@ -279,6 +320,7 @@ interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH 0 126 IRQ_TYPE_LEVEL_HIGH 0 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp4_clks R8A7740_CLK_SDHI2>; cap-sd-highspeed; cap-sdio-irq; status = "disabled"; @@ -289,6 +331,216 @@ compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2"; reg = <0xfe1f0000 0x400>; interrupts = <0 9 0x4>; + clocks = <&mstp3_clks R8A7740_CLK_FSI>; + status = "disabled"; + }; + + tmu0: timer@fff80000 { + compatible = "renesas,tmu-r8a7740", "renesas,tmu"; + reg = <0xfff80000 0x2c>; + interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>, + <0 199 IRQ_TYPE_LEVEL_HIGH>, + <0 200 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7740_CLK_TMU0>; + clock-names = "fck"; + + #renesas,channels = <3>; + status = "disabled"; }; + + tmu1: timer@fff90000 { + compatible = "renesas,tmu-r8a7740", "renesas,tmu"; + reg = <0xfff90000 0x2c>; + interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>, + <0 171 IRQ_TYPE_LEVEL_HIGH>, + <0 172 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7740_CLK_TMU1>; + clock-names = "fck"; + + #renesas,channels = <3>; + + status = "disabled"; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* External root clock */ + extalr_clk: extalr_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "extalr"; + }; + extal1_clk: extal1_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "extal1"; + }; + extal2_clk: extal2_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "extal2"; + }; + dv_clk: dv_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + clock-output-names = "dv"; + }; + fsiack_clk: fsiack_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "fsiack"; + }; + fsibck_clk: fsibck_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "fsibck"; + }; + + /* Special CPG clocks */ + cpg_clocks: cpg_clocks@e6150000 { + compatible = "renesas,r8a7740-cpg-clocks"; + reg = <0xe6150000 0x10000>; + clocks = <&extal1_clk>, <&extalr_clk>; + #clock-cells = <1>; + clock-output-names = "system", "pllc0", "pllc1", + "pllc2", "r", + "usb24s", + "i", "zg", "b", "m1", "hp", + "hpp", "usbp", "s", "zb", "m3", + "cp"; + }; + + /* Variable factor clocks (DIV6) */ + sub_clk: sub_clk@e6150080 { + compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; + reg = <0xe6150080 4>; + clocks = <&pllc1_div2_clk>; + #clock-cells = <0>; + clock-output-names = "sub"; + }; + + /* Fixed factor clocks */ + pllc1_div2_clk: pllc1_div2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7740_CLK_PLLC1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "pllc1_div2"; + }; + extal1_div2_clk: extal1_div2_clk { + compatible = "fixed-factor-clock"; + clocks = <&extal1_clk>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "extal1_div2"; + }; + + /* Gate clocks */ + subck_clks: subck_clks@e6150080 { + compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xe6150080 4>; + clocks = <&sub_clk>, <&sub_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7740_CLK_SUBCK R8A7740_CLK_SUBCK2 + >; + clock-output-names = + "subck", "subck2"; + }; + mstp1_clks: mstp1_clks@e6150134 { + compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xe6150134 4>, <0xe6150038 4>; + clocks = <&cpg_clocks R8A7740_CLK_S>, + <&cpg_clocks R8A7740_CLK_S>, <&sub_clk>, + <&cpg_clocks R8A7740_CLK_B>, + <&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>, + <&cpg_clocks R8A7740_CLK_B>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7740_CLK_CEU21 R8A7740_CLK_CEU20 R8A7740_CLK_TMU0 + R8A7740_CLK_LCDC1 R8A7740_CLK_IIC0 R8A7740_CLK_TMU1 + R8A7740_CLK_LCDC0 + >; + clock-output-names = + "ceu21", "ceu20", "tmu0", "lcdc1", "iic0", + "tmu1", "lcdc0"; + }; + mstp2_clks: mstp2_clks@e6150138 { + compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xe6150138 4>, <0xe6150040 4>; + clocks = <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>, + <&sub_clk>, <&cpg_clocks R8A7740_CLK_HP>, + <&cpg_clocks R8A7740_CLK_HP>, + <&cpg_clocks R8A7740_CLK_HP>, + <&cpg_clocks R8A7740_CLK_HP>, + <&sub_clk>, <&sub_clk>, <&sub_clk>, + <&sub_clk>, <&sub_clk>, <&sub_clk>, + <&sub_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7740_CLK_SCIFA6 R8A7740_CLK_INTCA + R8A7740_CLK_SCIFA7 + R8A7740_CLK_DMAC1 R8A7740_CLK_DMAC2 + R8A7740_CLK_DMAC3 R8A7740_CLK_USBDMAC + R8A7740_CLK_SCIFA5 R8A7740_CLK_SCIFB + R8A7740_CLK_SCIFA0 R8A7740_CLK_SCIFA1 + R8A7740_CLK_SCIFA2 R8A7740_CLK_SCIFA3 + R8A7740_CLK_SCIFA4 + >; + clock-output-names = + "scifa6", "intca", + "scifa7", "dmac1", "dmac2", "dmac3", + "usbdmac", "scifa5", "scifb", "scifa0", "scifa1", + "scifa2", "scifa3", "scifa4"; + }; + mstp3_clks: mstp3_clks@e615013c { + compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xe615013c 4>, <0xe6150048 4>; + clocks = <&cpg_clocks R8A7740_CLK_R>, + <&cpg_clocks R8A7740_CLK_HP>, + <&sub_clk>, + <&cpg_clocks R8A7740_CLK_HP>, + <&cpg_clocks R8A7740_CLK_HP>, + <&cpg_clocks R8A7740_CLK_HP>, + <&cpg_clocks R8A7740_CLK_HP>, + <&cpg_clocks R8A7740_CLK_HP>, + <&cpg_clocks R8A7740_CLK_HP>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7740_CLK_CMT1 R8A7740_CLK_FSI R8A7740_CLK_IIC1 + R8A7740_CLK_USBF R8A7740_CLK_SDHI0 R8A7740_CLK_SDHI1 + R8A7740_CLK_MMC R8A7740_CLK_GETHER R8A7740_CLK_TPU0 + >; + clock-output-names = + "cmt1", "fsi", "iic1", "usbf", "sdhi0", "sdhi1", + "mmc", "gether", "tpu0"; + }; + mstp4_clks: mstp4_clks@e6150140 { + compatible = "renesas,r8a7740-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0xe6150140 4>, <0xe615004c 4>; + clocks = <&cpg_clocks R8A7740_CLK_HP>, + <&cpg_clocks R8A7740_CLK_HP>, + <&cpg_clocks R8A7740_CLK_HP>, + <&cpg_clocks R8A7740_CLK_HP>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7740_CLK_USBH R8A7740_CLK_SDHI2 + R8A7740_CLK_USBFUNC R8A7740_CLK_USBPHY + >; + clock-output-names = + "usbhost", "sdhi2", "usbfunc", "usphy"; + }; + }; }; diff --git a/arch/arm/boot/dts/r8a7778-bockw-reference.dts b/arch/arm/boot/dts/r8a7778-bockw-reference.dts index 3342c74c5de8..04c0c37bb784 100644 --- a/arch/arm/boot/dts/r8a7778-bockw-reference.dts +++ b/arch/arm/boot/dts/r8a7778-bockw-reference.dts @@ -28,7 +28,8 @@ }; chosen { - bootargs = "console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw"; + bootargs = "ignore_loglevel root=/dev/nfs ip=dhcp rw"; + stdout-path = &scif0; }; memory { @@ -73,6 +74,10 @@ status = "okay"; }; +&tmu0 { + status = "okay"; +}; + &pfc { scif0_pins: serial0 { renesas,groups = "scif0_data_a", "scif0_ctrl"; diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index ecfdf4b01b5a..ef8533910029 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -23,8 +23,14 @@ interrupt-parent = <&gic>; cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; compatible = "arm,cortex-a9"; + reg = <0>; + clock-frequency = <800000000>; }; }; @@ -156,6 +162,42 @@ status = "disabled"; }; + tmu0: timer@ffd80000 { + compatible = "renesas,tmu-r8a7778", "renesas,tmu"; + reg = <0xffd80000 0x30>; + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, + <0 33 IRQ_TYPE_LEVEL_HIGH>, + <0 34 IRQ_TYPE_LEVEL_HIGH>; + + #renesas,channels = <3>; + + status = "disabled"; + }; + + tmu1: timer@ffd81000 { + compatible = "renesas,tmu-r8a7778", "renesas,tmu"; + reg = <0xffd81000 0x30>; + interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>, + <0 37 IRQ_TYPE_LEVEL_HIGH>, + <0 38 IRQ_TYPE_LEVEL_HIGH>; + + #renesas,channels = <3>; + + status = "disabled"; + }; + + tmu2: timer@ffd82000 { + compatible = "renesas,tmu-r8a7778", "renesas,tmu"; + reg = <0xffd82000 0x30>; + interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>, + <0 41 IRQ_TYPE_LEVEL_HIGH>, + <0 42 IRQ_TYPE_LEVEL_HIGH>; + + #renesas,channels = <3>; + + status = "disabled"; + }; + scif0: serial@ffe40000 { compatible = "renesas,scif-r8a7778", "renesas,scif"; reg = <0xffe40000 0x100>; @@ -209,8 +251,6 @@ compatible = "renesas,sdhi-r8a7778"; reg = <0xffe4c000 0x100>; interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>; - cap-sd-highspeed; - cap-sdio-irq; status = "disabled"; }; @@ -218,8 +258,6 @@ compatible = "renesas,sdhi-r8a7778"; reg = <0xffe4d000 0x100>; interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; - cap-sd-highspeed; - cap-sdio-irq; status = "disabled"; }; @@ -227,8 +265,6 @@ compatible = "renesas,sdhi-r8a7778"; reg = <0xffe4f000 0x100>; interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - cap-sd-highspeed; - cap-sdio-irq; status = "disabled"; }; diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts index 5745555df943..e83d40e24bcd 100644 --- a/arch/arm/boot/dts/r8a7779-marzen.dts +++ b/arch/arm/boot/dts/r8a7779-marzen.dts @@ -25,6 +25,7 @@ chosen { bootargs = "console=ttySC2,115200 ignore_loglevel root=/dev/nfs ip=on"; + stdout-path = &scif2; }; memory { @@ -68,6 +69,78 @@ gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>; }; }; + + vga-encoder { + compatible = "adi,adv7123"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + vga_enc_in: endpoint { + remote-endpoint = <&du_out_rgb0>; + }; + }; + port@1 { + reg = <1>; + vga_enc_out: endpoint { + remote-endpoint = <&vga_in>; + }; + }; + }; + }; + + vga { + compatible = "vga-connector"; + + port { + vga_in: endpoint { + remote-endpoint = <&vga_enc_out>; + }; + }; + }; + + lvds-encoder { + compatible = "thine,thc63lvdm83d"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds_enc_in: endpoint { + remote-endpoint = <&du_out_rgb1>; + }; + }; + port@1 { + reg = <1>; + lvds_connector: endpoint { + }; + }; + }; + }; +}; + +&du { + pinctrl-0 = <&du_pins>; + pinctrl-names = "default"; + status = "okay"; + + ports { + port@0 { + endpoint { + remote-endpoint = <&vga_enc_in>; + }; + }; + port@1 { + endpoint { + remote-endpoint = <&lvds_enc_in>; + }; + }; + }; }; &irqpin0 { @@ -78,7 +151,22 @@ clock-frequency = <31250000>; }; +&tmu0 { + status = "okay"; +}; + &pfc { + du_pins: du { + du0 { + renesas,groups = "du0_rgb888", "du0_sync_1", "du0_clk_out_0"; + renesas,function = "du0"; + }; + du1 { + renesas,groups = "du1_rgb666", "du1_sync_1", "du1_clk_out"; + renesas,function = "du1"; + }; + }; + lan0_pins: lan0 { intc { renesas,groups = "intc_irq1_b"; diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi index 58d0d952d60e..ede9a29e4bc6 100644 --- a/arch/arm/boot/dts/r8a7779.dtsi +++ b/arch/arm/boot/dts/r8a7779.dtsi @@ -199,7 +199,6 @@ scif0: serial@ffe40000 { compatible = "renesas,scif-r8a7779", "renesas,scif"; reg = <0xffe40000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg_clocks R8A7779_CLK_P>; clock-names = "sci_ick"; @@ -209,7 +208,6 @@ scif1: serial@ffe41000 { compatible = "renesas,scif-r8a7779", "renesas,scif"; reg = <0xffe41000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg_clocks R8A7779_CLK_P>; clock-names = "sci_ick"; @@ -219,7 +217,6 @@ scif2: serial@ffe42000 { compatible = "renesas,scif-r8a7779", "renesas,scif"; reg = <0xffe42000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg_clocks R8A7779_CLK_P>; clock-names = "sci_ick"; @@ -229,7 +226,6 @@ scif3: serial@ffe43000 { compatible = "renesas,scif-r8a7779", "renesas,scif"; reg = <0xffe43000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg_clocks R8A7779_CLK_P>; clock-names = "sci_ick"; @@ -239,7 +235,6 @@ scif4: serial@ffe44000 { compatible = "renesas,scif-r8a7779", "renesas,scif"; reg = <0xffe44000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg_clocks R8A7779_CLK_P>; clock-names = "sci_ick"; @@ -249,7 +244,6 @@ scif5: serial@ffe45000 { compatible = "renesas,scif-r8a7779", "renesas,scif"; reg = <0xffe45000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>; clocks = <&cpg_clocks R8A7779_CLK_P>; clock-names = "sci_ick"; @@ -262,12 +256,54 @@ }; thermal@ffc48000 { - compatible = "renesas,rcar-thermal"; + compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal"; reg = <0xffc48000 0x38>; }; + tmu0: timer@ffd80000 { + compatible = "renesas,tmu-r8a7779", "renesas,tmu"; + reg = <0xffd80000 0x30>; + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, + <0 33 IRQ_TYPE_LEVEL_HIGH>, + <0 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7779_CLK_TMU0>; + clock-names = "fck"; + + #renesas,channels = <3>; + + status = "disabled"; + }; + + tmu1: timer@ffd81000 { + compatible = "renesas,tmu-r8a7779", "renesas,tmu"; + reg = <0xffd81000 0x30>; + interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>, + <0 37 IRQ_TYPE_LEVEL_HIGH>, + <0 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7779_CLK_TMU1>; + clock-names = "fck"; + + #renesas,channels = <3>; + + status = "disabled"; + }; + + tmu2: timer@ffd82000 { + compatible = "renesas,tmu-r8a7779", "renesas,tmu"; + reg = <0xffd82000 0x30>; + interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>, + <0 41 IRQ_TYPE_LEVEL_HIGH>, + <0 42 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp0_clks R8A7779_CLK_TMU2>; + clock-names = "fck"; + + #renesas,channels = <3>; + + status = "disabled"; + }; + sata: sata@fc600000 { - compatible = "renesas,rcar-sata"; + compatible = "renesas,sata-r8a7779", "renesas,rcar-sata"; reg = <0xfc600000 0x2000>; interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp1_clks R8A7779_CLK_SATA>; @@ -278,8 +314,6 @@ reg = <0xffe4c000 0x100>; interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7779_CLK_SDHI0>; - cap-sd-highspeed; - cap-sdio-irq; status = "disabled"; }; @@ -288,8 +322,6 @@ reg = <0xffe4d000 0x100>; interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7779_CLK_SDHI1>; - cap-sd-highspeed; - cap-sdio-irq; status = "disabled"; }; @@ -298,8 +330,6 @@ reg = <0xffe4e000 0x100>; interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7779_CLK_SDHI2>; - cap-sd-highspeed; - cap-sdio-irq; status = "disabled"; }; @@ -308,8 +338,6 @@ reg = <0xffe4f000 0x100>; interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7779_CLK_SDHI3>; - cap-sd-highspeed; - cap-sdio-irq; status = "disabled"; }; @@ -343,6 +371,30 @@ status = "disabled"; }; + du: display@fff80000 { + compatible = "renesas,du-r8a7779"; + reg = <0 0xfff80000 0 0x40000>; + interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7779_CLK_DU>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb0: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_rgb1: endpoint { + }; + }; + }; + }; + clocks { #address-cells = <1>; #size-cells = <1>; @@ -404,10 +456,10 @@ /* Gate clocks */ mstp0_clks: clocks@ffc80030 { compatible = "renesas,r8a7779-mstp-clocks", - "renesas,cpg-mstp-clocks"; + "renesas,cpg-mstp-clocks"; reg = <0xffc80030 4>; clocks = <&cpg_clocks R8A7779_CLK_S>, - <&cpg_clocks R8A7779_CLK_P>, + <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_S>, @@ -441,7 +493,7 @@ }; mstp1_clks: clocks@ffc80034 { compatible = "renesas,r8a7779-mstp-clocks", - "renesas,cpg-mstp-clocks"; + "renesas,cpg-mstp-clocks"; reg = <0xffc80034 4>, <0xffc80044 4>; clocks = <&cpg_clocks R8A7779_CLK_P>, <&cpg_clocks R8A7779_CLK_P>, @@ -470,7 +522,7 @@ }; mstp3_clks: clocks@ffc8003c { compatible = "renesas,r8a7779-mstp-clocks", - "renesas,cpg-mstp-clocks"; + "renesas,cpg-mstp-clocks"; reg = <0xffc8003c 4>; clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>; diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index 856b4236b674..636d53bb87a2 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -9,6 +9,34 @@ * kind, whether express or implied. */ +/* + * SSI-AK4643 + * + * SW1: 1: AK4643 + * 2: CN22 + * 3: ADV7511 + * + * This command is required when Playback/Capture + * + * amixer set "LINEOUT Mixer DACL" on + * amixer set "DVC Out" 100% + * amixer set "DVC In" 100% + * + * You can use Mute + * + * amixer set "DVC Out Mute" on + * amixer set "DVC In Mute" on + * + * You can use Volume Ramp + * + * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" + * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" + * amixer set "DVC Out Ramp" on + * aplay xxx.wav & + * amixer set "DVC Out" 80% // Volume Down + * amixer set "DVC Out" 100% // Volume Up + */ + /dts-v1/; #include "r8a7790.dtsi" #include <dt-bindings/gpio/gpio.h> @@ -19,12 +47,13 @@ compatible = "renesas,lager", "renesas,r8a7790"; aliases { - serial6 = &scif0; - serial7 = &scif1; + serial6 = &scifa0; + serial7 = &scifa1; }; chosen { bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp"; + stdout-path = &scifa0; }; memory@40000000 { @@ -32,7 +61,7 @@ reg = <0 0x40000000 0 0x40000000>; }; - memory@180000000 { + memory@140000000 { device_type = "memory"; reg = <1 0x40000000 0 0xc0000000>; }; @@ -42,7 +71,7 @@ #size-cells = <1>; }; - gpio_keys { + keyboard { compatible = "gpio-keys"; button@1 { @@ -144,6 +173,73 @@ states = <3300000 1 1800000 0>; }; + + sound { + compatible = "simple-audio-card"; + + simple-audio-card,format = "left_j"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + + sndcpu: simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + }; + + sndcodec: simple-audio-card,codec { + sound-dai = <&ak4643>; + system-clock-frequency = <11289600>; + }; + }; + + vga-encoder { + compatible = "adi,adv7123"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7123_in: endpoint { + remote-endpoint = <&du_out_rgb>; + }; + }; + port@1 { + reg = <1>; + adv7123_out: endpoint { + remote-endpoint = <&vga_in>; + }; + }; + }; + }; + + vga { + compatible = "vga-connector"; + + port { + vga_in: endpoint { + remote-endpoint = <&adv7123_out>; + }; + }; + }; +}; + +&du { + pinctrl-0 = <&du_pins>; + pinctrl-names = "default"; + status = "okay"; + + ports { + port@0 { + endpoint { + remote-endpoint = <&adv7123_in>; + }; + }; + port@2 { + lvds_connector: endpoint { + }; + }; + }; }; &extal_clk { @@ -151,17 +247,14 @@ }; &pfc { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - du_pins: du { renesas,groups = "du_rgb666", "du_sync_1", "du_clk_out_0"; renesas,function = "du"; }; - scif0_pins: serial0 { - renesas,groups = "scif0_data"; - renesas,function = "scif0"; + scifa0_pins: serial0 { + renesas,groups = "scifa0_data"; + renesas,function = "scifa0"; }; ether_pins: ether { @@ -174,9 +267,9 @@ renesas,function = "intc"; }; - scif1_pins: serial1 { - renesas,groups = "scif1_data"; - renesas,function = "scif1"; + scifa1_pins: serial1 { + renesas,groups = "scifa1_data"; + renesas,function = "scifa1"; }; sdhi0_pins: sd0 { @@ -220,6 +313,11 @@ renesas,function = "iic3"; }; + hsusb_pins: hsusb { + renesas,groups = "usb0_ovc_vbus"; + renesas,function = "usb0"; + }; + usb0_pins: usb0 { renesas,groups = "usb0"; renesas,function = "usb0"; @@ -234,6 +332,21 @@ renesas,groups = "usb2"; renesas,function = "usb2"; }; + + vin1_pins: vin { + renesas,groups = "vin1_data8", "vin1_clk"; + renesas,function = "vin1"; + }; + + sound_pins: sound { + renesas,groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; + renesas,function = "ssi"; + }; + + sound_clk_pins: sound_clk { + renesas,groups = "audio_clk_a"; + renesas,function = "audio_clk"; + }; }; ðer { @@ -252,6 +365,10 @@ }; }; +&cmt0 { + status = "ok"; +}; + &mmcif1 { pinctrl-0 = <&mmc1_pins>; pinctrl-names = "default"; @@ -299,15 +416,15 @@ }; }; -&scif0 { - pinctrl-0 = <&scif0_pins>; +&scifa0 { + pinctrl-0 = <&scifa0_pins>; pinctrl-names = "default"; status = "okay"; }; -&scif1 { - pinctrl-0 = <&scif1_pins>; +&scifa1 { + pinctrl-0 = <&scifa1_pins>; pinctrl-names = "default"; status = "okay"; @@ -366,6 +483,27 @@ status = "ok"; pinctrl-0 = <&iic2_pins>; pinctrl-names = "default"; + + clock-frequency = <100000>; + + ak4643: sound-codec@12 { + compatible = "asahi-kasei,ak4643"; + #sound-dai-cells = <0>; + reg = <0x12>; + }; + + composite-in@20 { + compatible = "adi,adv7180"; + reg = <0x20>; + remote = <&vin1>; + + port { + adv7180: endpoint { + bus-width = <8>; + remote-endpoint = <&vin1ep0>; + }; + }; + }; }; &iic3 { @@ -374,7 +512,7 @@ status = "okay"; vdd_dvfs: regulator@68 { - compatible = "diasemi,da9210"; + compatible = "dlg,da9210"; reg = <0x68>; regulator-min-microvolt = <1000000>; @@ -396,8 +534,63 @@ pinctrl-names = "default"; }; +&xhci { + status = "okay"; + pinctrl-0 = <&usb2_pins>; + pinctrl-names = "default"; +}; + &pci2 { status = "okay"; pinctrl-0 = <&usb2_pins>; pinctrl-names = "default"; }; + +&hsusb { + status = "okay"; + pinctrl-0 = <&hsusb_pins>; + pinctrl-names = "default"; + renesas,enable-gpio = <&gpio5 18 GPIO_ACTIVE_HIGH>; +}; + +&usbphy { + status = "okay"; +}; + +/* composite video input */ +&vin1 { + pinctrl-0 = <&vin1_pins>; + pinctrl-names = "default"; + + status = "ok"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + vin1ep0: endpoint { + remote-endpoint = <&adv7180>; + bus-width = <8>; + }; + }; +}; + +&rcar_sound { + pinctrl-0 = <&sound_pins &sound_clk_pins>; + pinctrl-names = "default"; + + #sound-dai-cells = <0>; + + status = "okay"; + + rcar_sound,dai { + dai0 { + playback = <&ssi0 &src2 &dvc0>; + capture = <&ssi1 &src3 &dvc1>; + }; + }; +}; + +&ssi1 { + shared-pin; +}; diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index d9ddecbb859c..af7e255f629e 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -33,6 +33,10 @@ spi2 = &msiof1; spi3 = &msiof2; spi4 = &msiof3; + vin0 = &vin0; + vin1 = &vin1; + vin2 = &vin2; + vin3 = &vin3; }; cpus { @@ -206,6 +210,38 @@ <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; + cmt0: timer@ffca0000 { + compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2"; + reg = <0 0xffca0000 0 0x1004>; + interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>, + <0 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7790_CLK_CMT0>; + clock-names = "fck"; + + renesas,channels-mask = <0x60>; + + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>, + <0 121 IRQ_TYPE_LEVEL_HIGH>, + <0 122 IRQ_TYPE_LEVEL_HIGH>, + <0 123 IRQ_TYPE_LEVEL_HIGH>, + <0 124 IRQ_TYPE_LEVEL_HIGH>, + <0 125 IRQ_TYPE_LEVEL_HIGH>, + <0 126 IRQ_TYPE_LEVEL_HIGH>, + <0 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_CMT1>; + clock-names = "fck"; + + renesas,channels-mask = <0xff>; + + status = "disabled"; + }; + irqc0: interrupt-controller@e61c0000 { compatible = "renesas,irqc-r8a7790", "renesas,irqc"; #interrupt-cells = <2>; @@ -217,6 +253,129 @@ <0 3 IRQ_TYPE_LEVEL_HIGH>; }; + dmac0: dma-controller@e6700000 { + compatible = "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH + 0 200 IRQ_TYPE_LEVEL_HIGH + 0 201 IRQ_TYPE_LEVEL_HIGH + 0 202 IRQ_TYPE_LEVEL_HIGH + 0 203 IRQ_TYPE_LEVEL_HIGH + 0 204 IRQ_TYPE_LEVEL_HIGH + 0 205 IRQ_TYPE_LEVEL_HIGH + 0 206 IRQ_TYPE_LEVEL_HIGH + 0 207 IRQ_TYPE_LEVEL_HIGH + 0 208 IRQ_TYPE_LEVEL_HIGH + 0 209 IRQ_TYPE_LEVEL_HIGH + 0 210 IRQ_TYPE_LEVEL_HIGH + 0 211 IRQ_TYPE_LEVEL_HIGH + 0 212 IRQ_TYPE_LEVEL_HIGH + 0 213 IRQ_TYPE_LEVEL_HIGH + 0 214 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>; + clock-names = "fck"; + #dma-cells = <1>; + dma-channels = <15>; + }; + + dmac1: dma-controller@e6720000 { + compatible = "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH + 0 216 IRQ_TYPE_LEVEL_HIGH + 0 217 IRQ_TYPE_LEVEL_HIGH + 0 218 IRQ_TYPE_LEVEL_HIGH + 0 219 IRQ_TYPE_LEVEL_HIGH + 0 308 IRQ_TYPE_LEVEL_HIGH + 0 309 IRQ_TYPE_LEVEL_HIGH + 0 310 IRQ_TYPE_LEVEL_HIGH + 0 311 IRQ_TYPE_LEVEL_HIGH + 0 312 IRQ_TYPE_LEVEL_HIGH + 0 313 IRQ_TYPE_LEVEL_HIGH + 0 314 IRQ_TYPE_LEVEL_HIGH + 0 315 IRQ_TYPE_LEVEL_HIGH + 0 316 IRQ_TYPE_LEVEL_HIGH + 0 317 IRQ_TYPE_LEVEL_HIGH + 0 318 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>; + clock-names = "fck"; + #dma-cells = <1>; + dma-channels = <15>; + }; + + audma0: dma-controller@ec700000 { + compatible = "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = <0 346 IRQ_TYPE_LEVEL_HIGH + 0 320 IRQ_TYPE_LEVEL_HIGH + 0 321 IRQ_TYPE_LEVEL_HIGH + 0 322 IRQ_TYPE_LEVEL_HIGH + 0 323 IRQ_TYPE_LEVEL_HIGH + 0 324 IRQ_TYPE_LEVEL_HIGH + 0 325 IRQ_TYPE_LEVEL_HIGH + 0 326 IRQ_TYPE_LEVEL_HIGH + 0 327 IRQ_TYPE_LEVEL_HIGH + 0 328 IRQ_TYPE_LEVEL_HIGH + 0 329 IRQ_TYPE_LEVEL_HIGH + 0 330 IRQ_TYPE_LEVEL_HIGH + 0 331 IRQ_TYPE_LEVEL_HIGH + 0 332 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>; + clock-names = "fck"; + #dma-cells = <1>; + dma-channels = <13>; + }; + + audma1: dma-controller@ec720000 { + compatible = "renesas,rcar-dmac"; + reg = <0 0xec720000 0 0x10000>; + interrupts = <0 347 IRQ_TYPE_LEVEL_HIGH + 0 333 IRQ_TYPE_LEVEL_HIGH + 0 334 IRQ_TYPE_LEVEL_HIGH + 0 335 IRQ_TYPE_LEVEL_HIGH + 0 336 IRQ_TYPE_LEVEL_HIGH + 0 337 IRQ_TYPE_LEVEL_HIGH + 0 338 IRQ_TYPE_LEVEL_HIGH + 0 339 IRQ_TYPE_LEVEL_HIGH + 0 340 IRQ_TYPE_LEVEL_HIGH + 0 341 IRQ_TYPE_LEVEL_HIGH + 0 342 IRQ_TYPE_LEVEL_HIGH + 0 343 IRQ_TYPE_LEVEL_HIGH + 0 344 IRQ_TYPE_LEVEL_HIGH + 0 345 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>; + clock-names = "fck"; + #dma-cells = <1>; + dma-channels = <13>; + }; + + audmapp: dma-controller@ec740000 { + compatible = "renesas,rcar-audmapp"; + #dma-cells = <1>; + + reg = <0 0xec740000 0 0x200>; + }; + i2c0: i2c@e6508000 { #address-cells = <1>; #size-cells = <0>; @@ -264,6 +423,8 @@ reg = <0 0xe6500000 0 0x425>; interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_IIC0>; + dmas = <&dmac0 0x61>, <&dmac0 0x62>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -274,6 +435,8 @@ reg = <0 0xe6510000 0 0x425>; interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_IIC1>; + dmas = <&dmac0 0x65>, <&dmac0 0x66>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -284,6 +447,8 @@ reg = <0 0xe6520000 0 0x425>; interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_IIC2>; + dmas = <&dmac0 0x69>, <&dmac0 0x6a>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -294,14 +459,18 @@ reg = <0 0xe60b0000 0 0x425>; interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>; + dmas = <&dmac0 0x77>, <&dmac0 0x78>; + dma-names = "tx", "rx"; status = "disabled"; }; - mmcif0: mmcif@ee200000 { + mmcif0: mmc@ee200000 { compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; reg = <0 0xee200000 0 0x80>; interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; + dma-names = "tx", "rx"; reg-io-width = <4>; status = "disabled"; }; @@ -311,6 +480,8 @@ reg = <0 0xee220000 0 0x80>; interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>; + dmas = <&dmac0 0xe1>, <&dmac0 0xe2>; + dma-names = "tx", "rx"; reg-io-width = <4>; status = "disabled"; }; @@ -325,7 +496,6 @@ reg = <0 0xee100000 0 0x200>; interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_SDHI0>; - cap-sd-highspeed; status = "disabled"; }; @@ -334,7 +504,6 @@ reg = <0 0xee120000 0 0x200>; interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_SDHI1>; - cap-sd-highspeed; status = "disabled"; }; @@ -343,7 +512,6 @@ reg = <0 0xee140000 0 0x100>; interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_SDHI2>; - cap-sd-highspeed; status = "disabled"; }; @@ -352,7 +520,6 @@ reg = <0 0xee160000 0 0x100>; interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7790_CLK_SDHI3>; - cap-sd-highspeed; status = "disabled"; }; @@ -473,6 +640,158 @@ status = "disabled"; }; + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7790"; + reg = <0 0xe6590000 0 0x100>; + interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7790_CLK_HSUSB>; + renesas,buswait = <4>; + phys = <&usb0 1>; + phy-names = "usb"; + status = "disabled"; + }; + + usbphy: usb-phy@e6590100 { + compatible = "renesas,usb-phy-r8a7790"; + reg = <0 0xe6590100 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mstp7_clks R8A7790_CLK_HSUSB>; + clock-names = "usbhs"; + status = "disabled"; + + usb0: usb-channel@0 { + reg = <0>; + #phy-cells = <1>; + }; + usb2: usb-channel@2 { + reg = <2>; + #phy-cells = <1>; + }; + }; + + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7790"; + clocks = <&mstp8_clks R8A7790_CLK_VIN0>; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7790"; + clocks = <&mstp8_clks R8A7790_CLK_VIN1>; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a7790"; + clocks = <&mstp8_clks R8A7790_CLK_VIN2>; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + vin3: video@e6ef3000 { + compatible = "renesas,vin-r8a7790"; + clocks = <&mstp8_clks R8A7790_CLK_VIN3>; + reg = <0 0xe6ef3000 0 0x1000>; + interrupts = <0 191 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + vsp1@fe920000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe920000 0 0x8000>; + interrupts = <0 266 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>; + + renesas,has-sru; + renesas,#rpf = <5>; + renesas,#uds = <1>; + renesas,#wpf = <4>; + }; + + vsp1@fe928000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe928000 0 0x8000>; + interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>; + + renesas,has-lut; + renesas,has-sru; + renesas,#rpf = <5>; + renesas,#uds = <3>; + renesas,#wpf = <4>; + }; + + vsp1@fe930000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe930000 0 0x8000>; + interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>; + + renesas,has-lif; + renesas,has-lut; + renesas,#rpf = <4>; + renesas,#uds = <1>; + renesas,#wpf = <4>; + }; + + vsp1@fe938000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe938000 0 0x8000>; + interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>; + + renesas,has-lif; + renesas,has-lut; + renesas,#rpf = <4>; + renesas,#uds = <1>; + renesas,#wpf = <4>; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a7790"; + reg = <0 0xfeb00000 0 0x70000>, + <0 0xfeb90000 0 0x1c>, + <0 0xfeb94000 0 0x1c>; + reg-names = "du", "lvds.0", "lvds.1"; + interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>, + <0 268 IRQ_TYPE_LEVEL_HIGH>, + <0 269 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7790_CLK_DU0>, + <&mstp7_clks R8A7790_CLK_DU1>, + <&mstp7_clks R8A7790_CLK_DU2>, + <&mstp7_clks R8A7790_CLK_LVDS0>, + <&mstp7_clks R8A7790_CLK_LVDS1>; + clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_lvds0: endpoint { + }; + }; + port@2 { + reg = <2>; + du_out_lvds1: endpoint { + }; + }; + }; + }; + clocks { #address-cells = <2>; #size-cells = <2>; @@ -539,9 +858,9 @@ #clock-cells = <0>; clock-output-names = "sd2"; }; - sd3_clk: sd3_clk@e615007c { + sd3_clk: sd3_clk@e615026c { compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615007c 0 4>; + reg = <0 0xe615026c 0 4>; clocks = <&pll1_div2_clk>; #clock-cells = <0>; clock-output-names = "sd3"; @@ -741,58 +1060,72 @@ mstp1_clks: mstp1_clks@e6150134 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; - clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, - <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, - <&zs_clk>; + clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>, + <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>, + <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, + <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; #clock-cells = <1>; renesas,clock-indices = < - R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 - R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 - R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S + R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1 + R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1 + R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC + R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0 + R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0 + R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0 + R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S >; clock-output-names = - "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", - "vsp1-du0", "vsp1-rt", "vsp1-sy"; + "vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1", + "tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1", + "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0", + "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy"; }; mstp2_clks: mstp2_clks@e6150138 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, - <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>; + <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>, + <&zs_clk>; #clock-cells = <1>; renesas,clock-indices = < R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2 + R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0 >; clock-output-names = "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", - "scifb1", "msiof1", "msiof3", "scifb2"; + "scifb1", "msiof1", "msiof3", "scifb2", + "sys-dmac1", "sys-dmac0"; }; mstp3_clks: mstp3_clks@e615013c { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>, - <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>; + <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>, + <&hp_clk>, <&hp_clk>; #clock-cells = <1>; renesas,clock-indices = < R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1 + R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1 >; clock-output-names = "iic2", "tpu0", "mmcif1", "sdhi3", "sdhi2", "sdhi1", "sdhi0", "mmcif0", - "iic0", "pciec", "iic1", "ssusb", "cmt1"; + "iic0", "pciec", "iic1", "ssusb", "cmt1", + "usbdmac0", "usbdmac1"; }; mstp5_clks: mstp5_clks@e6150144 { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; - clocks = <&extal_clk>, <&p_clk>; + clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>; #clock-cells = <1>; - renesas,clock-indices = <R8A7790_CLK_THERMAL R8A7790_CLK_PWM>; - clock-output-names = "thermal", "pwm"; + renesas,clock-indices = <R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1 + R8A7790_CLK_THERMAL R8A7790_CLK_PWM>; + clock-output-names = "audmac0", "audmac1", "thermal", "pwm"; }; mstp7_clks: mstp7_clks@e615014c { compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; @@ -884,6 +1217,8 @@ reg = <0 0xe6b10000 0 0x2c>; interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>; + dma-names = "tx", "rx"; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -892,9 +1227,11 @@ msiof0: spi@e6e20000 { compatible = "renesas,msiof-r8a7790"; - reg = <0 0xe6e20000 0 0x0064>; + reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>; interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>; + dmas = <&dmac0 0x51>, <&dmac0 0x52>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -902,9 +1239,11 @@ msiof1: spi@e6e10000 { compatible = "renesas,msiof-r8a7790"; - reg = <0 0xe6e10000 0 0x0064>; + reg = <0 0xe6e10000 0 0x0064>, <0 0xe7e10000 0 0x0064>; interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>; + dmas = <&dmac0 0x55>, <&dmac0 0x56>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -912,9 +1251,11 @@ msiof2: spi@e6e00000 { compatible = "renesas,msiof-r8a7790"; - reg = <0 0xe6e00000 0 0x0064>; + reg = <0 0xe6e00000 0 0x0064>, <0 0xe7e00000 0 0x0064>; interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>; + dmas = <&dmac0 0x41>, <&dmac0 0x42>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -922,14 +1263,26 @@ msiof3: spi@e6c90000 { compatible = "renesas,msiof-r8a7790"; - reg = <0 0xe6c90000 0 0x0064>; + reg = <0 0xe6c90000 0 0x0064>, <0 0xe7c90000 0 0x0064>; interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>; + dmas = <&dmac0 0x45>, <&dmac0 0x46>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; + xhci: usb@ee000000 { + compatible = "renesas,xhci-r8a7790"; + reg = <0 0xee000000 0 0xc00>; + interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7790_CLK_SSUSB>; + phys = <&usb2 1>; + phy-names = "usb"; + status = "disabled"; + }; + pci0: pci@ee090000 { compatible = "renesas,pci-r8a7790"; device_type = "pci"; @@ -948,6 +1301,20 @@ interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>; + + usb@0,1 { + reg = <0x800 0 0 0 0>; + device_type = "pci"; + phys = <&usb0 0>; + phy-names = "usb"; + }; + + usb@0,2 { + reg = <0x1000 0 0 0 0>; + device_type = "pci"; + phys = <&usb0 0>; + phy-names = "usb"; + }; }; pci1: pci@ee0b0000 { @@ -988,6 +1355,20 @@ interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; + + usb@0,1 { + reg = <0x800 0 0 0 0>; + device_type = "pci"; + phys = <&usb2 0>; + phy-names = "usb"; + }; + + usb@0,2 { + reg = <0x1000 0 0 0 0>; + device_type = "pci"; + phys = <&usb2 0>; + phy-names = "usb"; + }; }; pciec: pcie@fe000000 { @@ -1015,10 +1396,9 @@ status = "disabled"; }; - rcar_sound: rcar_sound@0xec500000 { + rcar_sound: rcar_sound@ec500000 { #sound-dai-cells = <1>; compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2", "renesas,rcar_sound"; - interrupt-parent = <&gic>; reg = <0 0xec500000 0 0x1000>, /* SCU */ <0 0xec5a0000 0 0x100>, /* ADG */ <0 0xec540000 0 0x1000>, /* SSIU */ diff --git a/arch/arm/boot/dts/r8a7791-henninger.dts b/arch/arm/boot/dts/r8a7791-henninger.dts index 3a2ef0a2a137..740e38678032 100644 --- a/arch/arm/boot/dts/r8a7791-henninger.dts +++ b/arch/arm/boot/dts/r8a7791-henninger.dts @@ -23,6 +23,7 @@ chosen { bootargs = "console=ttySC0,38400 ignore_loglevel rw root=/dev/nfs ip=dhcp"; + stdout-path = &scif0; }; memory@40000000 { @@ -135,6 +136,11 @@ renesas,groups = "usb1"; renesas,function = "usb1"; }; + + vin0_pins: vin0 { + renesas,groups = "vin0_data8", "vin0_clk"; + renesas,function = "vin0"; + }; }; &scif0 { @@ -191,6 +197,19 @@ status = "okay"; clock-frequency = <400000>; + + composite-in@20 { + compatible = "adi,adv7180"; + reg = <0x20>; + remote = <&vin0>; + + port { + adv7180: endpoint { + bus-width = <8>; + remote-endpoint = <&vin0ep>; + }; + }; + }; }; &qspi { @@ -253,6 +272,17 @@ pinctrl-names = "default"; }; +&hsusb { + status = "okay"; + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + renesas,enable-gpio = <&gpio5 31 GPIO_ACTIVE_HIGH>; +}; + +&usbphy { + status = "okay"; +}; + &pcie_bus_clk { status = "okay"; }; @@ -260,3 +290,20 @@ &pciec { status = "okay"; }; + +/* composite video input */ +&vin0 { + status = "ok"; + pinctrl-0 = <&vin0_pins>; + pinctrl-names = "default"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + vin0ep: endpoint { + remote-endpoint = <&adv7180>; + bus-width = <8>; + }; + }; +}; diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index be59014474b2..990af167c551 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -10,6 +10,34 @@ * kind, whether express or implied. */ +/* + * SSI-AK4643 + * + * SW1: 1: AK4643 + * 2: CN22 + * 3: ADV7511 + * + * This command is required when Playback/Capture + * + * amixer set "LINEOUT Mixer DACL" on + * amixer set "DVC Out" 100% + * amixer set "DVC In" 100% + * + * You can use Mute + * + * amixer set "DVC Out Mute" on + * amixer set "DVC In Mute" on + * + * You can use Volume Ramp + * + * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" + * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" + * amixer set "DVC Out Ramp" on + * aplay xxx.wav & + * amixer set "DVC Out" 80% // Volume Down + * amixer set "DVC Out" 100% // Volume Up + */ + /dts-v1/; #include "r8a7791.dtsi" #include <dt-bindings/gpio/gpio.h> @@ -25,7 +53,8 @@ }; chosen { - bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp"; + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + stdout-path = &scif0; }; memory@40000000 { @@ -43,7 +72,7 @@ #size-cells = <1>; }; - gpio-keys { + keyboard { compatible = "gpio-keys"; key-1 { @@ -129,12 +158,15 @@ compatible = "gpio-leds"; led6 { gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; + label = "LED6"; }; led7 { gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + label = "LED7"; }; led8 { gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; + label = "LED8"; }; }; @@ -209,6 +241,36 @@ states = <3300000 1 1800000 0>; }; + + sound { + compatible = "simple-audio-card"; + + simple-audio-card,format = "left_j"; + simple-audio-card,bitclock-master = <&sndcodec>; + simple-audio-card,frame-master = <&sndcodec>; + + sndcpu: simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + }; + + sndcodec: simple-audio-card,codec { + sound-dai = <&ak4643>; + system-clock-frequency = <11289600>; + }; + }; +}; + +&du { + pinctrl-0 = <&du_pins>; + pinctrl-names = "default"; + status = "okay"; + + ports { + port@1 { + lvds_connector: endpoint { + }; + }; + }; }; &extal_clk { @@ -216,9 +278,6 @@ }; &pfc { - pinctrl-0 = <&du_pins>; - pinctrl-names = "default"; - i2c2_pins: i2c2 { renesas,groups = "i2c2"; renesas,function = "i2c2"; @@ -284,6 +343,21 @@ renesas,groups = "usb1"; renesas,function = "usb1"; }; + + vin1_pins: vin1 { + renesas,groups = "vin1_data8", "vin1_clk"; + renesas,function = "vin1"; + }; + + sound_pins: sound { + renesas,groups = "ssi0129_ctrl", "ssi0_data", "ssi1_data"; + renesas,function = "ssi"; + }; + + sound_clk_pins: sound_clk { + renesas,groups = "audio_clk_a"; + renesas,function = "audio_clk"; + }; }; ðer { @@ -302,6 +376,10 @@ }; }; +&cmt0 { + status = "ok"; +}; + &sata0 { status = "okay"; }; @@ -405,7 +483,26 @@ pinctrl-names = "default"; status = "okay"; - clock-frequency = <400000>; + clock-frequency = <100000>; + + ak4643: sound-codec@12 { + compatible = "asahi-kasei,ak4643"; + #sound-dai-cells = <0>; + reg = <0x12>; + }; + + composite-in@20 { + compatible = "adi,adv7180"; + reg = <0x20>; + remote = <&vin1>; + + port { + adv7180: endpoint { + bus-width = <8>; + remote-endpoint = <&vin1ep>; + }; + }; + }; eeprom@50 { compatible = "renesas,24c02"; @@ -419,7 +516,7 @@ clock-frequency = <100000>; vdd_dvfs: regulator@68 { - compatible = "diasemi,da9210"; + compatible = "dlg,da9210"; reg = <0x68>; regulator-min-microvolt = <1000000>; @@ -441,6 +538,17 @@ pinctrl-names = "default"; }; +&hsusb { + status = "okay"; + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + renesas,enable-gpio = <&gpio5 31 GPIO_ACTIVE_HIGH>; +}; + +&usbphy { + status = "okay"; +}; + &pcie_bus_clk { status = "okay"; }; @@ -452,3 +560,40 @@ &cpu0 { cpu0-supply = <&vdd_dvfs>; }; + +/* composite video input */ +&vin1 { + status = "ok"; + pinctrl-0 = <&vin1_pins>; + pinctrl-names = "default"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + vin1ep: endpoint { + remote-endpoint = <&adv7180>; + bus-width = <8>; + }; + }; +}; + +&rcar_sound { + pinctrl-0 = <&sound_pins &sound_clk_pins>; + pinctrl-names = "default"; + + #sound-dai-cells = <0>; + + status = "okay"; + + rcar_sound,dai { + dai0 { + playback = <&ssi0 &src2 &dvc0>; + capture = <&ssi1 &src3 &dvc1>; + }; + }; +}; + +&ssi1 { + shared-pin; +}; diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 0d82a4b3c650..77c0beeb8d7c 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -1,7 +1,7 @@ /* * Device Tree Source for the r8a7791 SoC * - * Copyright (C) 2013 Renesas Electronics Corporation + * Copyright (C) 2013-2014 Renesas Electronics Corporation * Copyright (C) 2013-2014 Renesas Solutions Corp. * Copyright (C) 2014 Cogent Embedded Inc. * @@ -34,6 +34,9 @@ spi1 = &msiof0; spi2 = &msiof1; spi3 = &msiof2; + vin0 = &vin0; + vin1 = &vin1; + vin2 = &vin2; }; cpus { @@ -189,6 +192,38 @@ <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; }; + cmt0: timer@ffca0000 { + compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2"; + reg = <0 0xffca0000 0 0x1004>; + interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>, + <0 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7791_CLK_CMT0>; + clock-names = "fck"; + + renesas,channels-mask = <0x60>; + + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>, + <0 121 IRQ_TYPE_LEVEL_HIGH>, + <0 122 IRQ_TYPE_LEVEL_HIGH>, + <0 123 IRQ_TYPE_LEVEL_HIGH>, + <0 124 IRQ_TYPE_LEVEL_HIGH>, + <0 125 IRQ_TYPE_LEVEL_HIGH>, + <0 126 IRQ_TYPE_LEVEL_HIGH>, + <0 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7791_CLK_CMT1>; + clock-names = "fck"; + + renesas,channels-mask = <0xff>; + + status = "disabled"; + }; + irqc0: interrupt-controller@e61c0000 { compatible = "renesas,irqc-r8a7791", "renesas,irqc"; #interrupt-cells = <2>; @@ -206,6 +241,129 @@ <0 17 IRQ_TYPE_LEVEL_HIGH>; }; + dmac0: dma-controller@e6700000 { + compatible = "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x20000>; + interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH + 0 200 IRQ_TYPE_LEVEL_HIGH + 0 201 IRQ_TYPE_LEVEL_HIGH + 0 202 IRQ_TYPE_LEVEL_HIGH + 0 203 IRQ_TYPE_LEVEL_HIGH + 0 204 IRQ_TYPE_LEVEL_HIGH + 0 205 IRQ_TYPE_LEVEL_HIGH + 0 206 IRQ_TYPE_LEVEL_HIGH + 0 207 IRQ_TYPE_LEVEL_HIGH + 0 208 IRQ_TYPE_LEVEL_HIGH + 0 209 IRQ_TYPE_LEVEL_HIGH + 0 210 IRQ_TYPE_LEVEL_HIGH + 0 211 IRQ_TYPE_LEVEL_HIGH + 0 212 IRQ_TYPE_LEVEL_HIGH + 0 213 IRQ_TYPE_LEVEL_HIGH + 0 214 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>; + clock-names = "fck"; + #dma-cells = <1>; + dma-channels = <15>; + }; + + dmac1: dma-controller@e6720000 { + compatible = "renesas,rcar-dmac"; + reg = <0 0xe6720000 0 0x20000>; + interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH + 0 216 IRQ_TYPE_LEVEL_HIGH + 0 217 IRQ_TYPE_LEVEL_HIGH + 0 218 IRQ_TYPE_LEVEL_HIGH + 0 219 IRQ_TYPE_LEVEL_HIGH + 0 308 IRQ_TYPE_LEVEL_HIGH + 0 309 IRQ_TYPE_LEVEL_HIGH + 0 310 IRQ_TYPE_LEVEL_HIGH + 0 311 IRQ_TYPE_LEVEL_HIGH + 0 312 IRQ_TYPE_LEVEL_HIGH + 0 313 IRQ_TYPE_LEVEL_HIGH + 0 314 IRQ_TYPE_LEVEL_HIGH + 0 315 IRQ_TYPE_LEVEL_HIGH + 0 316 IRQ_TYPE_LEVEL_HIGH + 0 317 IRQ_TYPE_LEVEL_HIGH + 0 318 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14"; + clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>; + clock-names = "fck"; + #dma-cells = <1>; + dma-channels = <15>; + }; + + audma0: dma-controller@ec700000 { + compatible = "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = <0 346 IRQ_TYPE_LEVEL_HIGH + 0 320 IRQ_TYPE_LEVEL_HIGH + 0 321 IRQ_TYPE_LEVEL_HIGH + 0 322 IRQ_TYPE_LEVEL_HIGH + 0 323 IRQ_TYPE_LEVEL_HIGH + 0 324 IRQ_TYPE_LEVEL_HIGH + 0 325 IRQ_TYPE_LEVEL_HIGH + 0 326 IRQ_TYPE_LEVEL_HIGH + 0 327 IRQ_TYPE_LEVEL_HIGH + 0 328 IRQ_TYPE_LEVEL_HIGH + 0 329 IRQ_TYPE_LEVEL_HIGH + 0 330 IRQ_TYPE_LEVEL_HIGH + 0 331 IRQ_TYPE_LEVEL_HIGH + 0 332 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>; + clock-names = "fck"; + #dma-cells = <1>; + dma-channels = <13>; + }; + + audma1: dma-controller@ec720000 { + compatible = "renesas,rcar-dmac"; + reg = <0 0xec720000 0 0x10000>; + interrupts = <0 347 IRQ_TYPE_LEVEL_HIGH + 0 333 IRQ_TYPE_LEVEL_HIGH + 0 334 IRQ_TYPE_LEVEL_HIGH + 0 335 IRQ_TYPE_LEVEL_HIGH + 0 336 IRQ_TYPE_LEVEL_HIGH + 0 337 IRQ_TYPE_LEVEL_HIGH + 0 338 IRQ_TYPE_LEVEL_HIGH + 0 339 IRQ_TYPE_LEVEL_HIGH + 0 340 IRQ_TYPE_LEVEL_HIGH + 0 341 IRQ_TYPE_LEVEL_HIGH + 0 342 IRQ_TYPE_LEVEL_HIGH + 0 343 IRQ_TYPE_LEVEL_HIGH + 0 344 IRQ_TYPE_LEVEL_HIGH + 0 345 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12"; + clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>; + clock-names = "fck"; + #dma-cells = <1>; + dma-channels = <13>; + }; + + audmapp: dma-controller@ec740000 { + compatible = "renesas,rcar-audmapp"; + #dma-cells = <1>; + + reg = <0 0xec740000 0 0x200>; + }; + /* The memory map in the User's Manual maps the cores to bus numbers */ i2c0: i2c@e6508000 { #address-cells = <1>; @@ -276,6 +434,8 @@ reg = <0 0xe60b0000 0 0x425>; interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>; + dmas = <&dmac0 0x77>, <&dmac0 0x78>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -286,6 +446,8 @@ reg = <0 0xe6500000 0 0x425>; interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7791_CLK_IIC0>; + dmas = <&dmac0 0x61>, <&dmac0 0x62>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -296,6 +458,8 @@ reg = <0 0xe6510000 0 0x425>; interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp3_clks R8A7791_CLK_IIC1>; + dmas = <&dmac0 0x65>, <&dmac0 0x66>; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -305,6 +469,17 @@ #gpio-range-cells = <3>; }; + mmcif0: mmc@ee200000 { + compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif"; + reg = <0 0xee200000 0 0x80>; + interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; + dma-names = "tx", "rx"; + reg-io-width = <4>; + status = "disabled"; + }; + sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a7791"; reg = <0 0xee100000 0 0x200>; @@ -518,6 +693,129 @@ status = "disabled"; }; + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7791"; + reg = <0 0xe6590000 0 0x100>; + interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7791_CLK_HSUSB>; + renesas,buswait = <4>; + phys = <&usb0 1>; + phy-names = "usb"; + status = "disabled"; + }; + + usbphy: usb-phy@e6590100 { + compatible = "renesas,usb-phy-r8a7791"; + reg = <0 0xe6590100 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mstp7_clks R8A7791_CLK_HSUSB>; + clock-names = "usbhs"; + status = "disabled"; + + usb0: usb-channel@0 { + reg = <0>; + #phy-cells = <1>; + }; + usb2: usb-channel@2 { + reg = <2>; + #phy-cells = <1>; + }; + }; + + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a7791"; + clocks = <&mstp8_clks R8A7791_CLK_VIN0>; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a7791"; + clocks = <&mstp8_clks R8A7791_CLK_VIN1>; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a7791"; + clocks = <&mstp8_clks R8A7791_CLK_VIN2>; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + vsp1@fe928000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe928000 0 0x8000>; + interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>; + + renesas,has-lut; + renesas,has-sru; + renesas,#rpf = <5>; + renesas,#uds = <3>; + renesas,#wpf = <4>; + }; + + vsp1@fe930000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe930000 0 0x8000>; + interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>; + + renesas,has-lif; + renesas,has-lut; + renesas,#rpf = <4>; + renesas,#uds = <1>; + renesas,#wpf = <4>; + }; + + vsp1@fe938000 { + compatible = "renesas,vsp1"; + reg = <0 0xfe938000 0 0x8000>; + interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>; + + renesas,has-lif; + renesas,has-lut; + renesas,#rpf = <4>; + renesas,#uds = <1>; + renesas,#wpf = <4>; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a7791"; + reg = <0 0xfeb00000 0 0x40000>, + <0 0xfeb90000 0 0x1c>; + reg-names = "du", "lvds.0"; + interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>, + <0 268 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7791_CLK_DU0>, + <&mstp7_clks R8A7791_CLK_DU1>, + <&mstp7_clks R8A7791_CLK_LVDS0>; + clock-names = "du.0", "du.1", "lvds.0"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_lvds0: endpoint { + }; + }; + }; + }; + clocks { #address-cells = <2>; #size-cells = <2>; @@ -770,17 +1068,23 @@ mstp1_clks: mstp1_clks@e6150134 { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; - clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, - <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; + clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>, + <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, + <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>, + <&zs_clk>; #clock-cells = <1>; renesas,clock-indices = < - R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 - R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 - R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S + R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU + R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG + R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0 + R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0 + R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0 + R8A7791_CLK_VSP1_S >; clock-output-names = - "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", - "vsp1-du0", "vsp1-sy"; + "vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg", + "2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0", + "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy"; }; mstp2_clks: mstp2_clks@e6150138 { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; @@ -804,24 +1108,28 @@ compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>, - <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>; + <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>, + <&hp_clk>, <&hp_clk>; #clock-cells = <1>; renesas,clock-indices = < R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1 + R8A7791_CLK_USBDMAC0 R8A7791_CLK_USBDMAC1 >; clock-output-names = "tpu0", "sdhi2", "sdhi1", "sdhi0", - "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1"; + "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1", + "usbdmac0", "usbdmac1"; }; mstp5_clks: mstp5_clks@e6150144 { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; - clocks = <&extal_clk>, <&p_clk>; + clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>; #clock-cells = <1>; - renesas,clock-indices = <R8A7791_CLK_THERMAL R8A7791_CLK_PWM>; - clock-output-names = "thermal", "pwm"; + renesas,clock-indices = <R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1 + R8A7791_CLK_THERMAL R8A7791_CLK_PWM>; + clock-output-names = "audmac0", "audmac1", "thermal", "pwm"; }; mstp7_clks: mstp7_clks@e615014c { compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; @@ -925,6 +1233,8 @@ reg = <0 0xe6b10000 0 0x2c>; interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>; + dma-names = "tx", "rx"; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -933,9 +1243,11 @@ msiof0: spi@e6e20000 { compatible = "renesas,msiof-r8a7791"; - reg = <0 0xe6e20000 0 0x0064>; + reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>; interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; + dmas = <&dmac0 0x51>, <&dmac0 0x52>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -943,9 +1255,11 @@ msiof1: spi@e6e10000 { compatible = "renesas,msiof-r8a7791"; - reg = <0 0xe6e10000 0 0x0064>; + reg = <0 0xe6e10000 0 0x0064>, <0 0xe7e10000 0 0x0064>; interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>; + dmas = <&dmac0 0x55>, <&dmac0 0x56>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -953,14 +1267,26 @@ msiof2: spi@e6e00000 { compatible = "renesas,msiof-r8a7791"; - reg = <0 0xe6e00000 0 0x0064>; + reg = <0 0xe6e00000 0 0x0064>, <0 0xe7e00000 0 0x0064>; interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>; + dmas = <&dmac0 0x41>, <&dmac0 0x42>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; + xhci: usb@ee000000 { + compatible = "renesas,xhci-r8a7791"; + reg = <0 0xee000000 0 0xc00>; + interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7791_CLK_SSUSB>; + phys = <&usb2 1>; + phy-names = "usb"; + status = "disabled"; + }; + pci0: pci@ee090000 { compatible = "renesas,pci-r8a7791"; device_type = "pci"; @@ -979,6 +1305,20 @@ interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>; + + usb@0,1 { + reg = <0x800 0 0 0 0>; + device_type = "pci"; + phys = <&usb0 0>; + phy-names = "usb"; + }; + + usb@0,2 { + reg = <0x1000 0 0 0 0>; + device_type = "pci"; + phys = <&usb0 0>; + phy-names = "usb"; + }; }; pci1: pci@ee0d0000 { @@ -999,6 +1339,20 @@ interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; + + usb@0,1 { + reg = <0x800 0 0 0 0>; + device_type = "pci"; + phys = <&usb2 0>; + phy-names = "usb"; + }; + + usb@0,2 { + reg = <0x1000 0 0 0 0>; + device_type = "pci"; + phys = <&usb2 0>; + phy-names = "usb"; + }; }; pciec: pcie@fe000000 { @@ -1026,10 +1380,9 @@ status = "disabled"; }; - rcar_sound: rcar_sound@0xec500000 { + rcar_sound: rcar_sound@ec500000 { #sound-dai-cells = <1>; compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2", "renesas,rcar_sound"; - interrupt-parent = <&gic>; reg = <0 0xec500000 0 0x1000>, /* SCU */ <0 0xec5a0000 0 0x100>, /* ADG */ <0 0xec540000 0 0x1000>, /* SSIU */ diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts new file mode 100644 index 000000000000..f2cf7576bf3f --- /dev/null +++ b/arch/arm/boot/dts/r8a7794-alt.dts @@ -0,0 +1,48 @@ +/* + * Device Tree Source for the Alt board + * + * Copyright (C) 2014 Renesas Electronics Corporation + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7794.dtsi" + +/ { + model = "Alt"; + compatible = "renesas,alt", "renesas,r8a7794"; + + aliases { + serial0 = &scif2; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + stdout-path = &scif2; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; + + lbsc { + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; + +&cmt0 { + status = "ok"; +}; + +&scif2 { + status = "ok"; +}; diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi new file mode 100644 index 000000000000..19c9de3f2a5a --- /dev/null +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -0,0 +1,542 @@ +/* + * Device Tree Source for the r8a7794 SoC + * + * Copyright (C) 2014 Renesas Electronics Corporation + * Copyright (C) 2014 Ulrich Hecht + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include <dt-bindings/clock/r8a7794-clock.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "renesas,r8a7794"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0>; + clock-frequency = <1000000000>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <1>; + clock-frequency = <1000000000>; + }; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0xf1001000 0 0x1000>, + <0 0xf1002000 0 0x1000>, + <0 0xf1004000 0 0x2000>, + <0 0xf1006000 0 0x2000>; + interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + cmt0: timer@ffca0000 { + compatible = "renesas,cmt-48-gen2"; + reg = <0 0xffca0000 0 0x1004>; + interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>, + <0 143 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp1_clks R8A7794_CLK_CMT0>; + clock-names = "fck"; + + renesas,channels-mask = <0x60>; + + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,cmt-48-gen2"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>, + <0 121 IRQ_TYPE_LEVEL_HIGH>, + <0 122 IRQ_TYPE_LEVEL_HIGH>, + <0 123 IRQ_TYPE_LEVEL_HIGH>, + <0 124 IRQ_TYPE_LEVEL_HIGH>, + <0 125 IRQ_TYPE_LEVEL_HIGH>, + <0 126 IRQ_TYPE_LEVEL_HIGH>, + <0 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp3_clks R8A7794_CLK_CMT1>; + clock-names = "fck"; + + renesas,channels-mask = <0xff>; + + status = "disabled"; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + + irqc0: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a7794", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, + <0 1 IRQ_TYPE_LEVEL_HIGH>, + <0 2 IRQ_TYPE_LEVEL_HIGH>, + <0 3 IRQ_TYPE_LEVEL_HIGH>, + <0 12 IRQ_TYPE_LEVEL_HIGH>, + <0 13 IRQ_TYPE_LEVEL_HIGH>, + <0 14 IRQ_TYPE_LEVEL_HIGH>, + <0 15 IRQ_TYPE_LEVEL_HIGH>, + <0 16 IRQ_TYPE_LEVEL_HIGH>, + <0 17 IRQ_TYPE_LEVEL_HIGH>; + }; + + scifa0: serial@e6c40000 { + compatible = "renesas,scifa-r8a7794", "renesas,scifa"; + reg = <0 0xe6c40000 0 64>; + interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifa1: serial@e6c50000 { + compatible = "renesas,scifa-r8a7794", "renesas,scifa"; + reg = <0 0xe6c50000 0 64>; + interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifa2: serial@e6c60000 { + compatible = "renesas,scifa-r8a7794", "renesas,scifa"; + reg = <0 0xe6c60000 0 64>; + interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifa3: serial@e6c70000 { + compatible = "renesas,scifa-r8a7794", "renesas,scifa"; + reg = <0 0xe6c70000 0 64>; + interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifa4: serial@e6c78000 { + compatible = "renesas,scifa-r8a7794", "renesas,scifa"; + reg = <0 0xe6c78000 0 64>; + interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifa5: serial@e6c80000 { + compatible = "renesas,scifa-r8a7794", "renesas,scifa"; + reg = <0 0xe6c80000 0 64>; + interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifb0: serial@e6c20000 { + compatible = "renesas,scifb-r8a7794", "renesas,scifb"; + reg = <0 0xe6c20000 0 64>; + interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifb1: serial@e6c30000 { + compatible = "renesas,scifb-r8a7794", "renesas,scifb"; + reg = <0 0xe6c30000 0 64>; + interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scifb2: serial@e6ce0000 { + compatible = "renesas,scifb-r8a7794", "renesas,scifb"; + reg = <0 0xe6ce0000 0 64>; + interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7794", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7794_CLK_SCIF0>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7794", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7794_CLK_SCIF1>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif2: serial@e6e58000 { + compatible = "renesas,scif-r8a7794", "renesas,scif"; + reg = <0 0xe6e58000 0 64>; + interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7794_CLK_SCIF2>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif3: serial@e6ea8000 { + compatible = "renesas,scif-r8a7794", "renesas,scif"; + reg = <0 0xe6ea8000 0 64>; + interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7794_CLK_SCIF3>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif4: serial@e6ee0000 { + compatible = "renesas,scif-r8a7794", "renesas,scif"; + reg = <0 0xe6ee0000 0 64>; + interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7794_CLK_SCIF4>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + scif5: serial@e6ee8000 { + compatible = "renesas,scif-r8a7794", "renesas,scif"; + reg = <0 0xe6ee8000 0 64>; + interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7794_CLK_SCIF5>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + hscif0: serial@e62c0000 { + compatible = "renesas,hscif-r8a7794", "renesas,hscif"; + reg = <0 0xe62c0000 0 96>; + interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + hscif1: serial@e62c8000 { + compatible = "renesas,hscif-r8a7794", "renesas,hscif"; + reg = <0 0xe62c8000 0 96>; + interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + hscif2: serial@e62d0000 { + compatible = "renesas,hscif-r8a7794", "renesas,hscif"; + reg = <0 0xe62d0000 0 96>; + interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>; + clock-names = "sci_ick"; + status = "disabled"; + }; + + clocks { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* External root clock */ + extal_clk: extal_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overriden by the board. */ + clock-frequency = <0>; + clock-output-names = "extal"; + }; + + /* Special CPG clocks */ + cpg_clocks: cpg_clocks@e6150000 { + compatible = "renesas,r8a7794-cpg-clocks", + "renesas,rcar-gen2-cpg-clocks"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>; + #clock-cells = <1>; + clock-output-names = "main", "pll0", "pll1", "pll3", + "lb", "qspi", "sdh", "sd0", "z"; + }; + + /* Fixed factor clocks */ + pll1_div2_clk: pll1_div2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7794_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "pll1_div2"; + }; + zg_clk: zg_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7794_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <6>; + clock-mult = <1>; + clock-output-names = "zg"; + }; + zx_clk: zx_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7794_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <3>; + clock-mult = <1>; + clock-output-names = "zx"; + }; + zs_clk: zs_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7794_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <6>; + clock-mult = <1>; + clock-output-names = "zs"; + }; + hp_clk: hp_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7794_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <12>; + clock-mult = <1>; + clock-output-names = "hp"; + }; + i_clk: i_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7794_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "i"; + }; + b_clk: b_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7794_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <12>; + clock-mult = <1>; + clock-output-names = "b"; + }; + p_clk: p_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7794_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <24>; + clock-mult = <1>; + clock-output-names = "p"; + }; + cl_clk: cl_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7794_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <48>; + clock-mult = <1>; + clock-output-names = "cl"; + }; + m2_clk: m2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7794_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clock-output-names = "m2"; + }; + imp_clk: imp_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7794_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + clock-output-names = "imp"; + }; + rclk_clk: rclk_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7794_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <(48 * 1024)>; + clock-mult = <1>; + clock-output-names = "rclk"; + }; + oscclk_clk: oscclk_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7794_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <(12 * 1024)>; + clock-mult = <1>; + clock-output-names = "oscclk"; + }; + zb3_clk: zb3_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7794_CLK_PLL3>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + clock-output-names = "zb3"; + }; + zb3d2_clk: zb3d2_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7794_CLK_PLL3>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clock-output-names = "zb3d2"; + }; + ddr_clk: ddr_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7794_CLK_PLL3>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clock-output-names = "ddr"; + }; + mp_clk: mp_clk { + compatible = "fixed-factor-clock"; + clocks = <&pll1_div2_clk>; + #clock-cells = <0>; + clock-div = <15>; + clock-mult = <1>; + clock-output-names = "mp"; + }; + cp_clk: cp_clk { + compatible = "fixed-factor-clock"; + clocks = <&cpg_clocks R8A7794_CLK_PLL1>; + #clock-cells = <0>; + clock-div = <48>; + clock-mult = <1>; + clock-output-names = "cp"; + }; + + acp_clk: acp_clk { + compatible = "fixed-factor-clock"; + clocks = <&extal_clk>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "acp"; + }; + + /* Gate clocks */ + mstp0_clks: mstp0_clks@e6150130 { + compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; + clocks = <&mp_clk>; + #clock-cells = <1>; + renesas,clock-indices = <R8A7794_CLK_MSIOF0>; + clock-output-names = "msiof0"; + }; + mstp1_clks: mstp1_clks@e6150134 { + compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; + clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, + <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>, + <&zs_clk>, <&zs_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1 + R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0 + R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0 + R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S + >; + clock-output-names = + "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0", + "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps"; + }; + mstp2_clks: mstp2_clks@e6150138 { + compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; + clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, + <&mp_clk>, <&mp_clk>, <&mp_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0 + R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1 + R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2 + >; + clock-output-names = + "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", + "scifb1", "msiof1", "scifb2"; + }; + mstp3_clks: mstp3_clks@e615013c { + compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; + clocks = <&rclk_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7794_CLK_CMT1 + >; + clock-output-names = + "cmt1"; + }; + mstp7_clks: mstp7_clks@e615014c { + compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; + clocks = <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, + <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5 + R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0 + R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1 + R8A7794_CLK_SCIF0 + >; + clock-output-names = + "hscif2", "scif5", "scif4", "hscif1", "hscif0", + "scif3", "scif2", "scif1", "scif0"; + }; + mstp8_clks: mstp8_clks@e6150990 { + compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; + clocks = <&zg_clk>, <&zg_clk>, <&p_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 R8A7794_CLK_ETHER + >; + clock-output-names = + "vin1", "vin0", "ether"; + }; + mstp11_clks: mstp11_clks@e615099c { + compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; + reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; + clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; + #clock-cells = <1>; + renesas,clock-indices = < + R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5 + >; + clock-output-names = "scifa3", "scifa4", "scifa5"; + }; + }; +}; diff --git a/arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi b/arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi new file mode 100644 index 000000000000..65cb50f0c29f --- /dev/null +++ b/arch/arm/boot/dts/r8a77xx-aa104xd12-panel.dtsi @@ -0,0 +1,41 @@ +/* + * Common file for the AA104XD12 panel connected to Renesas R-Car boards + * + * Copyright (C) 2014 Renesas Electronics Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/ { + panel { + compatible = "mitsubishi,aa104xd12", "panel-dpi"; + + width-mm = <210>; + height-mm = <158>; + + panel-timing { + /* 1024x768 @65Hz */ + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hsync-len = <136>; + hfront-porch = <20>; + hback-porch = <160>; + vfront-porch = <3>; + vback-porch = <29>; + vsync-len = <6>; + }; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds_connector>; + }; + }; + }; +}; + +&lvds_connector { + remote-endpoint = <&panel_in>; +}; diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts index c9d912da6141..baf21ac6ce7f 100644 --- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts +++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts @@ -60,6 +60,10 @@ }; }; +&cpu0 { + cpu0-supply = <&vdd_arm>; +}; + &i2c1 { status = "okay"; clock-frequency = <400000>; @@ -152,12 +156,8 @@ pinctrl-names = "default"; pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; vmmc-supply = <&vcc_sd0>; - - slot@0 { - reg = <0>; - bus-width = <4>; - disable-wp; - }; + bus-width = <4>; + disable-wp; }; &mmc1 { /* wifi */ @@ -168,11 +168,8 @@ pinctrl-names = "default"; pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>; - slot@0 { - reg = <0>; - bus-width = <4>; - disable-wp; - }; + bus-width = <4>; + disable-wp; }; &uart0 { diff --git a/arch/arm/boot/dts/rk3066a-marsboard.dts b/arch/arm/boot/dts/rk3066a-marsboard.dts new file mode 100644 index 000000000000..0a7304beb417 --- /dev/null +++ b/arch/arm/boot/dts/rk3066a-marsboard.dts @@ -0,0 +1,206 @@ +/* + * Copyright (c) 2014 Romain Perier <romain.perier@gmail.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +#include "rk3066a.dtsi" + +/ { + model = "MarsBoard RK3066"; + compatible = "haoyu,marsboard-rk3066", "rockchip,rk3066a"; + + memory { + reg = <0x60000000 0x40000000>; + }; + + vcc_sd0: sdmmc-regulator { + compatible = "regulator-fixed"; + regulator-name = "sdmmc-supply"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + gpio = <&gpio3 7 GPIO_ACTIVE_LOW>; + startup-delay-us = <100000>; + vin-supply = <&vcc_io>; + }; + + vsys: vsys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vsys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + }; +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + + tps: tps@2d { + reg = <0x2d>; + + interrupt-parent = <&gpio6>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + + vcc1-supply = <&vsys>; + vcc2-supply = <&vsys>; + vcc3-supply = <&vsys>; + vcc4-supply = <&vsys>; + vcc5-supply = <&vcc_io>; + vcc6-supply = <&vcc_io>; + vcc7-supply = <&vsys>; + vccio-supply = <&vsys>; + + regulators { + vcc_rtc: regulator@0 { + regulator-name = "vcc_rtc"; + regulator-always-on; + }; + + vcc_io: regulator@1 { + regulator-name = "vcc_io"; + regulator-always-on; + }; + + vdd_arm: regulator@2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_ddr: regulator@3 { + regulator-name = "vcc_ddr"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1500000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc18_cif: regulator@5 { + regulator-name = "vcc18_cif"; + regulator-always-on; + }; + + vdd_11: regulator@6 { + regulator-name = "vdd_11"; + regulator-always-on; + }; + + vcc_25: regulator@7 { + regulator-name = "vcc_25"; + regulator-always-on; + }; + + vcc_18: regulator@8 { + regulator-name = "vcc_18"; + regulator-always-on; + }; + + vcc25_hdmi: regulator@9 { + regulator-name = "vcc25_hdmi"; + regulator-always-on; + }; + + vcca_33: regulator@10 { + regulator-name = "vcca_33"; + regulator-always-on; + }; + + vcc_rmii: regulator@11 { + regulator-name = "vcc_rmii"; + }; + + vcc28_cif: regulator@12 { + regulator-name = "vcc28_cif"; + regulator-always-on; + }; + }; + }; +}; + +/* must be included after &tps gets defined */ +#include "tps65910.dtsi" + +&emac { + status = "okay"; + + phy = <&phy0>; + phy-supply = <&vcc_rmii>; + + pinctrl-names = "default"; + pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>; + + phy0: ethernet-phy@0 { + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&pinctrl { + lan8720a { + phy_int: phy-int { + rockchip,pins = <RK_GPIO1 26 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&wdt { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi index 879a818fba51..41ffd4951ef3 100644 --- a/arch/arm/boot/dts/rk3066a.dtsi +++ b/arch/arm/boot/dts/rk3066a.dtsi @@ -26,11 +26,21 @@ #size-cells = <0>; enable-method = "rockchip,rk3066-smp"; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x0>; + operating-points = < + /* kHz uV */ + 1008000 1075000 + 816000 1025000 + 600000 1025000 + 504000 1000000 + 312000 975000 + >; + clock-latency = <40000>; + clocks = <&cru ARMCLK>; }; cpu@1 { device_type = "cpu"; @@ -53,6 +63,51 @@ }; }; + i2s0: i2s@10118000 { + compatible = "rockchip,rk3066-i2s"; + reg = <0x10118000 0x2000>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_bus>; + dmas = <&dmac1_s 4>, <&dmac1_s 5>; + dma-names = "tx", "rx"; + clock-names = "i2s_hclk", "i2s_clk"; + clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; + status = "disabled"; + }; + + i2s1: i2s@1011a000 { + compatible = "rockchip,rk3066-i2s"; + reg = <0x1011a000 0x2000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s1_bus>; + dmas = <&dmac1_s 6>, <&dmac1_s 7>; + dma-names = "tx", "rx"; + clock-names = "i2s_hclk", "i2s_clk"; + clocks = <&cru HCLK_I2S1>, <&cru SCLK_I2S1>; + status = "disabled"; + }; + + i2s2: i2s@1011c000 { + compatible = "rockchip,rk3066-i2s"; + reg = <0x1011c000 0x2000>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s2_bus>; + dmas = <&dmac1_s 9>, <&dmac1_s 10>; + dma-names = "tx", "rx"; + clock-names = "i2s_hclk", "i2s_clk"; + clocks = <&cru HCLK_I2S2>, <&cru SCLK_I2S2>; + status = "disabled"; + }; + cru: clock-controller@20000000 { compatible = "rockchip,rk3066a-cru"; reg = <0x20000000 0x1000>; @@ -179,6 +234,45 @@ bias-disable; }; + emac { + emac_xfer: emac-xfer { + rockchip,pins = <RK_GPIO1 16 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */ + <RK_GPIO1 17 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */ + <RK_GPIO1 18 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */ + <RK_GPIO1 19 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */ + <RK_GPIO1 20 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */ + <RK_GPIO1 21 RK_FUNC_2 &pcfg_pull_none>, /* crs_dvalid */ + <RK_GPIO1 22 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */ + <RK_GPIO1 23 RK_FUNC_2 &pcfg_pull_none>; /* rxd0 */ + }; + + emac_mdio: emac-mdio { + rockchip,pins = <RK_GPIO1 24 RK_FUNC_2 &pcfg_pull_none>, /* mac_md */ + <RK_GPIO1 25 RK_FUNC_2 &pcfg_pull_none>; /* mac_mdclk */ + }; + }; + + emmc { + emmc_clk: emmc-clk { + rockchip,pins = <RK_GPIO3 31 RK_FUNC_2 &pcfg_pull_default>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = <RK_GPIO4 9 RK_FUNC_2 &pcfg_pull_default>; + }; + + emmc_rst: emmc-rst { + rockchip,pins = <RK_GPIO4 10 RK_FUNC_2 &pcfg_pull_default>; + }; + + /* + * The data pins are shared between nandc and emmc and + * not accessible through pinctrl. Also they should've + * been already set correctly by firmware, as + * flash/emmc is the boot-device. + */ + }; + i2c0 { i2c0_xfer: i2c0-xfer { rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>, @@ -238,6 +332,42 @@ }; }; + spi0 { + spi0_clk: spi0-clk { + rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_default>; + }; + spi0_cs0: spi0-cs0 { + rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_default>; + }; + spi0_tx: spi0-tx { + rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_default>; + }; + spi0_rx: spi0-rx { + rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_default>; + }; + spi0_cs1: spi0-cs1 { + rockchip,pins = <RK_GPIO4 15 RK_FUNC_1 &pcfg_pull_default>; + }; + }; + + spi1 { + spi1_clk: spi1-clk { + rockchip,pins = <RK_GPIO2 19 RK_FUNC_2 &pcfg_pull_default>; + }; + spi1_cs0: spi1-cs0 { + rockchip,pins = <RK_GPIO2 20 RK_FUNC_2 &pcfg_pull_default>; + }; + spi1_rx: spi1-rx { + rockchip,pins = <RK_GPIO2 22 RK_FUNC_2 &pcfg_pull_default>; + }; + spi1_tx: spi1-tx { + rockchip,pins = <RK_GPIO2 21 RK_FUNC_2 &pcfg_pull_default>; + }; + spi1_cs1: spi1-cs1 { + rockchip,pins = <RK_GPIO2 23 RK_FUNC_2 &pcfg_pull_default>; + }; + }; + uart0 { uart0_xfer: uart0-xfer { rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>, @@ -348,6 +478,42 @@ <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>; }; }; + + i2s0 { + i2s0_bus: i2s0-bus { + rockchip,pins = <RK_GPIO0 7 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO0 8 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO0 9 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO0 10 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO0 11 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO0 12 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO0 13 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO0 14 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO0 15 RK_FUNC_1 &pcfg_pull_default>; + }; + }; + + i2s1 { + i2s1_bus: i2s1-bus { + rockchip,pins = <RK_GPIO0 16 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO0 17 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO0 18 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO0 19 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO0 20 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO0 21 RK_FUNC_1 &pcfg_pull_default>; + }; + }; + + i2s2 { + i2s2_bus: i2s2-bus { + rockchip,pins = <RK_GPIO0 24 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO0 25 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO0 26 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO0 27 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_default>, + <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_default>; + }; + }; }; }; @@ -406,6 +572,16 @@ pinctrl-0 = <&pwm3_out>; }; +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer>; @@ -429,3 +605,7 @@ &wdt { compatible = "rockchip,rk3066-wdt", "snps,dw-wdt"; }; + +&emac { + compatible = "rockchip,rk3066-emac"; +}; diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts index 5e4e3c238b2d..9a09579b8309 100644 --- a/arch/arm/boot/dts/rk3188-radxarock.dts +++ b/arch/arm/boot/dts/rk3188-radxarock.dts @@ -43,16 +43,19 @@ compatible = "gpio-leds"; green { + label = "rock:green:user1"; gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; default-state = "off"; }; - yellow { + blue { + label = "rock:blue:user2"; gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; default-state = "off"; }; sleep { + label = "rock:red:power"; gpios = <&gpio0 15 0>; default-state = "off"; }; @@ -65,6 +68,19 @@ pinctrl-0 = <&ir_recv_pin>; }; + vcc_otg: usb-otg-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-name = "otg-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + vcc_sd0: sdmmc-regulator { compatible = "regulator-fixed"; regulator-name = "sdmmc-supply"; @@ -74,12 +90,56 @@ startup-delay-us = <100000>; vin-supply = <&vcc_io>; }; + + vcc_host: usb-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "host-pwr"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&emac { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&emac_xfer>, <&emac_mdio>, <&phy_int>; + + phy = <&phy0>; + phy-supply = <&vcc_rmii>; + + phy0: ethernet-phy@0 { + reg = <0>; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&cpu0 { + cpu0-supply = <&vdd_arm>; }; &i2c1 { status = "okay"; clock-frequency = <400000>; + rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + interrupt-parent = <&gpio0>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&rtc_int>; + #clock-cells = <0>; + clock-output-names = "xin32k"; + }; + act8846: act8846@5a { compatible = "active-semi,act8846"; reg = <0x5a>; @@ -106,7 +166,7 @@ vdd_arm: REG3 { regulator-name = "VDD_ARM"; regulator-min-microvolt = <875000>; - regulator-max-microvolt = <1300000>; + regulator-max-microvolt = <1350000>; regulator-always-on; }; @@ -149,7 +209,6 @@ regulator-name = "VCC_RMII"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - regulator-always-on; }; vccio_wl: REG10 { @@ -183,11 +242,20 @@ pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, <&sd0_cd>, <&sd0_bus4>; vmmc-supply = <&vcc_sd0>; - slot@0 { - reg = <0>; - bus-width = <4>; - disable-wp; - }; + bus-width = <4>; + disable-wp; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; }; &pinctrl { @@ -201,11 +269,32 @@ }; }; + hym8563 { + rtc_int: rtc-int { + rockchip,pins = <RK_GPIO0 0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + lan8720a { + phy_int: phy-int { + rockchip,pins = <RK_GPIO3 26 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + ir-receiver { ir_recv_pin: ir-recv-pin { rockchip,pins = <RK_GPIO0 10 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + usb { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <2 31 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &uart0 { @@ -224,6 +313,14 @@ status = "okay"; }; +&usb_host { + status = "okay"; +}; + +&usb_otg { + status = "okay"; +}; + &wdt { status = "okay"; }; diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index ee801a9c6b74..1d4d79c6688d 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -26,11 +26,24 @@ #size-cells = <0>; enable-method = "rockchip,rk3066-smp"; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; next-level-cache = <&L2>; reg = <0x0>; + operating-points = < + /* kHz uV */ + 1608000 1350000 + 1416000 1250000 + 1200000 1150000 + 1008000 1075000 + 816000 975000 + 600000 950000 + 504000 925000 + 312000 875000 + >; + clock-latency = <40000>; + clocks = <&cru ARMCLK>; }; cpu@1 { device_type = "cpu"; @@ -65,6 +78,21 @@ }; }; + i2s0: i2s@1011a000 { + compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s"; + reg = <0x1011a000 0x2000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_bus>; + dmas = <&dmac1_s 6>, <&dmac1_s 7>; + dma-names = "tx", "rx"; + clock-names = "i2s_hclk", "i2s_clk"; + clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; + status = "disabled"; + }; + cru: clock-controller@20000000 { compatible = "rockchip,rk3188-cru"; reg = <0x20000000 0x1000>; @@ -83,7 +111,7 @@ #size-cells = <1>; ranges; - gpio0: gpio0@0x2000a000 { + gpio0: gpio0@2000a000 { compatible = "rockchip,rk3188-gpio-bank0"; reg = <0x2000a000 0x100>; interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; @@ -96,7 +124,7 @@ #interrupt-cells = <2>; }; - gpio1: gpio1@0x2003c000 { + gpio1: gpio1@2003c000 { compatible = "rockchip,gpio-bank"; reg = <0x2003c000 0x100>; interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; @@ -147,6 +175,45 @@ bias-disable; }; + emmc { + emmc_clk: emmc-clk { + rockchip,pins = <RK_GPIO0 24 RK_FUNC_2 &pcfg_pull_none>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = <RK_GPIO0 26 RK_FUNC_2 &pcfg_pull_up>; + }; + + emmc_rst: emmc-rst { + rockchip,pins = <RK_GPIO0 27 RK_FUNC_2 &pcfg_pull_none>; + }; + + /* + * The data pins are shared between nandc and emmc and + * not accessible through pinctrl. Also they should've + * been already set correctly by firmware, as + * flash/emmc is the boot-device. + */ + }; + + emac { + emac_xfer: emac-xfer { + rockchip,pins = <RK_GPIO3 16 RK_FUNC_2 &pcfg_pull_none>, /* tx_en */ + <RK_GPIO3 17 RK_FUNC_2 &pcfg_pull_none>, /* txd1 */ + <RK_GPIO3 18 RK_FUNC_2 &pcfg_pull_none>, /* txd0 */ + <RK_GPIO3 19 RK_FUNC_2 &pcfg_pull_none>, /* rxd0 */ + <RK_GPIO3 20 RK_FUNC_2 &pcfg_pull_none>, /* rxd1 */ + <RK_GPIO3 21 RK_FUNC_2 &pcfg_pull_none>, /* mac_clk */ + <RK_GPIO3 22 RK_FUNC_2 &pcfg_pull_none>, /* rx_err */ + <RK_GPIO3 23 RK_FUNC_2 &pcfg_pull_none>; /* crs_dvalid */ + }; + + emac_mdio: emac-mdio { + rockchip,pins = <RK_GPIO3 24 RK_FUNC_2 &pcfg_pull_none>, + <RK_GPIO3 25 RK_FUNC_2 &pcfg_pull_none>; + }; + }; + i2c0 { i2c0_xfer: i2c0-xfer { rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>, @@ -206,6 +273,42 @@ }; }; + spi0 { + spi0_clk: spi0-clk { + rockchip,pins = <RK_GPIO1 6 RK_FUNC_2 &pcfg_pull_up>; + }; + spi0_cs0: spi0-cs0 { + rockchip,pins = <RK_GPIO1 7 RK_FUNC_2 &pcfg_pull_up>; + }; + spi0_tx: spi0-tx { + rockchip,pins = <RK_GPIO1 5 RK_FUNC_2 &pcfg_pull_up>; + }; + spi0_rx: spi0-rx { + rockchip,pins = <RK_GPIO1 4 RK_FUNC_2 &pcfg_pull_up>; + }; + spi0_cs1: spi0-cs1 { + rockchip,pins = <RK_GPIO1 15 RK_FUNC_1 &pcfg_pull_up>; + }; + }; + + spi1 { + spi1_clk: spi1-clk { + rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_up>; + }; + spi1_cs0: spi1-cs0 { + rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_up>; + }; + spi1_rx: spi1-rx { + rockchip,pins = <RK_GPIO0 28 RK_FUNC_1 &pcfg_pull_up>; + }; + spi1_tx: spi1-tx { + rockchip,pins = <RK_GPIO0 29 RK_FUNC_1 &pcfg_pull_up>; + }; + spi1_cs1: spi1-cs1 { + rockchip,pins = <RK_GPIO1 14 RK_FUNC_2 &pcfg_pull_up>; + }; + }; + uart0 { uart0_xfer: uart0-xfer { rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>, @@ -320,9 +423,24 @@ <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>; }; }; + + i2s0 { + i2s0_bus: i2s0-bus { + rockchip,pins = <RK_GPIO1 16 RK_FUNC_1 &pcfg_pull_none>, + <RK_GPIO1 17 RK_FUNC_1 &pcfg_pull_none>, + <RK_GPIO1 18 RK_FUNC_1 &pcfg_pull_none>, + <RK_GPIO1 19 RK_FUNC_1 &pcfg_pull_none>, + <RK_GPIO1 20 RK_FUNC_1 &pcfg_pull_none>, + <RK_GPIO1 21 RK_FUNC_1 &pcfg_pull_none>; + }; + }; }; }; +&emac { + compatible = "rockchip,rk3188-emac"; +}; + &global_timer { interrupts = <GIC_PPI 11 0xf04>; }; @@ -381,6 +499,18 @@ pinctrl-0 = <&pwm3_out>; }; +&spi0 { + compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; +}; + +&spi1 { + compatible = "rockchip,rk3188-spi", "rockchip,rk3066-spi"; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer>; diff --git a/arch/arm/boot/dts/rk3288-evb-act8846.dts b/arch/arm/boot/dts/rk3288-evb-act8846.dts index 7d59ff4de408..a76dd44adb53 100644 --- a/arch/arm/boot/dts/rk3288-evb-act8846.dts +++ b/arch/arm/boot/dts/rk3288-evb-act8846.dts @@ -26,7 +26,7 @@ interrupts = <4 IRQ_TYPE_EDGE_FALLING>; pinctrl-names = "default"; - pinctrl-0 = <&hym8563_int>; + pinctrl-0 = <&pmic_int>; #clock-cells = <0>; clock-output-names = "xin32k"; @@ -124,11 +124,3 @@ }; }; }; - -&pinctrl { - hym8563 { - hym8563_int: hym8563-int { - rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; -}; diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts b/arch/arm/boot/dts/rk3288-evb-rk808.dts index 9a88b6c66396..d8c775e6d5fe 100644 --- a/arch/arm/boot/dts/rk3288-evb-rk808.dts +++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts @@ -16,3 +16,139 @@ / { compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288"; }; + +&cpu0 { + cpu0-supply = <&vdd_cpu>; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + rk808: pmic@1b { + compatible = "rockchip,rk808"; + reg = <0x1b>; + interrupt-parent = <&gpio0>; + interrupts = <4 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int>; + rockchip,system-power-controller; + wakeup-source; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk808-clkout2"; + + vcc8-supply = <&vcc_18>; + vcc9-supply = <&vcc_io>; + vcc10-supply = <&vcc_io>; + vcc12-supply = <&vcc_io>; + vddio-supply = <&vccio_pmu>; + + regulators { + vdd_cpu: DCDC_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1350000>; + regulator-name = "vdd_arm"; + }; + + vdd_gpu: DCDC_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1250000>; + regulator-name = "vdd_gpu"; + }; + + vcc_ddr: DCDC_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_ddr"; + }; + + vcc_io: DCDC_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_io"; + }; + + vccio_pmu: LDO_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_pmu"; + }; + + vcc_tp: LDO_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc_tp"; + }; + + vdd_10: LDO_REG3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd_10"; + }; + + vcc18_lcd: LDO_REG4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc18_lcd"; + }; + + vccio_sd: LDO_REG5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vccio_sd"; + }; + + vdd10_lcd: LDO_REG6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-name = "vdd10_lcd"; + }; + + vcc_18: LDO_REG7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc_18"; + }; + + vcca_codec: LDO_REG8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcca_codec"; + }; + + vcc_wl: SWITCH_REG1 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_wl"; + }; + + vcc_lcd: SWITCH_REG2 { + regulator-always-on; + regulator-boot-on; + regulator-name = "vcc_lcd"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi index 4f572093c8b4..3e067dd65d0c 100644 --- a/arch/arm/boot/dts/rk3288-evb.dtsi +++ b/arch/arm/boot/dts/rk3288-evb.dtsi @@ -10,6 +10,7 @@ * GNU General Public License for more details. */ +#include <dt-bindings/pwm/pwm.h> #include "rk3288.dtsi" / { @@ -17,6 +18,48 @@ reg = <0x0 0x80000000>; }; + backlight { + compatible = "pwm-backlight"; + brightness-levels = < + 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255>; + default-brightness-level = <128>; + enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bl_en>; + pwms = <&pwm0 0 1000000 PWM_POLARITY_INVERTED>; + }; + gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; @@ -49,6 +92,30 @@ }; }; +&emmc { + broken-cd; + bus-width = <8>; + cap-mmc-highspeed; + disable-wp; + non-removable; + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>; + status = "okay"; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + disable-wp; /* wp not hooked up */ + num-slots = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; + status = "okay"; +}; + &i2c0 { status = "okay"; }; @@ -57,6 +124,10 @@ status = "okay"; }; +&pwm0 { + status = "okay"; +}; + &uart0 { status = "okay"; }; @@ -77,13 +148,31 @@ status = "okay"; }; +&tsadc { + rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ + rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ + status = "okay"; +}; + &pinctrl { + backlight { + bl_en: bl-en { + rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + buttons { pwrbtn: pwrbtn { rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>; }; }; + pmic { + pmic_int: pmic-int { + rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + usb { host_vbus_drv: host-vbus-drv { rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; @@ -94,3 +183,7 @@ &usb_host0_ehci { status = "okay"; }; + +&usb_host1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rk3288-thermal.dtsi b/arch/arm/boot/dts/rk3288-thermal.dtsi new file mode 100644 index 000000000000..2695200c0af7 --- /dev/null +++ b/arch/arm/boot/dts/rk3288-thermal.dtsi @@ -0,0 +1,74 @@ +/* + * Device Tree Source for RK3288 SoC thermal + * + * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include <dt-bindings/thermal/thermal.h> + +reserve_thermal: reserve_thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsadc 0>; +}; + +cpu_thermal: cpu_thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsadc 1>; + + trips { + cpu_alert0: cpu_alert0 { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + cpu_crit: cpu_crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + +gpu_thermal: gpu_thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ + + thermal-sensors = <&tsadc 2>; + + trips { + gpu_alert0: gpu_alert0 { + temperature = <70000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "passive"; + }; + gpu_crit: gpu_crit { + temperature = <90000>; /* millicelsius */ + hysteresis = <2000>; /* millicelsius */ + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&gpu_alert0>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 5950b0a53224..fd19f00784bd 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -15,6 +15,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/pinctrl/rockchip.h> #include <dt-bindings/clock/rk3288-cru.h> +#include <dt-bindings/thermal/thermal.h> #include "skeleton.dtsi" / { @@ -29,36 +30,105 @@ i2c3 = &i2c3; i2c4 = &i2c4; i2c5 = &i2c5; + mshc0 = &emmc; + mshc1 = &sdmmc; + mshc2 = &sdio0; + mshc3 = &sdio1; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; serial3 = &uart3; serial4 = &uart4; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; }; cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "rockchip,rk3066-smp"; + rockchip,pmu = <&pmu>; - cpu@500 { + cpu0: cpu@500 { device_type = "cpu"; compatible = "arm,cortex-a12"; reg = <0x500>; + resets = <&cru SRST_CORE0>; + operating-points = < + /* KHz uV */ + 1608000 1350000 + 1512000 1300000 + 1416000 1200000 + 1200000 1100000 + 1008000 1050000 + 816000 1000000 + 696000 950000 + 600000 900000 + 408000 900000 + 312000 900000 + 216000 900000 + 126000 900000 + >; + #cooling-cells = <2>; /* min followed by max */ + clock-latency = <40000>; + clocks = <&cru ARMCLK>; }; cpu@501 { device_type = "cpu"; compatible = "arm,cortex-a12"; reg = <0x501>; + resets = <&cru SRST_CORE1>; }; cpu@502 { device_type = "cpu"; compatible = "arm,cortex-a12"; reg = <0x502>; + resets = <&cru SRST_CORE2>; }; cpu@503 { device_type = "cpu"; compatible = "arm,cortex-a12"; reg = <0x503>; + resets = <&cru SRST_CORE3>; + }; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dmac_peri: dma-controller@ff250000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xff250000 0x4000>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&cru ACLK_DMAC2>; + clock-names = "apb_pclk"; + }; + + dmac_bus_ns: dma-controller@ff600000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xff600000 0x4000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&cru ACLK_DMAC1>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + dmac_bus_s: dma-controller@ffb20000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xffb20000 0x4000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&cru ACLK_DMAC1>; + clock-names = "apb_pclk"; }; }; @@ -71,6 +141,7 @@ timer { compatible = "arm,armv7-timer"; + arm,cpu-registers-not-fw-configured; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, @@ -78,6 +149,101 @@ clock-frequency = <24000000>; }; + sdmmc: dwmmc@ff0c0000 { + compatible = "rockchip,rk3288-dw-mshc"; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; + clock-names = "biu", "ciu"; + fifo-depth = <0x100>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xff0c0000 0x4000>; + status = "disabled"; + }; + + sdio0: dwmmc@ff0d0000 { + compatible = "rockchip,rk3288-dw-mshc"; + clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>; + clock-names = "biu", "ciu"; + fifo-depth = <0x100>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xff0d0000 0x4000>; + status = "disabled"; + }; + + sdio1: dwmmc@ff0e0000 { + compatible = "rockchip,rk3288-dw-mshc"; + clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>; + clock-names = "biu", "ciu"; + fifo-depth = <0x100>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xff0e0000 0x4000>; + status = "disabled"; + }; + + emmc: dwmmc@ff0f0000 { + compatible = "rockchip,rk3288-dw-mshc"; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; + clock-names = "biu", "ciu"; + fifo-depth = <0x100>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xff0f0000 0x4000>; + status = "disabled"; + }; + + saradc: saradc@ff100000 { + compatible = "rockchip,saradc"; + reg = <0xff100000 0x100>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + #io-channel-cells = <1>; + clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + status = "disabled"; + }; + + spi0: spi@ff110000 { + compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; + clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac_peri 11>, <&dmac_peri 12>; + dma-names = "tx", "rx"; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; + reg = <0xff110000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@ff120000 { + compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; + clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac_peri 13>, <&dmac_peri 14>; + dma-names = "tx", "rx"; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; + reg = <0xff120000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@ff130000 { + compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi"; + clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&dmac_peri 15>, <&dmac_peri 16>; + dma-names = "tx", "rx"; + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; + reg = <0xff130000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c1: i2c@ff140000 { compatible = "rockchip,rk3288-i2c"; reg = <0xff140000 0x1000>; @@ -195,6 +361,25 @@ status = "disabled"; }; + thermal-zones { + #include "rk3288-thermal.dtsi" + }; + + tsadc: tsadc@ff280000 { + compatible = "rockchip,rk3288-tsadc"; + reg = <0xff280000 0x100>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; + clock-names = "tsadc", "apb_pclk"; + resets = <&cru SRST_TSADC>; + reset-names = "tsadc-apb"; + pinctrl-names = "default"; + pinctrl-0 = <&otp_out>; + #thermal-sensor-cells = <1>; + rockchip,hw-tshut-temp = <95000>; + status = "disabled"; + }; + usb_host0_ehci: usb@ff500000 { compatible = "generic-ehci"; reg = <0xff500000 0x100>; @@ -206,6 +391,26 @@ /* NOTE: ohci@ff520000 doesn't actually work on hardware */ + usb_host1: usb@ff540000 { + compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0xff540000 0x40000>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_USBHOST1>; + clock-names = "otg"; + status = "disabled"; + }; + + usb_otg: usb@ff580000 { + compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb", + "snps,dwc2"; + reg = <0xff580000 0x40000>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_OTG0>; + clock-names = "otg"; + status = "disabled"; + }; + usb_hsic: usb@ff5c0000 { compatible = "generic-ehci"; reg = <0xff5c0000 0x100>; @@ -241,6 +446,62 @@ status = "disabled"; }; + pwm0: pwm@ff680000 { + compatible = "rockchip,rk3288-pwm"; + reg = <0xff680000 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm1: pwm@ff680010 { + compatible = "rockchip,rk3288-pwm"; + reg = <0xff680010 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_pin>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm2: pwm@ff680020 { + compatible = "rockchip,rk3288-pwm"; + reg = <0xff680020 0x10>; + #pwm-cells = <3>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pin>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + status = "disabled"; + }; + + pwm3: pwm@ff680030 { + compatible = "rockchip,rk3288-pwm"; + reg = <0xff680030 0x10>; + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pin>; + clocks = <&cru PCLK_PWM>; + clock-names = "pwm"; + status = "disabled"; + }; + + bus_intmem@ff700000 { + compatible = "mmio-sram"; + reg = <0xff700000 0x18000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xff700000 0x18000>; + smp-sram@0 { + compatible = "rockchip,rk3066-smp-sram"; + reg = <0x00 0x10>; + }; + }; + pmu: power-management@ff730000 { compatible = "rockchip,rk3288-pmu", "syscon"; reg = <0xff730000 0x100>; @@ -257,6 +518,16 @@ rockchip,grf = <&grf>; #clock-cells = <1>; #reset-cells = <1>; + assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, + <&cru PLL_NPLL>, <&cru ACLK_CPU>, + <&cru HCLK_CPU>, <&cru PCLK_CPU>, + <&cru ACLK_PERI>, <&cru HCLK_PERI>, + <&cru PCLK_PERI>; + assigned-clock-rates = <594000000>, <400000000>, + <500000000>, <300000000>, + <150000000>, <75000000>, + <300000000>, <150000000>, + <75000000>; }; grf: syscon@ff770000 { @@ -271,6 +542,39 @@ status = "disabled"; }; + i2s: i2s@ff890000 { + compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s"; + reg = <0xff890000 0x10000>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>; + dma-names = "tx", "rx"; + clock-names = "i2s_hclk", "i2s_clk"; + clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s0_bus>; + status = "disabled"; + }; + + vopb_mmu: iommu@ff930300 { + compatible = "rockchip,iommu"; + reg = <0xff930300 0x100>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "vopb_mmu"; + #iommu-cells = <0>; + status = "disabled"; + }; + + vopl_mmu: iommu@ff940300 { + compatible = "rockchip,iommu"; + reg = <0xff940300 0x100>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "vopl_mmu"; + #iommu-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@ffc01000 { compatible = "arm,gic-400"; interrupt-controller; @@ -463,6 +767,17 @@ }; }; + i2s0 { + i2s0_bus: i2s0-bus { + rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>, + <6 1 RK_FUNC_1 &pcfg_pull_none>, + <6 2 RK_FUNC_1 &pcfg_pull_none>, + <6 3 RK_FUNC_1 &pcfg_pull_none>, + <6 4 RK_FUNC_1 &pcfg_pull_none>, + <6 8 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + sdmmc { sdmmc_clk: sdmmc-clk { rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>; @@ -488,6 +803,88 @@ }; }; + sdio0 { + sdio0_bus1: sdio0-bus1 { + rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdio0_bus4: sdio0-bus4 { + rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>, + <4 21 RK_FUNC_1 &pcfg_pull_up>, + <4 22 RK_FUNC_1 &pcfg_pull_up>, + <4 23 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdio0_cmd: sdio0-cmd { + rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdio0_clk: sdio0-clk { + rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>; + }; + + sdio0_cd: sdio0-cd { + rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdio0_wp: sdio0-wp { + rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdio0_pwr: sdio0-pwr { + rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdio0_bkpwr: sdio0-bkpwr { + rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>; + }; + + sdio0_int: sdio0-int { + rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>; + }; + }; + + sdio1 { + sdio1_bus1: sdio1-bus1 { + rockchip,pins = <3 24 4 &pcfg_pull_up>; + }; + + sdio1_bus4: sdio1-bus4 { + rockchip,pins = <3 24 4 &pcfg_pull_up>, + <3 25 4 &pcfg_pull_up>, + <3 26 4 &pcfg_pull_up>, + <3 27 4 &pcfg_pull_up>; + }; + + sdio1_cd: sdio1-cd { + rockchip,pins = <3 28 4 &pcfg_pull_up>; + }; + + sdio1_wp: sdio1-wp { + rockchip,pins = <3 29 4 &pcfg_pull_up>; + }; + + sdio1_bkpwr: sdio1-bkpwr { + rockchip,pins = <3 30 4 &pcfg_pull_up>; + }; + + sdio1_int: sdio1-int { + rockchip,pins = <3 31 4 &pcfg_pull_up>; + }; + + sdio1_cmd: sdio1-cmd { + rockchip,pins = <4 6 4 &pcfg_pull_up>; + }; + + sdio1_clk: sdio1-clk { + rockchip,pins = <4 7 4 &pcfg_pull_none>; + }; + + sdio1_pwr: sdio1-pwr { + rockchip,pins = <4 9 4 &pcfg_pull_up>; + }; + }; + emmc { emmc_clk: emmc-clk { rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>; @@ -524,6 +921,56 @@ }; }; + spi0 { + spi0_clk: spi0-clk { + rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>; + }; + spi0_cs0: spi0-cs0 { + rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>; + }; + spi0_tx: spi0-tx { + rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>; + }; + spi0_rx: spi0-rx { + rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>; + }; + spi0_cs1: spi0-cs1 { + rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>; + }; + }; + spi1 { + spi1_clk: spi1-clk { + rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>; + }; + spi1_cs0: spi1-cs0 { + rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>; + }; + spi1_rx: spi1-rx { + rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>; + }; + spi1_tx: spi1-tx { + rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>; + }; + }; + + spi2 { + spi2_cs1: spi2-cs1 { + rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>; + }; + spi2_clk: spi2-clk { + rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>; + }; + spi2_cs0: spi2-cs0 { + rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>; + }; + spi2_rx: spi2-rx { + rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>; + }; + spi2_tx: spi2-tx { + rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>; + }; + }; + uart0 { uart0_xfer: uart0-xfer { rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>, @@ -591,5 +1038,35 @@ rockchip,pins = <5 15 3 &pcfg_pull_none>; }; }; + + tsadc { + otp_out: otp-out { + rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>; + }; + }; + + pwm2 { + pwm2_pin: pwm2-pin { + rockchip,pins = <7 22 3 &pcfg_pull_none>; + }; + }; + + pwm3 { + pwm3_pin: pwm3-pin { + rockchip,pins = <7 23 3 &pcfg_pull_none>; + }; + }; }; }; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index 8caf85d83901..c54a9715dcfa 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -26,6 +26,53 @@ i2c2 = &i2c2; i2c3 = &i2c3; i2c4 = &i2c4; + mshc0 = &emmc; + mshc1 = &mmc0; + mshc2 = &mmc1; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + spi0 = &spi0; + spi1 = &spi1; + }; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dmac1_s: dma-controller@20018000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x20018000 0x4000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&cru ACLK_DMA1>; + clock-names = "apb_pclk"; + }; + + dmac1_ns: dma-controller@2001c000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x2001c000 0x4000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&cru ACLK_DMA1>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + dmac2: dma-controller@20078000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x20078000 0x4000>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + clocks = <&cru ACLK_DMA2>; + clock-names = "apb_pclk"; + }; }; xin24m: oscillator { @@ -91,16 +138,48 @@ status = "disabled"; }; + usb_otg: usb@10180000 { + compatible = "rockchip,rk3066-usb", "snps,dwc2"; + reg = <0x10180000 0x40000>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_OTG0>; + clock-names = "otg"; + status = "disabled"; + }; + + usb_host: usb@101c0000 { + compatible = "snps,dwc2"; + reg = <0x101c0000 0x40000>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_OTG1>; + clock-names = "otg"; + status = "disabled"; + }; + + emac: ethernet@10204000 { + compatible = "snps,arc-emac"; + reg = <0x10204000 0x3c>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + + rockchip,grf = <&grf>; + + clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>; + clock-names = "hclk", "macref"; + max-speed = <100>; + phy-mode = "rmii"; + + status = "disabled"; + }; + mmc0: dwmmc@10214000 { compatible = "rockchip,rk2928-dw-mshc"; reg = <0x10214000 0x1000>; interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; clock-names = "biu", "ciu"; - + fifo-depth = <256>; status = "disabled"; }; @@ -108,12 +187,19 @@ compatible = "rockchip,rk2928-dw-mshc"; reg = <0x10218000 0x1000>; interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; clock-names = "biu", "ciu"; + fifo-depth = <256>; + status = "disabled"; + }; + emmc: dwmmc@1021c000 { + compatible = "rockchip,rk2928-dw-mshc"; + reg = <0x1021c000 0x1000>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; + clock-names = "biu", "ciu"; + fifo-depth = <256>; status = "disabled"; }; @@ -135,7 +221,6 @@ #size-cells = <0>; rockchip,grf = <&grf>; - rockchip,bus-index = <0>; clock-names = "i2c"; clocks = <&cru PCLK_I2C0>; @@ -264,4 +349,40 @@ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; status = "disabled"; }; + + saradc: saradc@2006c000 { + compatible = "rockchip,saradc"; + reg = <0x2006c000 0x100>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + #io-channel-cells = <1>; + clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + status = "disabled"; + }; + + spi0: spi@20070000 { + compatible = "rockchip,rk3066-spi"; + clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x20070000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmac2 10>, <&dmac2 11>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + spi1: spi@20074000 { + compatible = "rockchip,rk3066-spi"; + clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; + clock-names = "spiclk", "apb_pclk"; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x20074000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmac2 12>, <&dmac2 13>; + dma-names = "tx", "rx"; + status = "disabled"; + }; }; diff --git a/arch/arm/boot/dts/s3c6410-mini6410.dts b/arch/arm/boot/dts/s3c6410-mini6410.dts index 57e00f9bce99..a25debb50401 100644 --- a/arch/arm/boot/dts/s3c6410-mini6410.dts +++ b/arch/arm/boot/dts/s3c6410-mini6410.dts @@ -198,10 +198,6 @@ status = "okay"; }; -&pwm { - status = "okay"; -}; - &pinctrl0 { gpio_leds: gpio-leds { samsung,pins = "gpk-4", "gpk-5", "gpk-6", "gpk-7"; diff --git a/arch/arm/boot/dts/s3c64xx.dtsi b/arch/arm/boot/dts/s3c64xx.dtsi index ff5bdaac987a..0ccb414cd268 100644 --- a/arch/arm/boot/dts/s3c64xx.dtsi +++ b/arch/arm/boot/dts/s3c64xx.dtsi @@ -172,7 +172,6 @@ clocks = <&clocks PCLK_PWM>; samsung,pwm-outputs = <0>, <1>; #pwm-cells = <3>; - status = "disabled"; }; pinctrl0: pinctrl@7f008000 { diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi index 45013b867c8d..5f4144d1e3a1 100644 --- a/arch/arm/boot/dts/sama5d3.dtsi +++ b/arch/arm/boot/dts/sama5d3.dtsi @@ -177,6 +177,9 @@ compatible = "atmel,at91sam9260-usart"; reg = <0xf001c000 0x100>; interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, + <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart0>; clocks = <&usart0_clk>; @@ -188,6 +191,9 @@ compatible = "atmel,at91sam9260-usart"; reg = <0xf0020000 0x100>; interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(5)>, + <&dma0 2 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1>; clocks = <&usart1_clk>; @@ -333,6 +339,9 @@ compatible = "atmel,at91sam9260-usart"; reg = <0xf8020000 0x100>; interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(7)>, + <&dma1 2 (AT91_DMA_CFG_PER_ID(8) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart2>; clocks = <&usart2_clk>; @@ -344,6 +353,9 @@ compatible = "atmel,at91sam9260-usart"; reg = <0xf8024000 0x100>; interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(9)>, + <&dma1 2 (AT91_DMA_CFG_PER_ID(10) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart3>; clocks = <&usart3_clk>; @@ -402,14 +414,19 @@ }; ramc0: ramc@ffffea00 { - compatible = "atmel,at91sam9g45-ddramc"; + compatible = "atmel,sama5d3-ddramc"; reg = <0xffffea00 0x200>; + clocks = <&ddrck>, <&mpddr_clk>; + clock-names = "ddrck", "mpddr"; }; dbgu: serial@ffffee00 { compatible = "atmel,at91sam9260-usart"; reg = <0xffffee00 0x200>; interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(13)>, + <&dma1 2 (AT91_DMA_CFG_PER_ID(14) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dbgu>; clocks = <&dbgu_clk>; @@ -428,7 +445,7 @@ pinctrl@fffff200 { #address-cells = <1>; #size-cells = <1>; - compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; + compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus"; ranges = <0xfffff200 0xfffff200 0xa00>; atmel,mux-mask = < /* A B C */ @@ -1003,6 +1020,11 @@ reg = <2>; }; + hsmc_clk: hsmc_clk { + #clock-cells = <0>; + reg = <5>; + }; + pioA_clk: pioA_clk { #clock-cells = <0>; reg = <6>; @@ -1170,6 +1192,11 @@ #clock-cells = <0>; reg = <48>; }; + + mpddr_clk: mpddr_clk { + #clock-cells = <0>; + reg = <49>; + }; }; }; @@ -1178,6 +1205,11 @@ reg = <0xfffffe00 0x10>; }; + shutdown-controller@fffffe10 { + compatible = "atmel,at91sam9x5-shdwc"; + reg = <0xfffffe10 0x10>; + }; + pit: timer@fffffe30 { compatible = "atmel,at91sam9260-pit"; reg = <0xfffffe30 0xf>; @@ -1393,6 +1425,7 @@ 0xffffc000 0x00000070 /* NFC HSMC regs */ 0x00200000 0x00100000 /* NFC SRAM banks */ >; + clocks = <&hsmc_clk>; }; }; }; diff --git a/arch/arm/boot/dts/sama5d31.dtsi b/arch/arm/boot/dts/sama5d31.dtsi index 7997dc9863ed..883878b32971 100644 --- a/arch/arm/boot/dts/sama5d31.dtsi +++ b/arch/arm/boot/dts/sama5d31.dtsi @@ -12,5 +12,5 @@ #include "sama5d3_uart.dtsi" / { - compatible = "atmel,samad31", "atmel,sama5d3", "atmel,sama5"; + compatible = "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5"; }; diff --git a/arch/arm/boot/dts/sama5d33.dtsi b/arch/arm/boot/dts/sama5d33.dtsi index 39f832253caf..4b4434aca351 100644 --- a/arch/arm/boot/dts/sama5d33.dtsi +++ b/arch/arm/boot/dts/sama5d33.dtsi @@ -10,5 +10,5 @@ #include "sama5d3_gmac.dtsi" / { - compatible = "atmel,samad33", "atmel,sama5d3", "atmel,sama5"; + compatible = "atmel,sama5d33", "atmel,sama5d3", "atmel,sama5"; }; diff --git a/arch/arm/boot/dts/sama5d34.dtsi b/arch/arm/boot/dts/sama5d34.dtsi index 89cda2c0da39..aa01573fdee9 100644 --- a/arch/arm/boot/dts/sama5d34.dtsi +++ b/arch/arm/boot/dts/sama5d34.dtsi @@ -12,5 +12,5 @@ #include "sama5d3_mci2.dtsi" / { - compatible = "atmel,samad34", "atmel,sama5d3", "atmel,sama5"; + compatible = "atmel,sama5d34", "atmel,sama5d3", "atmel,sama5"; }; diff --git a/arch/arm/boot/dts/sama5d35.dtsi b/arch/arm/boot/dts/sama5d35.dtsi index d20cd71b5f0e..16c39f4c96a4 100644 --- a/arch/arm/boot/dts/sama5d35.dtsi +++ b/arch/arm/boot/dts/sama5d35.dtsi @@ -14,5 +14,5 @@ #include "sama5d3_tcb1.dtsi" / { - compatible = "atmel,samad35", "atmel,sama5d3", "atmel,sama5"; + compatible = "atmel,sama5d35", "atmel,sama5d3", "atmel,sama5"; }; diff --git a/arch/arm/boot/dts/sama5d36.dtsi b/arch/arm/boot/dts/sama5d36.dtsi index db58cad6acd3..e85139ef40af 100644 --- a/arch/arm/boot/dts/sama5d36.dtsi +++ b/arch/arm/boot/dts/sama5d36.dtsi @@ -16,5 +16,5 @@ #include "sama5d3_uart.dtsi" / { - compatible = "atmel,samad36", "atmel,sama5d3", "atmel,sama5"; + compatible = "atmel,sama5d36", "atmel,sama5d3", "atmel,sama5"; }; diff --git a/arch/arm/boot/dts/sama5d3_can.dtsi b/arch/arm/boot/dts/sama5d3_can.dtsi index a0775851cce5..eaf41451ad0c 100644 --- a/arch/arm/boot/dts/sama5d3_can.dtsi +++ b/arch/arm/boot/dts/sama5d3_can.dtsi @@ -40,7 +40,7 @@ atmel,clk-output-range = <0 66000000>; }; - can1_clk: can0_clk { + can1_clk: can1_clk { #clock-cells = <0>; reg = <41>; atmel,clk-output-range = <0 66000000>; diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi index f7d8583eef82..cfcd200b0c17 100644 --- a/arch/arm/boot/dts/sama5d3xcm.dtsi +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi @@ -8,7 +8,7 @@ */ / { - compatible = "atmel,samad3xcm", "atmel,sama5d3", "atmel,sama5"; + compatible = "atmel,sama5d3xcm", "atmel,sama5d3", "atmel,sama5"; chosen { bootargs = "console=ttyS0,115200 rootfstype=ubifs ubi.mtd=5 root=ubi0:rootfs"; @@ -36,6 +36,36 @@ macb0: ethernet@f0028000 { phy-mode = "rgmii"; + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@1 { + reg = <0x1>; + interrupt-parent = <&pioB>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + txen-skew-ps = <800>; + txc-skew-ps = <3000>; + rxdv-skew-ps = <400>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <400>; + rxd1-skew-ps = <400>; + rxd2-skew-ps = <400>; + rxd3-skew-ps = <400>; + }; + + ethernet-phy@7 { + reg = <0x7>; + interrupt-parent = <&pioB>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + txen-skew-ps = <800>; + txc-skew-ps = <3000>; + rxdv-skew-ps = <400>; + rxc-skew-ps = <3000>; + rxd0-skew-ps = <400>; + rxd1-skew-ps = <400>; + rxd2-skew-ps = <400>; + rxd3-skew-ps = <400>; + }; }; pmc: pmc@fffffc00 { diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi index b8c6f20e780c..49c10d33df30 100644 --- a/arch/arm/boot/dts/sama5d3xmb.dtsi +++ b/arch/arm/boot/dts/sama5d3xmb.dtsi @@ -25,6 +25,8 @@ }; spi0: spi@f0004000 { + dmas = <0>, <0>; /* Do not use DMA for spi0 */ + m25p80@0 { compatible = "atmel,at25df321a"; spi-max-frequency = <50000000>; @@ -51,6 +53,7 @@ }; usart1: serial@f0020000 { + dmas = <0>, <0>; /* Do not use DMA for usart1 */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts_cts>; status = "okay"; @@ -132,6 +135,7 @@ }; dbgu: serial@ffffee00 { + dmas = <0>, <0>; /* Do not use DMA for dbgu */ status = "okay"; }; diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi new file mode 100644 index 000000000000..1b0f30c2c4a5 --- /dev/null +++ b/arch/arm/boot/dts/sama5d4.dtsi @@ -0,0 +1,1309 @@ +/* + * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC + * + * Copyright (C) 2014 Atmel, + * 2014 Nicolas Ferre <nicolas.ferre@atmel.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "skeleton.dtsi" +#include <dt-bindings/clock/at91.h> +#include <dt-bindings/dma/at91.h> +#include <dt-bindings/pinctrl/at91.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Atmel SAMA5D4 family SoC"; + compatible = "atmel,sama5d4"; + interrupt-parent = <&aic>; + + aliases { + serial0 = &usart3; + serial1 = &usart4; + serial2 = &usart2; + gpio0 = &pioA; + gpio1 = &pioB; + gpio2 = &pioC; + gpio4 = &pioE; + tcb0 = &tcb0; + tcb1 = &tcb1; + i2c2 = &i2c2; + }; + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a5"; + reg = <0>; + next-level-cache = <&L2>; + }; + }; + + memory { + reg = <0x20000000 0x20000000>; + }; + + clocks { + slow_xtal: slow_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + main_xtal: main_xtal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + adc_op_clk: adc_op_clk{ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + }; + }; + + ahb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usb0: gadget@00400000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91sam9rl-udc"; + reg = <0x00400000 0x100000 + 0xfc02c000 0x4000>; + interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&udphs_clk>, <&utmi>; + clock-names = "pclk", "hclk"; + status = "disabled"; + + ep0 { + reg = <0>; + atmel,fifo-size = <64>; + atmel,nb-banks = <1>; + }; + + ep1 { + reg = <1>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep2 { + reg = <2>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <3>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep3 { + reg = <3>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep4 { + reg = <4>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep5 { + reg = <5>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep6 { + reg = <6>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep7 { + reg = <7>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-dma; + atmel,can-isoc; + }; + + ep8 { + reg = <8>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-isoc; + }; + + ep9 { + reg = <9>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-isoc; + }; + + ep10 { + reg = <10>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-isoc; + }; + + ep11 { + reg = <11>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-isoc; + }; + + ep12 { + reg = <12>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-isoc; + }; + + ep13 { + reg = <13>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-isoc; + }; + + ep14 { + reg = <14>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-isoc; + }; + + ep15 { + reg = <15>; + atmel,fifo-size = <1024>; + atmel,nb-banks = <2>; + atmel,can-isoc; + }; + }; + + usb1: ohci@00500000 { + compatible = "atmel,at91rm9200-ohci", "usb-ohci"; + reg = <0x00500000 0x100000>; + interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, + <&uhpck>; + clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; + status = "disabled"; + }; + + usb2: ehci@00600000 { + compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; + reg = <0x00600000 0x100000>; + interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; + clocks = <&usb>, <&uhphs_clk>, <&uhpck>; + clock-names = "usb_clk", "ehci_clk", "uhpck"; + status = "disabled"; + }; + + L2: cache-controller@00a00000 { + compatible = "arm,pl310-cache"; + reg = <0x00a00000 0x1000>; + interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>; + cache-unified; + cache-level = <2>; + }; + + nand0: nand@80000000 { + compatible = "atmel,at91rm9200-nand"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = < 0x80000000 0x08000000 /* EBI CS3 */ + 0xfc05c070 0x00000490 /* SMC PMECC regs */ + 0xfc05c500 0x00000100 /* SMC PMECC Error Location regs */ + >; + interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>; + atmel,nand-addr-offset = <21>; + atmel,nand-cmd-offset = <22>; + atmel,nand-has-dma; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + status = "disabled"; + + nfc@90000000 { + compatible = "atmel,sama5d3-nfc"; + #address-cells = <1>; + #size-cells = <1>; + reg = < + 0x90000000 0x10000000 /* NFC Command Registers */ + 0xfc05c000 0x00000070 /* NFC HSMC regs */ + 0x00100000 0x00100000 /* NFC SRAM banks */ + >; + clocks = <&hsmc_clk>; + atmel,write-by-sram; + }; + }; + + apb { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + dma1: dma-controller@f0004000 { + compatible = "atmel,sama5d4-dma"; + reg = <0xf0004000 0x200>; + interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells = <1>; + clocks = <&dma1_clk>; + clock-names = "dma_clk"; + }; + + ramc0: ramc@f0010000 { + compatible = "atmel,sama5d3-ddramc"; + reg = <0xf0010000 0x200>; + clocks = <&ddrck>, <&mpddr_clk>; + clock-names = "ddrck", "mpddr"; + }; + + dma0: dma-controller@f0014000 { + compatible = "atmel,sama5d4-dma"; + reg = <0xf0014000 0x200>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>; + #dma-cells = <1>; + clocks = <&dma0_clk>; + clock-names = "dma_clk"; + }; + + pmc: pmc@f0018000 { + compatible = "atmel,sama5d3-pmc"; + reg = <0xf0018000 0x120>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + #interrupt-cells = <1>; + + main_rc_osc: main_rc_osc { + compatible = "atmel,at91sam9x5-clk-main-rc-osc"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = <AT91_PMC_MOSCRCS>; + clock-frequency = <12000000>; + clock-accuracy = <100000000>; + }; + + main_osc: main_osc { + compatible = "atmel,at91rm9200-clk-main-osc"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = <AT91_PMC_MOSCS>; + clocks = <&main_xtal>; + }; + + main: mainck { + compatible = "atmel,at91sam9x5-clk-main"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = <AT91_PMC_MOSCSELS>; + clocks = <&main_rc_osc &main_osc>; + }; + + plla: pllack { + compatible = "atmel,sama5d3-clk-pll"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = <AT91_PMC_LOCKA>; + clocks = <&main>; + reg = <0>; + atmel,clk-input-range = <12000000 12000000>; + #atmel,pll-clk-output-range-cells = <4>; + atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>; + }; + + plladiv: plladivck { + compatible = "atmel,at91sam9x5-clk-plldiv"; + #clock-cells = <0>; + clocks = <&plla>; + }; + + utmi: utmick { + compatible = "atmel,at91sam9x5-clk-utmi"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = <AT91_PMC_LOCKU>; + clocks = <&main>; + }; + + mck: masterck { + compatible = "atmel,at91sam9x5-clk-master"; + #clock-cells = <0>; + interrupt-parent = <&pmc>; + interrupts = <AT91_PMC_MCKRDY>; + clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; + atmel,clk-output-range = <125000000 177000000>; + atmel,clk-divisors = <1 2 4 3>; + }; + + h32ck: h32mxck { + #clock-cells = <0>; + compatible = "atmel,sama5d4-clk-h32mx"; + clocks = <&mck>; + }; + + usb: usbck { + compatible = "atmel,at91sam9x5-clk-usb"; + #clock-cells = <0>; + clocks = <&plladiv>, <&utmi>; + }; + + prog: progck { + compatible = "atmel,at91sam9x5-clk-programmable"; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&pmc>; + clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; + + prog0: prog0 { + #clock-cells = <0>; + reg = <0>; + interrupts = <AT91_PMC_PCKRDY(0)>; + }; + + prog1: prog1 { + #clock-cells = <0>; + reg = <1>; + interrupts = <AT91_PMC_PCKRDY(1)>; + }; + + prog2: prog2 { + #clock-cells = <0>; + reg = <2>; + interrupts = <AT91_PMC_PCKRDY(2)>; + }; + }; + + smd: smdclk { + compatible = "atmel,at91sam9x5-clk-smd"; + #clock-cells = <0>; + clocks = <&plladiv>, <&utmi>; + }; + + systemck { + compatible = "atmel,at91rm9200-clk-system"; + #address-cells = <1>; + #size-cells = <0>; + + ddrck: ddrck { + #clock-cells = <0>; + reg = <2>; + clocks = <&mck>; + }; + + lcdck: lcdck { + #clock-cells = <0>; + reg = <4>; + clocks = <&smd>; + }; + + smdck: smdck { + #clock-cells = <0>; + reg = <4>; + clocks = <&smd>; + }; + + uhpck: uhpck { + #clock-cells = <0>; + reg = <6>; + clocks = <&usb>; + }; + + udpck: udpck { + #clock-cells = <0>; + reg = <7>; + clocks = <&usb>; + }; + + pck0: pck0 { + #clock-cells = <0>; + reg = <8>; + clocks = <&prog0>; + }; + + pck1: pck1 { + #clock-cells = <0>; + reg = <9>; + clocks = <&prog1>; + }; + + pck2: pck2 { + #clock-cells = <0>; + reg = <10>; + clocks = <&prog2>; + }; + }; + + periph32ck { + compatible = "atmel,at91sam9x5-clk-peripheral"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&h32ck>; + + pioD_clk: pioD_clk { + #clock-cells = <0>; + reg = <5>; + }; + + usart0_clk: usart0_clk { + #clock-cells = <0>; + reg = <6>; + }; + + usart1_clk: usart1_clk { + #clock-cells = <0>; + reg = <7>; + }; + + icm_clk: icm_clk { + #clock-cells = <0>; + reg = <9>; + }; + + aes_clk: aes_clk { + #clock-cells = <0>; + reg = <12>; + }; + + tdes_clk: tdes_clk { + #clock-cells = <0>; + reg = <14>; + }; + + sha_clk: sha_clk { + #clock-cells = <0>; + reg = <15>; + }; + + matrix1_clk: matrix1_clk { + #clock-cells = <0>; + reg = <17>; + }; + + hsmc_clk: hsmc_clk { + #clock-cells = <0>; + reg = <22>; + }; + + pioA_clk: pioA_clk { + #clock-cells = <0>; + reg = <23>; + }; + + pioB_clk: pioB_clk { + #clock-cells = <0>; + reg = <24>; + }; + + pioC_clk: pioC_clk { + #clock-cells = <0>; + reg = <25>; + }; + + pioE_clk: pioE_clk { + #clock-cells = <0>; + reg = <26>; + }; + + uart0_clk: uart0_clk { + #clock-cells = <0>; + reg = <27>; + }; + + uart1_clk: uart1_clk { + #clock-cells = <0>; + reg = <28>; + }; + + usart2_clk: usart2_clk { + #clock-cells = <0>; + reg = <29>; + }; + + usart3_clk: usart3_clk { + #clock-cells = <0>; + reg = <30>; + }; + + usart4_clk: usart4_clk { + #clock-cells = <0>; + reg = <31>; + }; + + twi0_clk: twi0_clk { + reg = <32>; + #clock-cells = <0>; + }; + + twi1_clk: twi1_clk { + #clock-cells = <0>; + reg = <33>; + }; + + twi2_clk: twi2_clk { + #clock-cells = <0>; + reg = <34>; + }; + + mci0_clk: mci0_clk { + #clock-cells = <0>; + reg = <35>; + }; + + mci1_clk: mci1_clk { + #clock-cells = <0>; + reg = <36>; + }; + + spi0_clk: spi0_clk { + #clock-cells = <0>; + reg = <37>; + }; + + spi1_clk: spi1_clk { + #clock-cells = <0>; + reg = <38>; + }; + + spi2_clk: spi2_clk { + #clock-cells = <0>; + reg = <39>; + }; + + tcb0_clk: tcb0_clk { + #clock-cells = <0>; + reg = <40>; + }; + + tcb1_clk: tcb1_clk { + #clock-cells = <0>; + reg = <41>; + }; + + tcb2_clk: tcb2_clk { + #clock-cells = <0>; + reg = <42>; + }; + + pwm_clk: pwm_clk { + #clock-cells = <0>; + reg = <43>; + }; + + adc_clk: adc_clk { + #clock-cells = <0>; + reg = <44>; + }; + + dbgu_clk: dbgu_clk { + #clock-cells = <0>; + reg = <45>; + }; + + uhphs_clk: uhphs_clk { + #clock-cells = <0>; + reg = <46>; + }; + + udphs_clk: udphs_clk { + #clock-cells = <0>; + reg = <47>; + }; + + ssc0_clk: ssc0_clk { + #clock-cells = <0>; + reg = <48>; + }; + + ssc1_clk: ssc1_clk { + #clock-cells = <0>; + reg = <49>; + }; + + trng_clk: trng_clk { + #clock-cells = <0>; + reg = <53>; + }; + + macb0_clk: macb0_clk { + #clock-cells = <0>; + reg = <54>; + }; + + macb1_clk: macb1_clk { + #clock-cells = <0>; + reg = <55>; + }; + + fuse_clk: fuse_clk { + #clock-cells = <0>; + reg = <57>; + }; + + securam_clk: securam_clk { + #clock-cells = <0>; + reg = <59>; + }; + + smd_clk: smd_clk { + #clock-cells = <0>; + reg = <61>; + }; + + twi3_clk: twi3_clk { + #clock-cells = <0>; + reg = <62>; + }; + + catb_clk: catb_clk { + #clock-cells = <0>; + reg = <63>; + }; + }; + + periph64ck { + compatible = "atmel,at91sam9x5-clk-peripheral"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mck>; + + dma0_clk: dma0_clk { + #clock-cells = <0>; + reg = <8>; + }; + + cpkcc_clk: cpkcc_clk { + #clock-cells = <0>; + reg = <10>; + }; + + aesb_clk: aesb_clk { + #clock-cells = <0>; + reg = <13>; + }; + + mpddr_clk: mpddr_clk { + #clock-cells = <0>; + reg = <16>; + }; + + matrix0_clk: matrix0_clk { + #clock-cells = <0>; + reg = <18>; + }; + + vdec_clk: vdec_clk { + #clock-cells = <0>; + reg = <19>; + }; + + dma1_clk: dma1_clk { + #clock-cells = <0>; + reg = <50>; + }; + + lcd_clk: lcd_clk { + #clock-cells = <0>; + reg = <51>; + }; + + isi_clk: isi_clk { + #clock-cells = <0>; + reg = <52>; + }; + }; + }; + + mmc0: mmc@f8000000 { + compatible = "atmel,hsmci"; + reg = <0xf8000000 0x600>; + interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(0))>; + dma-names = "rxtx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mci0_clk>; + clock-names = "mci_clk"; + }; + + spi0: spi@f8010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91rm9200-spi"; + reg = <0xf8010000 0x100>; + interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(10))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(11))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi0>; + clocks = <&spi0_clk>; + clock-names = "spi_clk"; + status = "disabled"; + }; + + i2c0: i2c@f8014000 { + compatible = "atmel,at91sam9x5-i2c"; + reg = <0xf8014000 0x4000>; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(2))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(3))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&twi0_clk>; + status = "disabled"; + }; + + tcb0: timer@f801c000 { + compatible = "atmel,at91sam9x5-tcb"; + reg = <0xf801c000 0x100>; + interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tcb0_clk>; + clock-names = "t0_clk"; + }; + + macb0: ethernet@f8020000 { + compatible = "atmel,sama5d4-gem"; + reg = <0xf8020000 0x100>; + interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_rmii>; + clocks = <&macb0_clk>, <&macb0_clk>; + clock-names = "hclk", "pclk"; + status = "disabled"; + }; + + i2c2: i2c@f8024000 { + compatible = "atmel,at91sam9x5-i2c"; + reg = <0xf8024000 0x4000>; + interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(6))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(7))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&twi2_clk>; + status = "disabled"; + }; + + mmc1: mmc@fc000000 { + compatible = "atmel,hsmci"; + reg = <0xfc000000 0x600>; + interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(1))>; + dma-names = "rxtx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&mci1_clk>; + clock-names = "mci_clk"; + }; + + usart2: serial@fc008000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfc008000 0x100>; + interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(16))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(17))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>; + clocks = <&usart2_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + usart3: serial@fc00c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfc00c000 0x100>; + interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(18))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(19))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart3>; + clocks = <&usart3_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + usart4: serial@fc010000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfc010000 0x100>; + interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>; + dmas = <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(20))>, + <&dma1 + (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) + | AT91_XDMAC_DT_PERID(21))>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart4>; + clocks = <&usart4_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + tcb1: timer@fc020000 { + compatible = "atmel,at91sam9x5-tcb"; + reg = <0xfc020000 0x100>; + interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&tcb1_clk>; + clock-names = "t0_clk"; + }; + + adc0: adc@fc034000 { + compatible = "atmel,at91sam9x5-adc"; + reg = <0xfc034000 0x100>; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>; + pinctrl-names = "default"; + pinctrl-0 = < + /* external trigger is conflict with USBA_VBUS */ + &pinctrl_adc0_ad0 + &pinctrl_adc0_ad1 + &pinctrl_adc0_ad2 + &pinctrl_adc0_ad3 + &pinctrl_adc0_ad4 + >; + clocks = <&adc_clk>, + <&adc_op_clk>; + clock-names = "adc_clk", "adc_op_clk"; + atmel,adc-channels-used = <0x01f>; + atmel,adc-startup-time = <40>; + atmel,adc-use-external; + atmel,adc-vref = <3000>; + atmel,adc-res = <8 10>; + atmel,adc-sample-hold-time = <11>; + atmel,adc-res-names = "lowres", "highres"; + atmel,adc-ts-pressure-threshold = <10000>; + status = "disabled"; + + trigger@0 { + trigger-name = "external-rising"; + trigger-value = <0x1>; + trigger-external; + }; + trigger@1 { + trigger-name = "external-falling"; + trigger-value = <0x2>; + trigger-external; + }; + trigger@2 { + trigger-name = "external-any"; + trigger-value = <0x3>; + trigger-external; + }; + trigger@3 { + trigger-name = "continuous"; + trigger-value = <0x6>; + }; + }; + + rstc@fc068600 { + compatible = "atmel,at91sam9g45-rstc"; + reg = <0xfc068600 0x10>; + }; + + shdwc@fc068610 { + compatible = "atmel,at91sam9x5-shdwc"; + reg = <0xfc068610 0x10>; + }; + + pit: timer@fc068630 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfc068630 0xf>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; + clocks = <&h32ck>; + }; + + watchdog@fc068640 { + compatible = "atmel,at91sam9260-wdt"; + reg = <0xfc068640 0x10>; + status = "disabled"; + }; + + sckc@fc068650 { + compatible = "atmel,at91sam9x5-sckc"; + reg = <0xfc068650 0x4>; + + slow_rc_osc: slow_rc_osc { + compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-accuracy = <250000000>; + atmel,startup-time-usec = <75>; + }; + + slow_osc: slow_osc { + compatible = "atmel,at91sam9x5-clk-slow-osc"; + #clock-cells = <0>; + clocks = <&slow_xtal>; + atmel,startup-time-usec = <1200000>; + }; + + clk32k: slowck { + compatible = "atmel,at91sam9x5-clk-slow"; + #clock-cells = <0>; + clocks = <&slow_rc_osc &slow_osc>; + }; + }; + + rtc@fc0686b0 { + compatible = "atmel,at91rm9200-rtc"; + reg = <0xfc0686b0 0x30>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + }; + + dbgu: serial@fc069000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfc069000 0x200>; + interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dbgu>; + clocks = <&dbgu_clk>; + clock-names = "usart"; + status = "disabled"; + }; + + + pinctrl@fc06a000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; + ranges = <0xfc06a000 0xfc06a000 0x4000>; + /* WARNING: revisit as pin spec has changed */ + atmel,mux-mask = < + /* A B C */ + 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */ + 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */ + 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */ + 0x00000000 0x00000000 0x00000000 /* pioD */ + 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */ + >; + + pioA: gpio@fc06a000 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfc06a000 0x100>; + interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioA_clk>; + }; + + pioB: gpio@fc06b000 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfc06b000 0x100>; + interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioB_clk>; + }; + + pioC: gpio@fc06c000 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfc06c000 0x100>; + interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioC_clk>; + }; + + pioE: gpio@fc06d000 { + compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; + reg = <0xfc06d000 0x100>; + interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>; + #gpio-cells = <2>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&pioE_clk>; + }; + + /* pinctrl pin settings */ + adc0 { + pinctrl_adc0_adtrg: adc0_adtrg { + atmel,pins = + <AT91_PIOE 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with USBA_VBUS */ + }; + pinctrl_adc0_ad0: adc0_ad0 { + atmel,pins = + <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + pinctrl_adc0_ad1: adc0_ad1 { + atmel,pins = + <AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + pinctrl_adc0_ad2: adc0_ad2 { + atmel,pins = + <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + pinctrl_adc0_ad3: adc0_ad3 { + atmel,pins = + <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + pinctrl_adc0_ad4: adc0_ad4 { + atmel,pins = + <AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + }; + + dbgu { + pinctrl_dbgu: dbgu-0 { + atmel,pins = + <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>, /* conflicts with D14 and TDI */ + <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* conflicts with D15 and TDO */ + }; + }; + + i2c0 { + pinctrl_i2c0: i2c0-0 { + atmel,pins = + <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE + AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; + }; + }; + + i2c2 { + pinctrl_i2c2: i2c2-0 { + atmel,pins = + <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* TWD2, conflicts with RD0 and PWML1 */ + AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */ + }; + }; + + macb0 { + pinctrl_macb0_rmii: macb0_rmii-0 { + atmel,pins = + <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX0 */ + AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX1 */ + AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX0 */ + AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX1 */ + AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXDV */ + AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXER */ + AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXEN */ + AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXCK */ + AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDC */ + AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDIO */ + >; + }; + }; + + mmc0 { + pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { + atmel,pins = + <AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* MCI0_CK, conflict with PCK1(ISI_MCK) */ + AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_CDB, conflict with NAND_D0 */ + AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB0, conflict with NAND_D1 */ + >; + }; + pinctrl_mmc0_dat1_3: mmc0_dat1_3 { + atmel,pins = + <AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB1, conflict with NAND_D2 */ + AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB2, conflict with NAND_D3 */ + AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB3, conflict with NAND_D4 */ + >; + }; + }; + + mmc1 { + pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { + atmel,pins = + <AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* MCI1_CK */ + AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_CDA */ + AT91_PIOE 20 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA0 */ + >; + }; + pinctrl_mmc1_dat1_3: mmc1_dat1_3 { + atmel,pins = + <AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA1 */ + AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA2 */ + AT91_PIOE 23 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA3 */ + >; + }; + }; + + nand0 { + pinctrl_nand: nand-0 { + atmel,pins = + <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A Read Enable */ + AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A Write Enable */ + + AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC17 ALE */ + AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC18 CLE */ + + AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC15 NCS3/Chip Enable */ + AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC16 NANDRDY */ + AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 Data bit 0 */ + AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 Data bit 1 */ + AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 Data bit 2 */ + AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 Data bit 3 */ + AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 Data bit 4 */ + AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 Data bit 5 */ + AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A Data bit 6 */ + AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC12 periph A Data bit 7 */ + }; + }; + + spi0 { + pinctrl_spi0: spi0-0 { + atmel,pins = + <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MISO */ + AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MOSI */ + AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_SPCK */ + >; + }; + }; + + usart2 { + pinctrl_usart2: usart2-0 { + atmel,pins = + <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD - conflicts with G0_CRS, ISI_HSYNC */ + AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD - conflicts with G0_COL, PCK2 */ + >; + }; + pinctrl_usart2_rts: usart2_rts-0 { + atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_RX3, PWMH1 */ + }; + pinctrl_usart2_cts: usart2_cts-0 { + atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_TXER, ISI_VSYNC */ + }; + }; + + usart3 { + pinctrl_usart3: usart3-0 { + atmel,pins = + <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */ + AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */ + >; + }; + }; + + usart4 { + pinctrl_usart4: usart4-0 { + atmel,pins = + <AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */ + AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */ + >; + }; + pinctrl_usart4_rts: usart4_rts-0 { + atmel,pins = <AT91_PIOE 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with NWAIT, A19 */ + }; + pinctrl_usart4_cts: usart4_cts-0 { + atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with A0/NBS0, MCI0_CDB */ + }; + }; + }; + + aic: interrupt-controller@fc06e000 { + #interrupt-cells = <3>; + compatible = "atmel,sama5d4-aic"; + interrupt-controller; + reg = <0xfc06e000 0x200>; + atmel,external-irqs = <56>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/sh7372.dtsi b/arch/arm/boot/dts/sh7372.dtsi index 249f65be2a50..f863a10cb1b2 100644 --- a/arch/arm/boot/dts/sh7372.dtsi +++ b/arch/arm/boot/dts/sh7372.dtsi @@ -21,6 +21,7 @@ compatible = "arm,cortex-a8"; device_type = "cpu"; reg = <0x0>; + clock-frequency = <800000000>; }; }; diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts index 18662aec2ec4..939be1299ca6 100644 --- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts +++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts @@ -40,6 +40,7 @@ chosen { bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel rw"; + stdout-path = &scifa4; }; memory { @@ -66,7 +67,7 @@ }; vmmc_sdhi0: regulator@2 { - compatible = "regulator-fixed"; + compatible = "regulator-fixed"; regulator-name = "SDHI0 Vcc"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -75,7 +76,7 @@ }; vmmc_sdhi2: regulator@3 { - compatible = "regulator-fixed"; + compatible = "regulator-fixed"; regulator-name = "SDHI2 Vcc"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -100,19 +101,23 @@ compatible = "gpio-leds"; led1 { gpios = <&pfc 20 GPIO_ACTIVE_LOW>; + label = "LED1"; }; led2 { gpios = <&pfc 21 GPIO_ACTIVE_LOW>; + label = "LED2"; }; led3 { gpios = <&pfc 22 GPIO_ACTIVE_LOW>; + label = "LED3"; }; led4 { gpios = <&pfc 23 GPIO_ACTIVE_LOW>; + label = "LED4"; }; }; - gpio-keys { + keyboard { compatible = "gpio-keys"; back-key { @@ -173,6 +178,10 @@ }; }; +&cmt1 { + status = "ok"; +}; + &i2c0 { status = "okay"; as3711@40 { @@ -246,7 +255,7 @@ }; }; - ak4648: ak4648@0x12 { + ak4648: ak4648@12 { #sound-dai-cells = <0>; compatible = "asahi-kasei,ak4648"; reg = <0x12>; diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index 910b79079d5a..d8def5a529da 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -14,6 +14,7 @@ / { compatible = "renesas,sh73a0"; + interrupt-parent = <&gic>; cpus { #address-cells = <1>; @@ -23,11 +24,13 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + clock-frequency = <1196000000>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + clock-frequency = <1196000000>; }; }; @@ -45,6 +48,16 @@ <0 56 IRQ_TYPE_LEVEL_HIGH>; }; + cmt1: timer@e6138000 { + compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48"; + reg = <0xe6138000 0x200>; + interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>; + + renesas,channels-mask = <0x3f>; + + status = "disabled"; + }; + irqpin0: irqpin@e6900000 { compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; #interrupt-cells = <2>; @@ -54,7 +67,6 @@ <0xe6900020 1>, <0xe6900040 1>, <0xe6900060 1>; - interrupt-parent = <&gic>; interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH 0 2 IRQ_TYPE_LEVEL_HIGH 0 3 IRQ_TYPE_LEVEL_HIGH @@ -74,7 +86,6 @@ <0xe6900024 1>, <0xe6900044 1>, <0xe6900064 1>; - interrupt-parent = <&gic>; interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH 0 10 IRQ_TYPE_LEVEL_HIGH 0 11 IRQ_TYPE_LEVEL_HIGH @@ -95,7 +106,6 @@ <0xe6900028 1>, <0xe6900048 1>, <0xe6900068 1>; - interrupt-parent = <&gic>; interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH 0 18 IRQ_TYPE_LEVEL_HIGH 0 19 IRQ_TYPE_LEVEL_HIGH @@ -115,7 +125,6 @@ <0xe690002c 1>, <0xe690004c 1>, <0xe690006c 1>; - interrupt-parent = <&gic>; interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH 0 26 IRQ_TYPE_LEVEL_HIGH 0 27 IRQ_TYPE_LEVEL_HIGH @@ -129,9 +138,8 @@ i2c0: i2c@e6820000 { #address-cells = <1>; #size-cells = <0>; - compatible = "renesas,rmobile-iic"; + compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; reg = <0xe6820000 0x425>; - interrupt-parent = <&gic>; interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH 0 168 IRQ_TYPE_LEVEL_HIGH 0 169 IRQ_TYPE_LEVEL_HIGH @@ -142,9 +150,8 @@ i2c1: i2c@e6822000 { #address-cells = <1>; #size-cells = <0>; - compatible = "renesas,rmobile-iic"; + compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; reg = <0xe6822000 0x425>; - interrupt-parent = <&gic>; interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH 0 52 IRQ_TYPE_LEVEL_HIGH 0 53 IRQ_TYPE_LEVEL_HIGH @@ -155,9 +162,8 @@ i2c2: i2c@e6824000 { #address-cells = <1>; #size-cells = <0>; - compatible = "renesas,rmobile-iic"; + compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; reg = <0xe6824000 0x425>; - interrupt-parent = <&gic>; interrupts = <0 171 IRQ_TYPE_LEVEL_HIGH 0 172 IRQ_TYPE_LEVEL_HIGH 0 173 IRQ_TYPE_LEVEL_HIGH @@ -168,9 +174,8 @@ i2c3: i2c@e6826000 { #address-cells = <1>; #size-cells = <0>; - compatible = "renesas,rmobile-iic"; + compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; reg = <0xe6826000 0x425>; - interrupt-parent = <&gic>; interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH 0 184 IRQ_TYPE_LEVEL_HIGH 0 185 IRQ_TYPE_LEVEL_HIGH @@ -181,9 +186,8 @@ i2c4: i2c@e6828000 { #address-cells = <1>; #size-cells = <0>; - compatible = "renesas,rmobile-iic"; + compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; reg = <0xe6828000 0x425>; - interrupt-parent = <&gic>; interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH 0 188 IRQ_TYPE_LEVEL_HIGH 0 189 IRQ_TYPE_LEVEL_HIGH @@ -194,7 +198,6 @@ mmcif: mmc@e6bd0000 { compatible = "renesas,sh-mmcif"; reg = <0xe6bd0000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH 0 141 IRQ_TYPE_LEVEL_HIGH>; reg-io-width = <4>; @@ -204,7 +207,6 @@ sdhi0: sd@ee100000 { compatible = "renesas,sdhi-sh73a0"; reg = <0xee100000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH 0 84 IRQ_TYPE_LEVEL_HIGH 0 85 IRQ_TYPE_LEVEL_HIGH>; @@ -216,7 +218,6 @@ sdhi1: sd@ee120000 { compatible = "renesas,sdhi-sh73a0"; reg = <0xee120000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH 0 89 IRQ_TYPE_LEVEL_HIGH>; toshiba,mmc-wrprotect-disable; @@ -227,7 +228,6 @@ sdhi2: sd@ee140000 { compatible = "renesas,sdhi-sh73a0"; reg = <0xee140000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH 0 105 IRQ_TYPE_LEVEL_HIGH>; toshiba,mmc-wrprotect-disable; @@ -238,7 +238,6 @@ scifa0: serial@e6c40000 { compatible = "renesas,scifa-sh73a0", "renesas,scifa"; reg = <0xe6c40000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -246,7 +245,6 @@ scifa1: serial@e6c50000 { compatible = "renesas,scifa-sh73a0", "renesas,scifa"; reg = <0xe6c50000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -254,7 +252,6 @@ scifa2: serial@e6c60000 { compatible = "renesas,scifa-sh73a0", "renesas,scifa"; reg = <0xe6c60000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -262,7 +259,6 @@ scifa3: serial@e6c70000 { compatible = "renesas,scifa-sh73a0", "renesas,scifa"; reg = <0xe6c70000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -270,7 +266,6 @@ scifa4: serial@e6c80000 { compatible = "renesas,scifa-sh73a0", "renesas,scifa"; reg = <0xe6c80000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -278,7 +273,6 @@ scifa5: serial@e6cb0000 { compatible = "renesas,scifa-sh73a0", "renesas,scifa"; reg = <0xe6cb0000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -286,7 +280,6 @@ scifa6: serial@e6cc0000 { compatible = "renesas,scifa-sh73a0", "renesas,scifa"; reg = <0xe6cc0000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -294,7 +287,6 @@ scifa7: serial@e6cd0000 { compatible = "renesas,scifa-sh73a0", "renesas,scifa"; reg = <0xe6cd0000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -302,7 +294,6 @@ scifb8: serial@e6c30000 { compatible = "renesas,scifb-sh73a0", "renesas,scifb"; reg = <0xe6c30000 0x100>; - interrupt-parent = <&gic>; interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -328,7 +319,6 @@ #sound-dai-cells = <1>; compatible = "renesas,sh_fsi2"; reg = <0xec230000 0x400>; - interrupt-parent = <&gic>; interrupts = <0 146 0x4>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 4d77ad690ed5..252c3d1bda50 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -547,7 +547,7 @@ status = "disabled"; }; - gpio@ff708000 { + gpio0: gpio@ff708000 { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dw-apb-gpio"; @@ -555,7 +555,7 @@ clocks = <&per_base_clk>; status = "disabled"; - gpio0: gpio-controller@0 { + porta: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; @@ -567,7 +567,7 @@ }; }; - gpio@ff709000 { + gpio1: gpio@ff709000 { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dw-apb-gpio"; @@ -575,7 +575,7 @@ clocks = <&per_base_clk>; status = "disabled"; - gpio1: gpio-controller@0 { + portb: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; @@ -587,7 +587,7 @@ }; }; - gpio@ff70a000 { + gpio2: gpio@ff70a000 { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dw-apb-gpio"; @@ -595,7 +595,7 @@ clocks = <&per_base_clk>; status = "disabled"; - gpio2: gpio-controller@0 { + portc: gpio-controller@0 { compatible = "snps,dw-apb-gpio-port"; gpio-controller; #gpio-cells = <2>; @@ -607,6 +607,17 @@ }; }; + sdr: sdr@ffc25000 { + compatible = "syscon"; + reg = <0xffc25000 0x1000>; + }; + + sdramedac { + compatible = "altr,sdram-edac"; + altr,sdr-syscon = <&sdr>; + interrupts = <0 39 4>; + }; + L2: l2-cache@fffef000 { compatible = "arm,pl310-cache"; reg = <0xfffef000 0x1000>; @@ -628,6 +639,33 @@ clock-names = "biu", "ciu"; }; + ocram: sram@ffff0000 { + compatible = "mmio-sram"; + reg = <0xffff0000 0x10000>; + }; + + spi0: spi@fff00000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfff00000 0x1000>; + interrupts = <0 154 4>; + num-cs = <4>; + clocks = <&spi_m_clk>; + status = "disabled"; + }; + + spi1: spi@fff01000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfff01000 0x1000>; + interrupts = <0 156 4>; + num-cs = <4>; + clocks = <&spi_m_clk>; + status = "disabled"; + }; + /* Local timer */ timer@fffec600 { compatible = "arm,cortex-a9-twd-timer"; diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi new file mode 100644 index 000000000000..8a05c47fd57f --- /dev/null +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -0,0 +1,374 @@ +/* + * Copyright Altera Corporation (C) 2014. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "skeleton.dtsi" +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &gmac0; + ethernet1 = &gmac1; + ethernet2 = &gmac2; + serial0 = &uart0; + serial1 = &uart1; + timer0 = &timer0; + timer1 = &timer1; + timer2 = &timer2; + timer3 = &timer3; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L2>; + }; + cpu@1 { + compatible = "arm,cortex-a9"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L2>; + }; + }; + + intc: intc@ffffd000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xffffd000 0x1000>, + <0xffffc100 0x100>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + device_type = "soc"; + interrupt-parent = <&intc>; + ranges; + + amba { + compatible = "arm,amba-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + pdma: pdma@ffda1000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xffda1000 0x1000>; + interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>, + <0 84 IRQ_TYPE_LEVEL_HIGH>, + <0 85 IRQ_TYPE_LEVEL_HIGH>, + <0 86 IRQ_TYPE_LEVEL_HIGH>, + <0 87 IRQ_TYPE_LEVEL_HIGH>, + <0 88 IRQ_TYPE_LEVEL_HIGH>, + <0 89 IRQ_TYPE_LEVEL_HIGH>, + <0 90 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + }; + }; + + clkmgr@ffd04000 { + compatible = "altr,clk-mgr"; + reg = <0xffd04000 0x1000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + osc1: osc1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + }; + + main_pll: main_pll { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "altr,socfpga-pll-clock"; + clocks = <&osc1>; + }; + + periph_pll: periph_pll { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "altr,socfpga-pll-clock"; + clocks = <&osc1>; + }; + }; + }; + + gmac0: ethernet@ff800000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; + reg = <0xff800000 0x2000>; + interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + /* Filled in by bootloader */ + mac-address = [00 00 00 00 00 00]; + status = "disabled"; + }; + + gmac1: ethernet@ff802000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; + reg = <0xff802000 0x2000>; + interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + /* Filled in by bootloader */ + mac-address = [00 00 00 00 00 00]; + status = "disabled"; + }; + + gmac2: ethernet@ff804000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; + reg = <0xff804000 0x2000>; + interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + /* Filled in by bootloader */ + mac-address = [00 00 00 00 00 00]; + status = "disabled"; + }; + + gpio0: gpio@ffc02900 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xffc02900 0x100>; + status = "disabled"; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <29>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpio1: gpio@ffc02a00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xffc02a00 0x100>; + status = "disabled"; + + portb: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <29>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpio2: gpio@ffc02b00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xffc02b00 0x100>; + status = "disabled"; + + portc: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <27>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + i2c0: i2c@ffc02200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02200 0x100>; + interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + i2c1: i2c@ffc02300 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02300 0x100>; + interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + i2c2: i2c@ffc02400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02400 0x100>; + interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + i2c3: i2c@ffc02500 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02500 0x100>; + interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + i2c4: i2c@ffc02600 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02600 0x100>; + interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + L2: l2-cache@fffff000 { + compatible = "arm,pl310-cache"; + reg = <0xfffff000 0x1000>; + interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; + cache-unified; + cache-level = <2>; + }; + + mmc: dwmmc0@ff808000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "altr,socfpga-dw-mshc"; + reg = <0xff808000 0x1000>; + interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; + fifo-depth = <0x400>; + }; + + ocram: sram@ffe00000 { + compatible = "mmio-sram"; + reg = <0xffe00000 0x40000>; + }; + + rst: rstmgr@ffd05000 { + #reset-cells = <1>; + compatible = "altr,rst-mgr"; + reg = <0xffd05000 0x100>; + }; + + sysmgr: sysmgr@ffd06000 { + compatible = "altr,sys-mgr", "syscon"; + reg = <0xffd06000 0x300>; + }; + + /* Local timer */ + timer@ffffc600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0xffffc600 0x100>; + interrupts = <1 13 0xf04>; + }; + + timer0: timer0@ffc02700 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xffc02700 0x100>; + }; + + timer1: timer1@ffc02800 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xffc02800 0x100>; + }; + + timer2: timer2@ffd00000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xffd00000 0x100>; + }; + + timer3: timer3@ffd00100 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xffd01000 0x100>; + }; + + uart0: serial0@ffc02000 { + compatible = "snps,dw-apb-uart"; + reg = <0xffc02000 0x100>; + interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + }; + + uart1: serial1@ffc02100 { + compatible = "snps,dw-apb-uart"; + reg = <0xffc02100 0x100>; + interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + reg-io-width = <4>; + }; + + usbphy0: usbphy@0 { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + status = "okay"; + }; + + usb0: usb@ffb00000 { + compatible = "snps,dwc2"; + reg = <0xffb00000 0xffff>; + interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb1: usb@ffb40000 { + compatible = "snps,dwc2"; + reg = <0xffb40000 0xffff>; + interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + watchdog0: watchdog@ffd00200 { + compatible = "snps,dw-wdt"; + reg = <0xffd00200 0x100>; + interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + watchdog1: watchdog@ffd00300 { + compatible = "snps,dw-wdt"; + reg = <0xffd00300 0x100>; + interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dts b/arch/arm/boot/dts/socfpga_arria10_socdk.dts new file mode 100755 index 000000000000..3015ce8d3057 --- /dev/null +++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dts @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2014 Altera Corporation <www.altera.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +/dts-v1/; +#include "socfpga_arria10.dtsi" + +/ { + model = "Altera SOCFPGA Arria 10"; + compatible = "altr,socfpga-arria10", "altr,socfpga"; + + chosen { + bootargs = "console=ttyS0,115200 rootwait"; + }; + + memory { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + soc { + clkmgr@ffd04000 { + clocks { + osc1 { + clock-frequency = <25000000>; + }; + }; + }; + + serial0@ffc02000 { + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi index 12d1c2ccaf5b..1907cc600452 100644 --- a/arch/arm/boot/dts/socfpga_arria5.dtsi +++ b/arch/arm/boot/dts/socfpga_arria5.dtsi @@ -15,6 +15,8 @@ */ /dts-v1/; +/* First 4KB has trampoline code for secondary cores. */ +/memreserve/ 0x00000000 0x0001000; #include "socfpga.dtsi" / { @@ -27,15 +29,12 @@ }; }; - dwmmc0@ff704000 { + mmc0: dwmmc0@ff704000 { num-slots = <1>; - supports-highspeed; broken-cd; - - slot@0 { - reg = <0>; - bus-width = <4>; - }; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; }; sysmgr@ffd08000 { diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts index d532d171e391..ccaf41742fc3 100644 --- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts @@ -38,11 +38,11 @@ ethernet0 = &gmac1; }; - aliases { - /* this allow the ethaddr uboot environmnet variable contents - * to be added to the gmac1 device tree blob. - */ - ethernet0 = &gmac1; + regulator_3_3v: 3-3-v-regulator { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; }; }; @@ -75,6 +75,11 @@ }; }; +&mmc0 { + vmmc-supply = <®ulator_3_3v>; + vqmmc-supply = <®ulator_3_3v>; +}; + &usb1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi index bf511828729f..06db951e06f8 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi +++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi @@ -16,6 +16,8 @@ */ /dts-v1/; +/* First 4KB has trampoline code for secondary cores. */ +/memreserve/ 0x00000000 0x0001000; #include "socfpga.dtsi" / { @@ -28,15 +30,12 @@ }; }; - dwmmc0@ff704000 { + mmc0: dwmmc0@ff704000 { num-slots = <1>; - supports-highspeed; broken-cd; - - slot@0 { - reg = <0>; - bus-width = <4>; - }; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; }; ethernet@ff702000 { @@ -50,3 +49,7 @@ }; }; }; + +&watchdog0 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts index 45de1514af0a..258865da8f6a 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts @@ -37,6 +37,13 @@ */ ethernet0 = &gmac1; }; + + regulator_3_3v: 3-3-v-regulator { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; }; &gmac1 { @@ -53,6 +60,10 @@ rxc-skew-ps = <2000>; }; +&gpio1 { + status = "okay"; +}; + &i2c0 { status = "okay"; @@ -68,6 +79,12 @@ }; }; +&mmc0 { + cd-gpios = <&portb 18 0>; + vmmc-supply = <®ulator_3_3v>; + vqmmc-supply = <®ulator_3_3v>; +}; + &usb1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts index d26f155f5fd9..16ea6f5f2ab8 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts +++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts @@ -37,6 +37,13 @@ */ ethernet0 = &gmac1; }; + + regulator_3_3v: vcc3p3-regulator { + compatible = "regulator-fixed"; + regulator-name = "VCC3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; }; &gmac1 { @@ -53,6 +60,11 @@ rxc-skew-ps = <2000>; }; +&mmc0 { + vmmc-supply = <®ulator_3_3v>; + vqmmc-supply = <®ulator_3_3v>; +}; + &usb1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts index 09792b411110..f9345e02ca49 100644 --- a/arch/arm/boot/dts/socfpga_vt.dts +++ b/arch/arm/boot/dts/socfpga_vt.dts @@ -43,13 +43,10 @@ dwmmc0@ff704000 { num-slots = <1>; - supports-highspeed; broken-cd; - - slot@0 { - reg = <0>; - bus-width = <4>; - }; + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; }; ethernet@ff700000 { diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi index fa5f2bb5f106..9d342920695a 100644 --- a/arch/arm/boot/dts/spear1310.dtsi +++ b/arch/arm/boot/dts/spear1310.dtsi @@ -85,7 +85,8 @@ pcie0: pcie@b1000000 { compatible = "st,spear1340-pcie", "snps,dw-pcie"; - reg = <0xb1000000 0x4000>; + reg = <0xb1000000 0x4000>, <0x80000000 0x20000>; + reg-names = "dbi", "config"; interrupts = <0 68 0x4>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 0 68 0x4>; @@ -95,15 +96,15 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */ - 0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */ + ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ status = "disabled"; }; pcie1: pcie@b1800000 { compatible = "st,spear1340-pcie", "snps,dw-pcie"; - reg = <0xb1800000 0x4000>; + reg = <0xb1800000 0x4000>, <0x90000000 0x20000>; + reg-names = "dbi", "config"; interrupts = <0 69 0x4>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 0 69 0x4>; @@ -113,15 +114,15 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - ranges = <0x00000800 0 0x90000000 0x90000000 0 0x00020000 /* configuration space */ - 0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */ + ranges = <0x81000000 0 0 0x90020000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x90030000 0x90030000 0 0x0ffd0000>; /* non-prefetchable memory */ status = "disabled"; }; pcie2: pcie@b4000000 { compatible = "st,spear1340-pcie", "snps,dw-pcie"; - reg = <0xb4000000 0x4000>; + reg = <0xb4000000 0x4000>, <0xc0000000 0x20000>; + reg-names = "dbi", "config"; interrupts = <0 70 0x4>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 0 70 0x4>; @@ -131,8 +132,7 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - ranges = <0x00000800 0 0xc0000000 0xc0000000 0 0x00020000 /* configuration space */ - 0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */ + ranges = <0x81000000 0 0 0xc0020000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0xc0030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ status = "disabled"; }; diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi index e71df0f2cb52..13e1aa33daa2 100644 --- a/arch/arm/boot/dts/spear1340.dtsi +++ b/arch/arm/boot/dts/spear1340.dtsi @@ -50,7 +50,8 @@ pcie0: pcie@b1000000 { compatible = "st,spear1340-pcie", "snps,dw-pcie"; - reg = <0xb1000000 0x4000>; + reg = <0xb1000000 0x4000>, <0x80000000 0x20000>; + reg-names = "dbi", "config"; interrupts = <0 68 0x4>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0x0 0 &gic 0 68 0x4>; @@ -60,8 +61,7 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - ranges = <0x00000800 0 0x80000000 0x80000000 0 0x00020000 /* configuration space */ - 0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */ + ranges = <0x81000000 0 0 0x80020000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x80030000 0xc0030000 0 0x0ffd0000>; /* non-prefetchable memory */ status = "disabled"; }; diff --git a/arch/arm/boot/dts/ste-ccu8540-pinctrl.dtsi b/arch/arm/boot/dts/ste-ccu8540-pinctrl.dtsi index e0799966bc25..52dba2e39c71 100644 --- a/arch/arm/boot/dts/ste-ccu8540-pinctrl.dtsi +++ b/arch/arm/boot/dts/ste-ccu8540-pinctrl.dtsi @@ -16,31 +16,31 @@ uart0 { uart0_default_mux: uart0_mux { default_mux { - ste,function = "u0"; - ste,pins = "u0_a_1"; + function = "u0"; + groups = "u0_a_1"; }; }; uart0_default_mode: uart0_default { default_cfg1 { - ste,pins = "GPIO0", "GPIO2"; + pins = "GPIO0", "GPIO2"; ste,config = <&in_pu>; }; default_cfg2 { - ste,pins = "GPIO1", "GPIO3"; + pins = "GPIO1", "GPIO3"; ste,config = <&out_hi>; }; }; uart0_sleep_mode: uart0_sleep { sleep_cfg1 { - ste,pins = "GPIO0", "GPIO2"; + pins = "GPIO0", "GPIO2"; ste,config = <&slpm_in_pu>; }; sleep_cfg2 { - ste,pins = "GPIO1", "GPIO3"; + pins = "GPIO1", "GPIO3"; ste,config = <&slpm_out_hi>; }; }; @@ -49,29 +49,29 @@ uart2 { uart2_default_mode: uart2_default { default_mux { - ste,function = "u2"; - ste,pins = "u2txrx_a_1"; + function = "u2"; + groups = "u2txrx_a_1"; }; default_cfg1 { - ste,pins = "GPIO120"; + pins = "GPIO120"; ste,config = <&in_pu>; }; default_cfg2 { - ste,pins = "GPIO121"; + pins = "GPIO121"; ste,config = <&out_hi>; }; }; uart2_sleep_mode: uart2_sleep { sleep_cfg1 { - ste,pins = "GPIO120"; + pins = "GPIO120"; ste,config = <&slpm_in_pu>; }; sleep_cfg2 { - ste,pins = "GPIO121"; + pins = "GPIO121"; ste,config = <&slpm_out_hi>; }; }; @@ -80,21 +80,21 @@ i2c0 { i2c0_default_mux: i2c_mux { default_mux { - ste,function = "i2c0"; - ste,pins = "i2c0_a_1"; + function = "i2c0"; + groups = "i2c0_a_1"; }; }; i2c0_default_mode: i2c_default { default_cfg1 { - ste,pins = "GPIO147", "GPIO148"; + pins = "GPIO147", "GPIO148"; ste,config = <&in_pu>; }; }; i2c0_sleep_mode: i2c_sleep { sleep_cfg1 { - ste,pins = "GPIO147", "GPIO148"; + pins = "GPIO147", "GPIO148"; ste,config = <&slpm_in_pu>; }; }; @@ -103,21 +103,21 @@ i2c1 { i2c1_default_mux: i2c_mux { default_mux { - ste,function = "i2c1"; - ste,pins = "i2c1_b_2"; + function = "i2c1"; + groups = "i2c1_b_2"; }; }; i2c1_default_mode: i2c_default { default_cfg1 { - ste,pins = "GPIO16", "GPIO17"; + pins = "GPIO16", "GPIO17"; ste,config = <&in_pu>; }; }; i2c1_sleep_mode: i2c_sleep { sleep_cfg1 { - ste,pins = "GPIO16", "GPIO17"; + pins = "GPIO16", "GPIO17"; ste,config = <&slpm_in_pu>; }; }; @@ -126,21 +126,21 @@ i2c2 { i2c2_default_mux: i2c_mux { default_mux { - ste,function = "i2c2"; - ste,pins = "i2c2_b_2"; + function = "i2c2"; + groups = "i2c2_b_2"; }; }; i2c2_default_mode: i2c_default { default_cfg1 { - ste,pins = "GPIO10", "GPIO11"; + pins = "GPIO10", "GPIO11"; ste,config = <&in_pu>; }; }; i2c2_sleep_mode: i2c_sleep { sleep_cfg1 { - ste,pins = "GPIO11", "GPIO11"; + pins = "GPIO11", "GPIO11"; ste,config = <&slpm_in_pu>; }; }; @@ -149,21 +149,21 @@ i2c4 { i2c4_default_mux: i2c_mux { default_mux { - ste,function = "i2c4"; - ste,pins = "i2c4_b_2"; + function = "i2c4"; + groups = "i2c4_b_2"; }; }; i2c4_default_mode: i2c_default { default_cfg1 { - ste,pins = "GPIO122", "GPIO123"; + pins = "GPIO122", "GPIO123"; ste,config = <&in_pu>; }; }; i2c4_sleep_mode: i2c_sleep { sleep_cfg1 { - ste,pins = "GPIO122", "GPIO123"; + pins = "GPIO122", "GPIO123"; ste,config = <&slpm_in_pu>; }; }; @@ -172,21 +172,21 @@ i2c5 { i2c5_default_mux: i2c_mux { default_mux { - ste,function = "i2c5"; - ste,pins = "i2c5_c_2"; + function = "i2c5"; + groups = "i2c5_c_2"; }; }; i2c5_default_mode: i2c_default { default_cfg1 { - ste,pins = "GPIO118", "GPIO119"; + pins = "GPIO118", "GPIO119"; ste,config = <&in_pu>; }; }; i2c5_sleep_mode: i2c_sleep { sleep_cfg1 { - ste,pins = "GPIO118", "GPIO119"; + pins = "GPIO118", "GPIO119"; ste,config = <&slpm_in_pu>; }; }; diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index 9d2323020d34..bfd3f1c734b8 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -11,6 +11,7 @@ #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/mfd/dbx500-prcmu.h> +#include <dt-bindings/arm/ux500_pm_domains.h> #include "skeleton.dtsi" / { @@ -43,6 +44,10 @@ interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; }; + pm_domains: pm_domains0 { + compatible = "stericsson,ux500-pm-domains"; + #power-domain-cells = <1>; + }; clocks { compatible = "stericsson,u8500-clks"; @@ -636,6 +641,7 @@ clock-frequency = <400000>; clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>; clock-names = "i2cclk", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; }; i2c@80122000 { @@ -651,6 +657,7 @@ clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>; clock-names = "i2cclk", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; }; i2c@80128000 { @@ -666,6 +673,7 @@ clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>; clock-names = "i2cclk", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; }; i2c@80110000 { @@ -681,6 +689,7 @@ clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>; clock-names = "i2cclk", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; }; i2c@8012a000 { @@ -696,6 +705,7 @@ clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>; clock-names = "i2cclk", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; }; ssp@80002000 { @@ -709,6 +719,7 @@ dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */ <&dma 8 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; + power-domains = <&pm_domains DOMAIN_VAPE>; }; ssp@80003000 { @@ -722,6 +733,7 @@ dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */ <&dma 9 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; + power-domains = <&pm_domains DOMAIN_VAPE>; }; spi@8011a000 { @@ -736,6 +748,7 @@ dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */ <&dma 0 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; + power-domains = <&pm_domains DOMAIN_VAPE>; }; spi@80112000 { @@ -750,6 +763,7 @@ dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */ <&dma 35 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; + power-domains = <&pm_domains DOMAIN_VAPE>; }; spi@80111000 { @@ -764,6 +778,7 @@ dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */ <&dma 33 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; + power-domains = <&pm_domains DOMAIN_VAPE>; }; spi@80129000 { @@ -778,6 +793,7 @@ dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */ <&dma 40 0 0x0>; /* Logical - MemToDev */ dma-names = "rx", "tx"; + power-domains = <&pm_domains DOMAIN_VAPE>; }; uart@80120000 { @@ -836,6 +852,7 @@ clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>; clock-names = "sdi", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; status = "disabled"; }; @@ -851,6 +868,7 @@ clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>; clock-names = "sdi", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; status = "disabled"; }; @@ -866,6 +884,7 @@ clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>; clock-names = "sdi", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; status = "disabled"; }; @@ -881,6 +900,7 @@ clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>; clock-names = "sdi", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; status = "disabled"; }; @@ -896,6 +916,7 @@ clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>; clock-names = "sdi", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; status = "disabled"; }; @@ -911,6 +932,7 @@ clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>; clock-names = "sdi", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/ste-href-ab8500.dtsi b/arch/arm/boot/dts/ste-href-ab8500.dtsi index 30f8601da323..9b69bce9297d 100644 --- a/arch/arm/boot/dts/ste-href-ab8500.dtsi +++ b/arch/arm/boot/dts/ste-href-ab8500.dtsi @@ -47,11 +47,11 @@ gpio2 { gpio2_default_mode: gpio2_default { default_mux { - ste,function = "gpio"; - ste,pins = "gpio2_a_1"; + function = "gpio"; + groups = "gpio2_a_1"; }; default_cfg { - ste,pins = "GPIO2_T9"; + pins = "GPIO2_T9"; input-enable; bias-pull-down; }; @@ -60,11 +60,11 @@ gpio4 { gpio4_default_mode: gpio4_default { default_mux { - ste,function = "gpio"; - ste,pins = "gpio4_a_1"; + function = "gpio"; + groups = "gpio4_a_1"; }; default_cfg { - ste,pins = "GPIO4_W2"; + pins = "GPIO4_W2"; input-enable; bias-pull-down; }; @@ -73,11 +73,11 @@ gpio10 { gpio10_default_mode: gpio10_default { default_mux { - ste,function = "gpio"; - ste,pins = "gpio10_d_1"; + function = "gpio"; + groups = "gpio10_d_1"; }; default_cfg { - ste,pins = "GPIO10_U17"; + pins = "GPIO10_U17"; input-enable; bias-pull-down; }; @@ -86,11 +86,11 @@ gpio11 { gpio11_default_mode: gpio11_default { default_mux { - ste,function = "gpio"; - ste,pins = "gpio11_d_1"; + function = "gpio"; + groups = "gpio11_d_1"; }; default_cfg { - ste,pins = "GPIO11_AA18"; + pins = "GPIO11_AA18"; input-enable; bias-pull-down; }; @@ -99,11 +99,11 @@ gpio12 { gpio12_default_mode: gpio12_default { default_mux { - ste,function = "gpio"; - ste,pins = "gpio12_d_1"; + function = "gpio"; + groups = "gpio12_d_1"; }; default_cfg { - ste,pins = "GPIO12_U16"; + pins = "GPIO12_U16"; input-enable; bias-pull-down; }; @@ -112,11 +112,11 @@ gpio13 { gpio13_default_mode: gpio13_default { default_mux { - ste,function = "gpio"; - ste,pins = "gpio13_d_1"; + function = "gpio"; + groups = "gpio13_d_1"; }; default_cfg { - ste,pins = "GPIO13_W17"; + pins = "GPIO13_W17"; input-enable; bias-pull-down; }; @@ -125,11 +125,11 @@ gpio16 { gpio16_default_mode: gpio16_default { default_mux { - ste,function = "gpio"; - ste,pins = "gpio16_a_1"; + function = "gpio"; + groups = "gpio16_a_1"; }; default_cfg { - ste,pins = "GPIO16_F15"; + pins = "GPIO16_F15"; input-enable; bias-pull-down; }; @@ -138,11 +138,11 @@ gpio24 { gpio24_default_mode: gpio24_default { default_mux { - ste,function = "gpio"; - ste,pins = "gpio24_a_1"; + function = "gpio"; + groups = "gpio24_a_1"; }; default_cfg { - ste,pins = "GPIO24_T14"; + pins = "GPIO24_T14"; input-enable; bias-pull-down; }; @@ -151,11 +151,11 @@ gpio25 { gpio25_default_mode: gpio25_default { default_mux { - ste,function = "gpio"; - ste,pins = "gpio25_a_1"; + function = "gpio"; + groups = "gpio25_a_1"; }; default_cfg { - ste,pins = "GPIO25_R16"; + pins = "GPIO25_R16"; input-enable; bias-pull-down; }; @@ -164,11 +164,11 @@ gpio36 { gpio36_default_mode: gpio36_default { default_mux { - ste,function = "gpio"; - ste,pins = "gpio36_a_1"; + function = "gpio"; + groups = "gpio36_a_1"; }; default_cfg { - ste,pins = "GPIO36_A17"; + pins = "GPIO36_A17"; input-enable; bias-pull-down; }; @@ -177,11 +177,11 @@ gpio37 { gpio37_default_mode: gpio37_default { default_mux { - ste,function = "gpio"; - ste,pins = "gpio37_a_1"; + function = "gpio"; + groups = "gpio37_a_1"; }; default_cfg { - ste,pins = "GPIO37_E15"; + pins = "GPIO37_E15"; input-enable; bias-pull-down; }; @@ -190,11 +190,11 @@ gpio38 { gpio38_default_mode: gpio38_default { default_mux { - ste,function = "gpio"; - ste,pins = "gpio38_a_1"; + function = "gpio"; + groups = "gpio38_a_1"; }; default_cfg { - ste,pins = "GPIO38_C17"; + pins = "GPIO38_C17"; input-enable; bias-pull-down; }; @@ -203,11 +203,11 @@ gpio39 { gpio39_default_mode: gpio39_default { default_mux { - ste,function = "gpio"; - ste,pins = "gpio39_a_1"; + function = "gpio"; + groups = "gpio39_a_1"; }; default_cfg { - ste,pins = "GPIO39_E16"; + pins = "GPIO39_E16"; input-enable; bias-pull-down; }; @@ -216,11 +216,11 @@ gpio42 { gpio42_default_mode: gpio42_default { default_mux { - ste,function = "gpio"; - ste,pins = "gpio42_a_1"; + function = "gpio"; + groups = "gpio42_a_1"; }; default_cfg { - ste,pins = "GPIO42_U2"; + pins = "GPIO42_U2"; input-enable; bias-pull-down; }; @@ -232,11 +232,11 @@ gpio26 { gpio26_default_mode: gpio26_default { default_mux { - ste,function = "gpio"; - ste,pins = "gpio26_d_1"; + function = "gpio"; + groups = "gpio26_d_1"; }; default_cfg { - ste,pins = "GPIO26_M16"; + pins = "GPIO26_M16"; output-low; }; }; @@ -244,11 +244,11 @@ gpio35 { gpio35_default_mode: gpio35_default { default_mux { - ste,function = "gpio"; - ste,pins = "gpio35_d_1"; + function = "gpio"; + groups = "gpio35_d_1"; }; default_cfg { - ste,pins = "GPIO35_W15"; + pins = "GPIO35_W15"; output-low; }; }; @@ -260,11 +260,11 @@ ycbcr { ycbcr_default_mode: ycbcr_default { default_mux { - ste,function = "ycbcr"; - ste,pins = "ycbcr0123_d_1"; + function = "ycbcr"; + groups = "ycbcr0123_d_1"; }; default_cfg { - ste,pins = "GPIO6_Y18", + pins = "GPIO6_Y18", "GPIO7_AA20", "GPIO8_W18", "GPIO9_AA19"; @@ -277,11 +277,11 @@ pwm { pwm_default_mode: pwm_default { default_mux { - ste,function = "pwmout"; - ste,pins = "pwmout1_d_1", "pwmout2_d_1"; + function = "pwmout"; + groups = "pwmout1_d_1", "pwmout2_d_1"; }; default_cfg { - ste,pins = "GPIO14_F14", + pins = "GPIO14_F14", "GPIO15_B17"; input-enable; bias-pull-down; @@ -292,11 +292,11 @@ adi1 { adi1_default_mode: adi1_default { default_mux { - ste,function = "adi1"; - ste,pins = "adi1_d_1"; + function = "adi1"; + groups = "adi1_d_1"; }; default_cfg { - ste,pins = "GPIO17_P5", + pins = "GPIO17_P5", "GPIO18_R5", "GPIO19_U5", "GPIO20_T5"; @@ -309,11 +309,11 @@ usbuicc { usbuicc_default_mode: usbuicc_default { default_mux { - ste,function = "usbuicc"; - ste,pins = "usbuicc_d_1"; + function = "usbuicc"; + groups = "usbuicc_d_1"; }; default_cfg { - ste,pins = "GPIO21_H19", + pins = "GPIO21_H19", "GPIO22_G20", "GPIO23_G19"; input-enable; @@ -325,13 +325,13 @@ dmic { dmic_default_mode: dmic_default { default_mux { - ste,function = "dmic"; - ste,pins = "dmic12_d_1", + function = "dmic"; + groups = "dmic12_d_1", "dmic34_d_1", "dmic56_d_1"; }; default_cfg { - ste,pins = "GPIO27_J6", + pins = "GPIO27_J6", "GPIO28_K6", "GPIO29_G6", "GPIO30_H6", @@ -345,11 +345,11 @@ extcpena { extcpena_default_mode: extcpena_default { default_mux { - ste,function = "extcpena"; - ste,pins = "extcpena_d_1"; + function = "extcpena"; + groups = "extcpena_d_1"; }; default_cfg { - ste,pins = "GPIO34_R17"; + pins = "GPIO34_R17"; input-enable; bias-pull-down; }; @@ -359,11 +359,11 @@ modsclsda { modsclsda_default_mode: modsclsda_default { default_mux { - ste,function = "modsclsda"; - ste,pins = "modsclsda_d_1"; + function = "modsclsda"; + groups = "modsclsda_d_1"; }; default_cfg { - ste,pins = "GPIO40_T19", + pins = "GPIO40_T19", "GPIO41_U19"; input-enable; bias-pull-down; @@ -376,22 +376,22 @@ sysclkreq2 { sysclkreq2_default_mode: sysclkreq2_default { default_mux { - ste,function = "sysclkreq"; - ste,pins = "sysclkreq2_d_1"; + function = "sysclkreq"; + groups = "sysclkreq2_d_1"; }; default_cfg { - ste,pins = "GPIO1_T10"; + pins = "GPIO1_T10"; input-enable; bias-disable; }; }; sysclkreq2_sleep_mode: sysclkreq2_sleep { default_mux { - ste,function = "gpio"; - ste,pins = "gpio1_a_1"; + function = "gpio"; + groups = "gpio1_a_1"; }; default_cfg { - ste,pins = "GPIO1_T10"; + pins = "GPIO1_T10"; input-enable; bias-pull-down; }; @@ -400,22 +400,22 @@ sysclkreq4 { sysclkreq4_default_mode: sysclkreq4_default { default_mux { - ste,function = "sysclkreq"; - ste,pins = "sysclkreq4_d_1"; + function = "sysclkreq"; + groups = "sysclkreq4_d_1"; }; default_cfg { - ste,pins = "GPIO3_U9"; + pins = "GPIO3_U9"; input-enable; bias-disable; }; }; sysclkreq4_sleep_mode: sysclkreq4_sleep { default_mux { - ste,function = "gpio"; - ste,pins = "gpio3_a_1"; + function = "gpio"; + groups = "gpio3_a_1"; }; default_cfg { - ste,pins = "GPIO3_U9"; + pins = "GPIO3_U9"; input-enable; bias-pull-down; }; diff --git a/arch/arm/boot/dts/ste-href-ab8505.dtsi b/arch/arm/boot/dts/ste-href-ab8505.dtsi index 6006d62086a2..ccf37a9df050 100644 --- a/arch/arm/boot/dts/ste-href-ab8505.dtsi +++ b/arch/arm/boot/dts/ste-href-ab8505.dtsi @@ -35,11 +35,11 @@ gpio2 { gpio2_default_mode: gpio2_default { default_mux { - ste,function = "gpio"; - ste,pins = "gpio2_a_1"; + function = "gpio"; + groups = "gpio2_a_1"; }; default_cfg { - ste,pins = "GPIO2_R5"; + pins = "GPIO2_R5"; input-enable; bias-pull-down; }; @@ -48,11 +48,11 @@ gpio10 { gpio10_default_mode: gpio10_default { default_mux { - ste,function = "gpio"; - ste,pins = "gpio10_d_1"; + function = "gpio"; + groups = "gpio10_d_1"; }; default_cfg { - ste,pins = "GPIO10_B16"; + pins = "GPIO10_B16"; input-enable; bias-pull-down; }; @@ -61,11 +61,11 @@ gpio11 { gpio11_default_mode: gpio11_default { default_mux { - ste,function = "gpio"; - ste,pins = "gpio11_d_1"; + function = "gpio"; + groups = "gpio11_d_1"; }; default_cfg { - ste,pins = "GPIO11_B17"; + pins = "GPIO11_B17"; input-enable; bias-pull-down; }; @@ -74,11 +74,11 @@ gpio13 { gpio13_default_mode: gpio13_default { default_mux { - ste,function = "gpio"; - ste,pins = "gpio13_d_1"; + function = "gpio"; + groups = "gpio13_d_1"; }; default_cfg { - ste,pins = "GPIO13_D17"; + pins = "GPIO13_D17"; input-enable; bias-disable; }; @@ -87,11 +87,11 @@ gpio34 { gpio34_default_mode: gpio34_default { default_mux { - ste,function = "gpio"; - ste,pins = "gpio34_a_1"; + function = "gpio"; + groups = "gpio34_a_1"; }; default_cfg { - ste,pins = "GPIO34_H14"; + pins = "GPIO34_H14"; input-enable; bias-pull-down; }; @@ -100,11 +100,11 @@ gpio50 { gpio50_default_mode: gpio50_default { default_mux { - ste,function = "gpio"; - ste,pins = "gpio50_d_1"; + function = "gpio"; + groups = "gpio50_d_1"; }; default_cfg { - ste,pins = "GPIO50_L4"; + pins = "GPIO50_L4"; input-enable; bias-disable; }; @@ -114,11 +114,11 @@ pwm { pwm_default_mode: pwm_default { default_mux { - ste,function = "pwmout"; - ste,pins = "pwmout1_d_1"; + function = "pwmout"; + groups = "pwmout1_d_1"; }; default_cfg { - ste,pins = "GPIO14_C16"; + pins = "GPIO14_C16"; input-enable; bias-pull-down; }; @@ -128,11 +128,11 @@ adi2 { adi2_default_mode: adi2_default { default_mux { - ste,function = "adi2"; - ste,pins = "adi2_d_1"; + function = "adi2"; + groups = "adi2_d_1"; }; default_cfg { - ste,pins = "GPIO17_P2", + pins = "GPIO17_P2", "GPIO18_N3", "GPIO19_T1", "GPIO20_P3"; @@ -145,11 +145,11 @@ modsclsda { modsclsda_default_mode: modsclsda_default { default_mux { - ste,function = "modsclsda"; - ste,pins = "modsclsda_d_1"; + function = "modsclsda"; + groups = "modsclsda_d_1"; }; default_cfg { - ste,pins = "GPIO40_J15", + pins = "GPIO40_J15", "GPIO41_J14"; input-enable; bias-pull-down; @@ -159,11 +159,11 @@ resethw { resethw_default_mode: resethw_default { default_mux { - ste,function = "resethw"; - ste,pins = "resethw_d_1"; + function = "resethw"; + groups = "resethw_d_1"; }; default_cfg { - ste,pins = "GPIO52_D16"; + pins = "GPIO52_D16"; input-enable; bias-pull-down; }; @@ -172,11 +172,11 @@ service { service_default_mode: service_default { default_mux { - ste,function = "service"; - ste,pins = "service_d_1"; + function = "service"; + groups = "service_d_1"; }; default_cfg { - ste,pins = "GPIO53_D15"; + pins = "GPIO53_D15"; input-enable; bias-pull-down; }; @@ -188,22 +188,22 @@ sysclkreq2 { sysclkreq2_default_mode: sysclkreq2_default { default_mux { - ste,function = "sysclkreq"; - ste,pins = "sysclkreq2_d_1"; + function = "sysclkreq"; + groups = "sysclkreq2_d_1"; }; default_cfg { - ste,pins = "GPIO1_N4"; + pins = "GPIO1_N4"; input-enable; bias-disable; }; }; sysclkreq2_sleep_mode: sysclkreq2_sleep { default_mux { - ste,function = "gpio"; - ste,pins = "gpio1_a_1"; + function = "gpio"; + groups = "gpio1_a_1"; }; default_cfg { - ste,pins = "GPIO1_N4"; + pins = "GPIO1_N4"; input-enable; bias-pull-down; }; @@ -212,22 +212,22 @@ sysclkreq4 { sysclkreq4_default_mode: sysclkreq4_default { default_mux { - ste,function = "sysclkreq"; - ste,pins = "sysclkreq4_d_1"; + function = "sysclkreq"; + groups = "sysclkreq4_d_1"; }; default_cfg { - ste,pins = "GPIO3_P5"; + pins = "GPIO3_P5"; input-enable; bias-disable; }; }; sysclkreq4_sleep_mode: sysclkreq4_sleep { default_mux { - ste,function = "gpio"; - ste,pins = "gpio3_a_1"; + function = "gpio"; + groups = "gpio3_a_1"; }; default_cfg { - ste,pins = "GPIO3_P5"; + pins = "GPIO3_P5"; input-enable; bias-pull-down; }; diff --git a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi index addfcc7c2750..5c5cea232743 100644 --- a/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi +++ b/arch/arm/boot/dts/ste-href-family-pinctrl.dtsi @@ -18,33 +18,33 @@ uart0 { uart0_default_mode: uart0_default { default_mux { - ste,function = "u0"; - ste,pins = "u0_a_1"; + function = "u0"; + groups = "u0_a_1"; }; default_cfg1 { - ste,pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */ + pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */ ste,config = <&in_pu>; }; default_cfg2 { - ste,pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */ + pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */ ste,config = <&out_hi>; }; }; uart0_sleep_mode: uart0_sleep { sleep_cfg1 { - ste,pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */ + pins = "GPIO0_AJ5", "GPIO2_AH4"; /* CTS+RXD */ ste,config = <&slpm_in_wkup_pdis>; }; sleep_cfg2 { - ste,pins = "GPIO1_AJ3"; /* RTS */ + pins = "GPIO1_AJ3"; /* RTS */ ste,config = <&slpm_out_hi_wkup_pdis>; }; sleep_cfg3 { - ste,pins = "GPIO3_AH3"; /* TXD */ + pins = "GPIO3_AH3"; /* TXD */ ste,config = <&slpm_out_wkup_pdis>; }; }; @@ -53,28 +53,28 @@ uart1 { uart1_default_mode: uart1_default { default_mux { - ste,function = "u1"; - ste,pins = "u1rxtx_a_1"; + function = "u1"; + groups = "u1rxtx_a_1"; }; default_cfg1 { - ste,pins = "GPIO4_AH6"; /* RXD */ + pins = "GPIO4_AH6"; /* RXD */ ste,config = <&in_pu>; }; default_cfg2 { - ste,pins = "GPIO5_AG6"; /* TXD */ + pins = "GPIO5_AG6"; /* TXD */ ste,config = <&out_hi>; }; }; uart1_sleep_mode: uart1_sleep { sleep_cfg1 { - ste,pins = "GPIO4_AH6"; /* RXD */ + pins = "GPIO4_AH6"; /* RXD */ ste,config = <&slpm_in_wkup_pdis>; }; sleep_cfg2 { - ste,pins = "GPIO5_AG6"; /* TXD */ + pins = "GPIO5_AG6"; /* TXD */ ste,config = <&slpm_out_wkup_pdis>; }; }; @@ -83,28 +83,28 @@ uart2 { uart2_default_mode: uart2_default { default_mux { - ste,function = "u2"; - ste,pins = "u2rxtx_c_1"; + function = "u2"; + groups = "u2rxtx_c_1"; }; default_cfg1 { - ste,pins = "GPIO29_W2"; /* RXD */ + pins = "GPIO29_W2"; /* RXD */ ste,config = <&in_pu>; }; default_cfg2 { - ste,pins = "GPIO30_W3"; /* TXD */ + pins = "GPIO30_W3"; /* TXD */ ste,config = <&out_hi>; }; }; uart2_sleep_mode: uart2_sleep { sleep_cfg1 { - ste,pins = "GPIO29_W2"; /* RXD */ + pins = "GPIO29_W2"; /* RXD */ ste,config = <&in_wkup_pdis>; }; sleep_cfg2 { - ste,pins = "GPIO30_W3"; /* TXD */ + pins = "GPIO30_W3"; /* TXD */ ste,config = <&out_wkup_pdis>; }; }; @@ -114,18 +114,18 @@ i2c0 { i2c0_default_mode: i2c_default { default_mux { - ste,function = "i2c0"; - ste,pins = "i2c0_a_1"; + function = "i2c0"; + groups = "i2c0_a_1"; }; default_cfg1 { - ste,pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */ + pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */ ste,config = <&in_pu>; }; }; i2c0_sleep_mode: i2c_sleep { sleep_cfg1 { - ste,pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */ + pins = "GPIO147_C15", "GPIO148_B16"; /* SDA/SCL */ ste,config = <&slpm_in_wkup_pdis>; }; }; @@ -134,18 +134,18 @@ i2c1 { i2c1_default_mode: i2c_default { default_mux { - ste,function = "i2c1"; - ste,pins = "i2c1_b_2"; + function = "i2c1"; + groups = "i2c1_b_2"; }; default_cfg1 { - ste,pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */ + pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */ ste,config = <&in_pu>; }; }; i2c1_sleep_mode: i2c_sleep { sleep_cfg1 { - ste,pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */ + pins = "GPIO16_AD3", "GPIO17_AD4"; /* SDA/SCL */ ste,config = <&slpm_in_wkup_pdis>; }; }; @@ -154,18 +154,18 @@ i2c2 { i2c2_default_mode: i2c_default { default_mux { - ste,function = "i2c2"; - ste,pins = "i2c2_b_2"; + function = "i2c2"; + groups = "i2c2_b_2"; }; default_cfg1 { - ste,pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */ + pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */ ste,config = <&in_pu>; }; }; i2c2_sleep_mode: i2c_sleep { sleep_cfg1 { - ste,pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */ + pins = "GPIO10_AF5", "GPIO11_AG4"; /* SDA/SCL */ ste,config = <&slpm_in_wkup_pdis>; }; }; @@ -174,18 +174,18 @@ i2c3 { i2c3_default_mode: i2c_default { default_mux { - ste,function = "i2c3"; - ste,pins = "i2c3_c_2"; + function = "i2c3"; + groups = "i2c3_c_2"; }; default_cfg1 { - ste,pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */ + pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */ ste,config = <&in_pu>; }; }; i2c3_sleep_mode: i2c_sleep { sleep_cfg1 { - ste,pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */ + pins = "GPIO229_AG7", "GPIO230_AF7"; /* SDA/SCL */ ste,config = <&slpm_in_wkup_pdis>; }; }; @@ -198,18 +198,18 @@ i2c4 { i2c4_default_mode: i2c_default { default_mux { - ste,function = "i2c4"; - ste,pins = "i2c4_b_1"; + function = "i2c4"; + groups = "i2c4_b_1"; }; default_cfg1 { - ste,pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */ + pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */ ste,config = <&in_pu>; }; }; i2c4_sleep_mode: i2c_sleep { sleep_cfg1 { - ste,pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */ + pins = "GPIO4_AH6", "GPIO5_AG6"; /* SDA/SCL */ ste,config = <&slpm_in_wkup_pdis>; }; }; @@ -219,19 +219,19 @@ spi2 { spi2_default_mode: spi_default { default_mux { - ste,function = "spi2"; - ste,pins = "spi2_oc1_2"; + function = "spi2"; + groups = "spi2_oc1_2"; }; default_cfg1 { - ste,pins = "GPIO216_AG12"; /* FRM */ + pins = "GPIO216_AG12"; /* FRM */ ste,config = <&gpio_out_hi>; }; default_cfg2 { - ste,pins = "GPIO218_AH11"; /* RXD */ + pins = "GPIO218_AH11"; /* RXD */ ste,config = <&in_pd>; }; default_cfg3 { - ste,pins = + pins = "GPIO215_AH13", /* TXD */ "GPIO217_AH12"; /* CLK */ ste,config = <&out_lo>; @@ -245,32 +245,32 @@ * as we do not state any muxing. */ idle_cfg1 { - ste,pins = "GPIO218_AH11"; /* RXD */ + pins = "GPIO218_AH11"; /* RXD */ ste,config = <&slpm_in_pdis>; }; idle_cfg2 { - ste,pins = "GPIO215_AH13"; /* TXD */ + pins = "GPIO215_AH13"; /* TXD */ ste,config = <&slpm_out_lo_pdis>; }; idle_cfg3 { - ste,pins = "GPIO217_AH12"; /* CLK */ + pins = "GPIO217_AH12"; /* CLK */ ste,config = <&slpm_pdis>; }; }; spi2_sleep_mode: spi_sleep { sleep_cfg1 { - ste,pins = + pins = "GPIO216_AG12", /* FRM */ "GPIO218_AH11"; /* RXD */ ste,config = <&slpm_in_wkup_pdis>; }; sleep_cfg2 { - ste,pins = "GPIO215_AH13"; /* TXD */ + pins = "GPIO215_AH13"; /* TXD */ ste,config = <&slpm_out_lo_wkup_pdis>; }; sleep_cfg3 { - ste,pins = "GPIO217_AH12"; /* CLK */ + pins = "GPIO217_AH12"; /* CLK */ ste,config = <&slpm_wkup_pdis>; }; }; @@ -281,26 +281,26 @@ /* This is the external SD card slot, 4 bits wide */ sdi0_default_mode: sdi0_default { default_mux { - ste,function = "mc0"; - ste,pins = "mc0_a_1"; + function = "mc0"; + groups = "mc0_a_1"; }; default_cfg1 { - ste,pins = + pins = "GPIO18_AC2", /* CMDDIR */ "GPIO19_AC1", /* DAT0DIR */ "GPIO20_AB4"; /* DAT2DIR */ ste,config = <&out_hi>; }; default_cfg2 { - ste,pins = "GPIO22_AA3"; /* FBCLK */ + pins = "GPIO22_AA3"; /* FBCLK */ ste,config = <&in_nopull>; }; default_cfg3 { - ste,pins = "GPIO23_AA4"; /* CLK */ + pins = "GPIO23_AA4"; /* CLK */ ste,config = <&out_lo>; }; default_cfg4 { - ste,pins = + pins = "GPIO24_AB2", /* CMD */ "GPIO25_Y4", /* DAT0 */ "GPIO26_Y2", /* DAT1 */ @@ -312,14 +312,14 @@ sdi0_sleep_mode: sdi0_sleep { sleep_cfg1 { - ste,pins = + pins = "GPIO18_AC2", /* CMDDIR */ "GPIO19_AC1", /* DAT0DIR */ "GPIO20_AB4"; /* DAT2DIR */ ste,config = <&slpm_out_hi_wkup_pdis>; }; sleep_cfg2 { - ste,pins = + pins = "GPIO22_AA3", /* FBCLK */ "GPIO24_AB2", /* CMD */ "GPIO25_Y4", /* DAT0 */ @@ -329,7 +329,7 @@ ste,config = <&slpm_in_wkup_pdis>; }; sleep_cfg3 { - ste,pins = "GPIO23_AA4"; /* CLK */ + pins = "GPIO23_AA4"; /* CLK */ ste,config = <&slpm_out_lo_wkup_pdis>; }; }; @@ -339,19 +339,19 @@ /* This is the WLAN SDIO 4 bits wide */ sdi1_default_mode: sdi1_default { default_mux { - ste,function = "mc1"; - ste,pins = "mc1_a_1"; + function = "mc1"; + groups = "mc1_a_1"; }; default_cfg1 { - ste,pins = "GPIO208_AH16"; /* CLK */ + pins = "GPIO208_AH16"; /* CLK */ ste,config = <&out_lo>; }; default_cfg2 { - ste,pins = "GPIO209_AG15"; /* FBCLK */ + pins = "GPIO209_AG15"; /* FBCLK */ ste,config = <&in_nopull>; }; default_cfg3 { - ste,pins = + pins = "GPIO210_AJ15", /* CMD */ "GPIO211_AG14", /* DAT0 */ "GPIO212_AF13", /* DAT1 */ @@ -363,11 +363,11 @@ sdi1_sleep_mode: sdi1_sleep { sleep_cfg1 { - ste,pins = "GPIO208_AH16"; /* CLK */ + pins = "GPIO208_AH16"; /* CLK */ ste,config = <&slpm_out_lo_wkup_pdis>; }; sleep_cfg2 { - ste,pins = + pins = "GPIO209_AG15", /* FBCLK */ "GPIO210_AJ15", /* CMD */ "GPIO211_AG14", /* DAT0 */ @@ -383,19 +383,19 @@ /* This is the eMMC 8 bits wide, usually PoP eMMC */ sdi2_default_mode: sdi2_default { default_mux { - ste,function = "mc2"; - ste,pins = "mc2_a_1"; + function = "mc2"; + groups = "mc2_a_1"; }; default_cfg1 { - ste,pins = "GPIO128_A5"; /* CLK */ + pins = "GPIO128_A5"; /* CLK */ ste,config = <&out_lo>; }; default_cfg2 { - ste,pins = "GPIO130_C8"; /* FBCLK */ + pins = "GPIO130_C8"; /* FBCLK */ ste,config = <&in_nopull>; }; default_cfg3 { - ste,pins = + pins = "GPIO129_B4", /* CMD */ "GPIO131_A12", /* DAT0 */ "GPIO132_C10", /* DAT1 */ @@ -411,17 +411,17 @@ sdi2_sleep_mode: sdi2_sleep { sleep_cfg1 { - ste,pins = "GPIO128_A5"; /* CLK */ + pins = "GPIO128_A5"; /* CLK */ ste,config = <&out_lo_wkup_pdis>; }; sleep_cfg2 { - ste,pins = + pins = "GPIO130_C8", /* FBCLK */ "GPIO129_B4"; /* CMD */ ste,config = <&in_wkup_pdis_en>; }; sleep_cfg3 { - ste,pins = + pins = "GPIO131_A12", /* DAT0 */ "GPIO132_C10", /* DAT1 */ "GPIO133_B10", /* DAT2 */ @@ -439,19 +439,19 @@ /* This is the eMMC 8 bits wide, usually PCB-mounted eMMC */ sdi4_default_mode: sdi4_default { default_mux { - ste,function = "mc4"; - ste,pins = "mc4_a_1"; + function = "mc4"; + groups = "mc4_a_1"; }; default_cfg1 { - ste,pins = "GPIO203_AE23"; /* CLK */ + pins = "GPIO203_AE23"; /* CLK */ ste,config = <&out_lo>; }; default_cfg2 { - ste,pins = "GPIO202_AF25"; /* FBCLK */ + pins = "GPIO202_AF25"; /* FBCLK */ ste,config = <&in_nopull>; }; default_cfg3 { - ste,pins = + pins = "GPIO201_AF24", /* CMD */ "GPIO200_AH26", /* DAT0 */ "GPIO199_AH23", /* DAT1 */ @@ -467,11 +467,11 @@ sdi4_sleep_mode: sdi4_sleep { sleep_cfg1 { - ste,pins = "GPIO203_AE23"; /* CLK */ + pins = "GPIO203_AE23"; /* CLK */ ste,config = <&out_lo_wkup_pdis>; }; sleep_cfg2 { - ste,pins = + pins = "GPIO202_AF25", /* FBCLK */ "GPIO201_AF24", /* CMD */ "GPIO200_AH26", /* DAT0 */ @@ -494,11 +494,11 @@ msp0 { msp0_default_mode: msp0_default { default_msp0_mux { - ste,function = "msp0"; - ste,pins = "msp0txrx_a_1", "msp0tfstck_a_1"; + function = "msp0"; + groups = "msp0txrx_a_1", "msp0tfstck_a_1"; }; default_msp0_cfg { - ste,pins = + pins = "GPIO12_AC4", /* TXD */ "GPIO15_AC3", /* RXD */ "GPIO13_AF3", /* TFS */ @@ -511,15 +511,15 @@ msp1 { msp1_default_mode: msp1_default { default_mux { - ste,function = "msp1"; - ste,pins = "msp1txrx_a_1", "msp1_a_1"; + function = "msp1"; + groups = "msp1txrx_a_1", "msp1_a_1"; }; default_cfg1 { - ste,pins = "GPIO33_AF2"; + pins = "GPIO33_AF2"; ste,config = <&out_lo>; }; default_cfg2 { - ste,pins = + pins = "GPIO34_AE1", "GPIO35_AE2", "GPIO36_AG2"; @@ -533,18 +533,18 @@ msp2_default_mode: msp2_default { /* MSP2 usually used for HDMI audio */ default_mux { - ste,function = "msp2"; - ste,pins = "msp2_a_1"; + function = "msp2"; + groups = "msp2_a_1"; }; default_cfg1 { - ste,pins = + pins = "GPIO193_AH27", /* TXD */ "GPIO194_AF27", /* TCK */ "GPIO195_AG28"; /* TFS */ ste,config = <&in_pd>; }; default_cfg2 { - ste,pins = "GPIO196_AG26"; /* RXD */ + pins = "GPIO196_AG26"; /* RXD */ ste,config = <&out_lo>; }; }; @@ -554,11 +554,11 @@ musb { musb_default_mode: musb_default { default_mux { - ste,function = "usb"; - ste,pins = "usb_a_1"; + function = "usb"; + groups = "usb_a_1"; }; default_cfg1 { - ste,pins = + pins = "GPIO256_AF28", /* NXT */ "GPIO258_AD29", /* XCLK */ "GPIO259_AC29", /* DIR */ @@ -573,25 +573,25 @@ ste,config = <&in_nopull>; }; default_cfg2 { - ste,pins = "GPIO257_AE29"; /* STP */ + pins = "GPIO257_AE29"; /* STP */ ste,config = <&out_hi>; }; }; musb_sleep_mode: musb_sleep { sleep_cfg1 { - ste,pins = + pins = "GPIO256_AF28", /* NXT */ "GPIO258_AD29", /* XCLK */ "GPIO259_AC29"; /* DIR */ ste,config = <&slpm_wkup_pdis_en>; }; sleep_cfg2 { - ste,pins = "GPIO257_AE29"; /* STP */ + pins = "GPIO257_AE29"; /* STP */ ste,config = <&slpm_out_hi_wkup_pdis>; }; sleep_cfg3 { - ste,pins = + pins = "GPIO260_AD28", /* DAT7 */ "GPIO261_AD26", /* DAT6 */ "GPIO262_AE26", /* DAT5 */ @@ -609,8 +609,8 @@ lcd_default_mode: lcd_default { default_mux { /* Mux in VSI0 and all the data lines */ - ste,function = "lcd"; - ste,pins = + function = "lcd"; + groups = "lcdvsi0_a_1", /* VSI0 for LCD */ "lcd_d0_d7_a_1", /* Data lines */ "lcd_d8_d11_a_1", /* TV-out */ @@ -618,7 +618,7 @@ "lcdvsi1_a_1"; /* VSI1 for HDMI */ }; default_cfg1 { - ste,pins = + pins = "GPIO68_E1", /* VSI0 */ "GPIO69_E2"; /* VSI1 */ ste,config = <&in_pu>; @@ -626,7 +626,7 @@ }; lcd_sleep_mode: lcd_sleep { sleep_cfg1 { - ste,pins = "GPIO69_E2"; /* VSI1 */ + pins = "GPIO69_E2"; /* VSI1 */ ste,config = <&slpm_in_wkup_pdis>; }; }; @@ -636,11 +636,11 @@ /* SKE keys on position 2 in an 8x8 matrix */ ske_kpa2_default_mode: ske_kpa2_default { default_mux { - ste,function = "kp"; - ste,pins = "kp_a_2"; + function = "kp"; + groups = "kp_a_2"; }; default_cfg1 { - ste,pins = + pins = "GPIO153_B17", /* I7 */ "GPIO154_C16", /* I6 */ "GPIO155_C19", /* I5 */ @@ -652,7 +652,7 @@ ste,config = <&in_pd>; }; default_cfg2 { - ste,pins = + pins = "GPIO157_A18", /* O7 */ "GPIO158_C18", /* O6 */ "GPIO159_B19", /* O5 */ @@ -666,7 +666,7 @@ }; ske_kpa2_sleep_mode: ske_kpa2_sleep { sleep_cfg1 { - ste,pins = + pins = "GPIO153_B17", /* I7 */ "GPIO154_C16", /* I6 */ "GPIO155_C19", /* I5 */ @@ -678,7 +678,7 @@ ste,config = <&slpm_in_pu_wkup_pdis_en>; }; sleep_cfg2 { - ste,pins = + pins = "GPIO157_A18", /* O7 */ "GPIO158_C18", /* O6 */ "GPIO159_B19", /* O5 */ @@ -696,11 +696,11 @@ */ ske_kpaoc1_default_mode: ske_kpaoc1_default { default_mux { - ste,function = "kp"; - ste,pins = "kp_a_1", "kp_oc1_1"; + function = "kp"; + groups = "kp_a_1", "kp_oc1_1"; }; default_cfg1 { - ste,pins = + pins = "GPIO91_B6", /* KP_O0 */ "GPIO90_A3", /* KP_O1 */ "GPIO87_B3", /* KP_O2 */ @@ -710,7 +710,7 @@ ste,config = <&out_lo>; }; default_cfg2 { - ste,pins = + pins = "GPIO93_B7", /* KP_I0 */ "GPIO92_D6", /* KP_I1 */ "GPIO89_E6", /* KP_I2 */ @@ -729,13 +729,13 @@ * These are plain GPIO pins used by WLAN */ default_cfg1 { - ste,pins = + pins = "GPIO226_AF8", /* WLAN_PMU_EN */ "GPIO85_D5"; /* WLAN_ENA */ ste,config = <&gpio_out_lo>; }; default_cfg2 { - ste,pins = "GPIO4_AH6"; /* WLAN_IRQ on UART1 */ + pins = "GPIO4_AH6"; /* WLAN_IRQ on UART1 */ ste,config = <&gpio_in_pu>; }; }; diff --git a/arch/arm/boot/dts/ste-href-stuib.dtsi b/arch/arm/boot/dts/ste-href-stuib.dtsi index 84d7c5d883f2..7d4f8184c522 100644 --- a/arch/arm/boot/dts/ste-href-stuib.dtsi +++ b/arch/arm/boot/dts/ste-href-stuib.dtsi @@ -103,7 +103,7 @@ prox { prox_stuib_mode: prox_stuib { stuib_cfg { - ste,pins = "GPIO217_AH12"; + pins = "GPIO217_AH12"; ste,config = <&gpio_in_pu>; }; }; @@ -111,7 +111,7 @@ hall { hall_stuib_mode: stuib_tvk { stuib_cfg { - ste,pins = "GPIO145_C13"; + pins = "GPIO145_C13"; ste,config = <&gpio_in_pu>; }; }; diff --git a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi index 18b65d1b14f2..062c6aae3afa 100644 --- a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi +++ b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi @@ -130,7 +130,7 @@ tc35893 { tc35893_tvk_mode: tc35893_tvk { tvk_cfg { - ste,pins = "GPIO218_AH11"; + pins = "GPIO218_AH11"; ste,config = <&gpio_in_pu>; }; }; @@ -138,7 +138,7 @@ prox { prox_tvk_mode: prox_tvk { tvk_cfg { - ste,pins = "GPIO217_AH12"; + pins = "GPIO217_AH12"; ste,config = <&gpio_in_pu>; }; }; @@ -146,7 +146,7 @@ hall { hall_tvk_mode: hall_tvk { tvk_cfg { - ste,pins = "GPIO145_C13"; + pins = "GPIO145_C13"; ste,config = <&gpio_in_pu>; }; }; @@ -155,7 +155,7 @@ accel_tvk_mode: accel_tvk { /* Accelerometer interrupt lines 1 & 2 */ tvk_cfg { - ste,pins = "GPIO82_C1", "GPIO83_D3"; + pins = "GPIO82_C1", "GPIO83_D3"; ste,config = <&gpio_in_pu>; }; }; @@ -164,11 +164,11 @@ magneto_tvk_mode: magneto_tvk { /* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */ tvk_cfg1 { - ste,pins = "GPIO31_V3"; + pins = "GPIO31_V3"; ste,config = <&gpio_in_pu>; }; tvk_cfg2 { - ste,pins = "GPIO32_V2"; + pins = "GPIO32_V2"; ste,config = <&gpio_in_pd>; }; }; diff --git a/arch/arm/boot/dts/ste-hrefprev60.dtsi b/arch/arm/boot/dts/ste-hrefprev60.dtsi index abc762e24fcb..7f3975b58d16 100644 --- a/arch/arm/boot/dts/ste-hrefprev60.dtsi +++ b/arch/arm/boot/dts/ste-hrefprev60.dtsi @@ -79,11 +79,11 @@ ssp0 { ssp0_hrefprev60_mode: ssp0_hrefprev60_default { hrefprev60_mux { - ste,function = "ssp0"; - ste,pins = "ssp0_a_1"; + function = "ssp0"; + groups = "ssp0_a_1"; }; hrefprev60_cfg1 { - ste,pins = "GPIO145_C13"; /* RXD */ + pins = "GPIO145_C13"; /* RXD */ ste,config = <&in_pd>; }; @@ -93,11 +93,11 @@ /* This additional pin needed on early MOP500 and HREFs previous to v60 */ sdi0_default_mode: sdi0_default { hrefprev60_mux { - ste,function = "mc0"; - ste,pins = "mc0dat31dir_a_1"; + function = "mc0"; + groups = "mc0dat31dir_a_1"; }; hrefprev60_cfg1 { - ste,pins = "GPIO21_AB3"; /* DAT31DIR */ + pins = "GPIO21_AB3"; /* DAT31DIR */ ste,config = <&out_hi>; }; @@ -106,7 +106,7 @@ tc35892 { tc35892_hrefprev60_mode: tc35892_hrefprev60 { hrefprev60_cfg { - ste,pins = "GPIO217_AH12"; + pins = "GPIO217_AH12"; ste,config = <&gpio_in_pu>; }; }; @@ -114,11 +114,11 @@ ipgpio { ipgpio_hrefprev60_mode: ipgpio_hrefprev60 { hrefprev60_mux { - ste,function = "ipgpio"; - ste,pins = "ipgpio0_c_1", "ipgpio1_c_1"; + function = "ipgpio"; + groups = "ipgpio0_c_1", "ipgpio1_c_1"; }; hrefprev60_cfg1 { - ste,pins = "GPIO6_AF6", "GPIO7_AG5"; + pins = "GPIO6_AF6", "GPIO7_AG5"; ste,config = <&in_pu>; }; }; diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/ste-hrefv60plus.dtsi index bcc1f0c37f49..a4bc9e77d640 100644 --- a/arch/arm/boot/dts/ste-hrefv60plus.dtsi +++ b/arch/arm/boot/dts/ste-hrefv60plus.dtsi @@ -49,7 +49,7 @@ /* SD card detect GPIO pin, extend default state */ sdi0_default_mode: sdi0_default { default_hrefv60_cfg1 { - ste,pins = "GPIO95_E8"; + pins = "GPIO95_E8"; ste,config = <&gpio_in_pu>; }; }; @@ -64,19 +64,19 @@ */ ipgpio_hrefv60_mode: ipgpio_hrefv60 { hrefv60_mux { - ste,function = "ipgpio"; - ste,pins = "ipgpio0_c_1", "ipgpio1_c_1", "ipgpio4_c_1"; + function = "ipgpio"; + groups = "ipgpio0_c_1", "ipgpio1_c_1", "ipgpio4_c_1"; }; hrefv60_cfg1 { - ste,pins = "GPIO6_AF6", "GPIO7_AG5"; + pins = "GPIO6_AF6", "GPIO7_AG5"; ste,config = <&in_pu>; }; hrefv60_cfg2 { - ste,pins = "GPIO21_AB3"; + pins = "GPIO21_AB3"; ste,config = <&gpio_out_lo>; }; hrefv60_cfg3 { - ste,pins = "GPIO64_F3"; + pins = "GPIO64_F3"; ste,config = <&out_lo>; }; }; @@ -89,7 +89,7 @@ */ etm_hrefv60_mode: etm_hrefv60 { hrefv60_cfg1 { - ste,pins = + pins = "GPIO70_G5", "GPIO71_G4", "GPIO72_H4", @@ -103,11 +103,11 @@ nahj_hrefv60_mode: nahj_hrefv60 { /* NAHJ CTRL on GPIO76 to low, CTRL_INV on GPIO216 to high */ hrefv60_cfg1 { - ste,pins = "GPIO76_J2"; + pins = "GPIO76_J2"; ste,config = <&gpio_out_lo>; }; hrefv60_cfg2 { - ste,pins = "GPIO216_AG12"; + pins = "GPIO216_AG12"; ste,config = <&gpio_out_hi>; }; }; @@ -116,13 +116,13 @@ nfc_hrefv60_mode: nfc_hrefv60 { /* NFC ENA and RESET to low, pulldown IRQ line */ hrefv60_cfg1 { - ste,pins = + pins = "GPIO77_H1", /* NFC_ENA */ "GPIO142_C11"; /* NFC_RESET */ ste,config = <&gpio_out_lo>; }; hrefv60_cfg2 { - ste,pins = "GPIO144_B13"; /* NFC_IRQ */ + pins = "GPIO144_B13"; /* NFC_IRQ */ ste,config = <&gpio_in_pd>; }; }; @@ -130,11 +130,11 @@ force { force_hrefv60_mode: force_hrefv60 { hrefv60_cfg1 { - ste,pins = "GPIO91_B6"; /* FORCE_SENSING_INT */ + pins = "GPIO91_B6"; /* FORCE_SENSING_INT */ ste,config = <&gpio_in_pu>; }; hrefv60_cfg2 { - ste,pins = + pins = "GPIO92_D6", /* FORCE_SENSING_RST */ "GPIO97_D9"; /* FORCE_SENSING_WU */ ste,config = <&gpio_out_lo>; @@ -144,7 +144,7 @@ dipro { dipro_hrefv60_mode: dipro_hrefv60 { hrefv60_cfg1 { - ste,pins = "GPIO139_C9"; /* DIPRO_INT */ + pins = "GPIO139_C9"; /* DIPRO_INT */ ste,config = <&gpio_in_pu>; }; }; @@ -153,7 +153,7 @@ vaudio_hf_hrefv60_mode: vaudio_hf_hrefv60 { /* Audio Amplifier HF enable GPIO */ hrefv60_cfg1 { - ste,pins = "GPIO149_B14"; /* VAUDIO_HF_EN, enable MAX8968 */ + pins = "GPIO149_B14"; /* VAUDIO_HF_EN, enable MAX8968 */ ste,config = <&gpio_out_hi>; }; }; @@ -165,7 +165,7 @@ * pull low to reset state */ hrefv60_cfg1 { - ste,pins = "GPIO171_D23"; /* GBF_ENA_RESET */ + pins = "GPIO171_D23"; /* GBF_ENA_RESET */ ste,config = <&gpio_out_lo>; }; }; @@ -174,7 +174,7 @@ hdtv_hrefv60_mode: hdtv_hrefv60 { /* MSP : HDTV INTERFACE GPIO line */ hrefv60_cfg1 { - ste,pins = "GPIO192_AJ27"; + pins = "GPIO192_AJ27"; ste,config = <&gpio_in_pd>; }; }; @@ -187,11 +187,11 @@ * reset signals low. */ hrefv60_cfg1 { - ste,pins = "GPIO143_D12", "GPIO146_D13"; + pins = "GPIO143_D12", "GPIO146_D13"; ste,config = <&gpio_out_lo>; }; hrefv60_cfg2 { - ste,pins = "GPIO67_G2"; + pins = "GPIO67_G2"; ste,config = <&gpio_in_pu>; }; }; @@ -204,11 +204,11 @@ * Drive DISP1 reset high (not reset), driver DISP2 reset low (reset) */ hrefv60_cfg1 { - ste,pins ="GPIO65_F1"; + pins ="GPIO65_F1"; ste,config = <&gpio_out_hi>; }; hrefv60_cfg2 { - ste,pins ="GPIO66_G3"; + pins ="GPIO66_G3"; ste,config = <&gpio_out_lo>; }; }; diff --git a/arch/arm/boot/dts/ste-nomadik-nhk15.dts b/arch/arm/boot/dts/ste-nomadik-nhk15.dts new file mode 100644 index 000000000000..a8c00ee7522a --- /dev/null +++ b/arch/arm/boot/dts/ste-nomadik-nhk15.dts @@ -0,0 +1,151 @@ +/* + * Device Tree for the ST-Ericsson Nomadik S8815 board + * Produced by Calao Systems + */ + +/dts-v1/; +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> +#include "ste-nomadik-stn8815.dtsi" + +/ { + model = "Nomadik STN8815NHK"; + compatible = "st,nomadik-nhk-15"; + + chosen { + bootargs = "root=/dev/ram0 console=ttyAMA1,115200n8 earlyprintk"; + }; + + aliases { + stmpe-i2c0 = &stmpe0; + stmpe-i2c1 = &stmpe1; + }; + + pinctrl { + stmpe2401_1 { + stmpe2401_1_nhk_mode: stmpe2401_1_nhk { + nhk_cfg1 { + ste,pins = "GPIO76_B20"; // IRQ line + ste,input = <0>; + }; + nhk_cfg2 { + ste,pins = "GPIO77_B8"; // reset line + ste,output = <1>; + }; + }; + }; + stmpe2401_2 { + stmpe2401_2_nhk_mode: stmpe2401_2_nhk { + nhk_cfg1 { + ste,pins = "GPIO78_A8"; // IRQ line + ste,input = <0>; + }; + nhk_cfg2 { + ste,pins = "GPIO79_C9"; // reset line + ste,output = <1>; + }; + }; + }; + }; + + src@101e0000 { + /* These chrystal outputs are not used on this board */ + disable-sxtalo; + disable-mxtalo; + }; + + /* This is where the interrupt is routed on the NHK-15 debug board */ + external-bus@34000000 { + compatible = "simple-bus"; + reg = <0x34000000 0x1000000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x34000000 0x1000000>; + ethernet@300 { + compatible = "smsc,lan91c111"; + reg = <0x300 0x0fd00>; + reg-io-width = <2>; + reset-gpios = <&stmpe_gpio44 10 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&stmpe_gpio44>; + interrupts = <11 IRQ_TYPE_EDGE_RISING>; + }; + }; + + i2c0 { + stmpe0: stmpe2401@43 { + compatible = "st,stmpe2401"; + reg = <0x43>; + reset-gpios = <&gpio2 13 GPIO_ACTIVE_LOW>; // GPIO77 + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; // GPIO76 + interrupt-parent = <&gpio2>; + interrupt-controller; + wakeup-source; + pinctrl-names = "default"; + pinctrl-0 = <&stmpe2401_1_nhk_mode>; + stmpe_gpio43: stmpe_gpio { + compatible = "st,stmpe-gpio"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + /* Some pins in alternate functions */ + st,norequest-mask = <0xf0f002>; + }; + stmpe_keypad { + compatible = "st,stmpe-keypad"; + debounce-interval = <64>; + st,scan-count = <8>; + st,no-autorepeat; + keypad,num-rows = <8>; + keypad,num-columns = <8>; + linux,keymap = <0x00020072 // Vol down + 0x00030073 // Vol up + 0x0100009e // Back + 0x010100e3 // TV out + 0x01020098 // Lock + 0x0103013b // Start + 0x020000a3 // Next + 0x020100a4 // Play + 0x020200a5 // Prev + 0x02030160 // OK + 0x03000069 // Left + 0x0301006a // Right + 0x03020067 // Up + 0x0303006c>; // Down + }; + }; + stmpe1: stmpe2401@44 { + compatible = "st,stmpe2401"; + reg = <0x44>; + reset-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; // GPIO79 + interrupts = <14 IRQ_TYPE_EDGE_FALLING>; // GPIO78 + interrupt-parent = <&gpio2>; + interrupt-controller; + wakeup-source; + pinctrl-names = "default"; + pinctrl-0 = <&stmpe2401_2_nhk_mode>; + stmpe_gpio44: stmpe_gpio { + compatible = "st,stmpe-gpio"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + }; + + amba { + mmcsd: sdi@101f6000 { + cd-gpios = <&stmpe_gpio44 7 GPIO_ACTIVE_LOW>; + wp-gpios = <&stmpe_gpio44 18 GPIO_ACTIVE_HIGH>; + }; + }; + + /* Custom board node with GPIO pins to active etc */ + usb-s8815 { + /* This will turn off SATA so that MMC/SD can thrive */ + mmcsd-gpio { + gpios = <&stmpe_gpio44 2 0x1>; + }; + }; +}; diff --git a/arch/arm/boot/dts/ste-nomadik-s8815.dts b/arch/arm/boot/dts/ste-nomadik-s8815.dts index 90d8b6c7a205..85d3b95dfdba 100644 --- a/arch/arm/boot/dts/ste-nomadik-s8815.dts +++ b/arch/arm/boot/dts/ste-nomadik-s8815.dts @@ -4,6 +4,7 @@ */ /dts-v1/; +#include <dt-bindings/interrupt-controller/irq.h> #include "ste-nomadik-stn8815.dtsi" / { @@ -14,14 +15,6 @@ bootargs = "root=/dev/ram0 console=ttyAMA1,115200n8 earlyprintk"; }; - /* This is where the interrupt is routed on the S8815 board */ - external-bus@34000000 { - ethernet@300 { - interrupt-parent = <&gpio3>; - interrupts = <8 0x1>; - }; - }; - src@101e0000 { /* These chrystal drivers are not used on this board */ disable-sxtalo; @@ -37,20 +30,28 @@ cd_default_mode: cd_default { cd_default_cfg1 { /* CD input GPIO */ - ste,pins = "GPIO111_H21"; + pins = "GPIO111_H21"; ste,input = <0>; }; cd_default_cfg2 { /* CD GPIO biasing */ - ste,pins = "GPIO112_J21"; + pins = "GPIO112_J21"; ste,output = <0>; }; }; }; + gpioi2c { + gpioi2c_default_mode: gpioi2c_default { + gpioi2c_default_cfg { + pins = "GPIO73_C21", "GPIO74_C20"; + ste,input = <0>; + }; + }; + }; user-led { user_led_default_mode: user_led_default { user_led_default_cfg { - ste,pins = "GPIO2_C5"; + pins = "GPIO2_C5"; ste,output = <1>; }; }; @@ -58,13 +59,52 @@ user-button { user_button_default_mode: user_button_default { user_button_default_cfg { - ste,pins = "GPIO3_A4"; + pins = "GPIO3_A4"; ste,input = <0>; }; }; }; }; + /* Ethernet */ + external-bus@34000000 { + compatible = "simple-bus"; + reg = <0x34000000 0x1000000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x34000000 0x1000000>; + ethernet@300 { + compatible = "smsc,lan91c111"; + reg = <0x300 0x0fd00>; + interrupt-parent = <&gpio3>; + interrupts = <8 IRQ_TYPE_EDGE_RISING>; + }; + }; + + /* GPIO I2C connected to the USB portions of the STw4811 only */ + gpio-i2c { + compatible = "i2c-gpio"; + gpios = <&gpio2 10 0>, /* sda */ + <&gpio2 9 0>; /* scl */ + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&gpioi2c_default_mode>; + + stw4811@2d { + compatible = "st,stw4811-usb"; + reg = <0x2d>; + }; + }; + + + /* Configure card detect for the uSD slot */ + amba { + mmcsd: sdi@101f6000 { + cd-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; + }; + }; + /* Custom board node with GPIO pins to active etc */ usb-s8815 { /* This will bias the MMC/SD card detect line */ diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi index dbcf521b017f..f182f6538e90 100644 --- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi +++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi @@ -100,41 +100,41 @@ uart0 { uart0_default_mux: uart0_mux { u0_default_mux { - ste,function = "u0"; - ste,pins = "u0_a_1"; + function = "u0"; + groups = "u0_a_1"; }; }; }; uart1 { uart1_default_mux: uart1_mux { u1_default_mux { - ste,function = "u1"; - ste,pins = "u1_a_1"; + function = "u1"; + groups = "u1_a_1"; }; }; }; mmcsd { mmcsd_default_mux: mmcsd_mux { mmcsd_default_mux { - ste,function = "mmcsd"; - ste,pins = "mmcsd_a_1"; + function = "mmcsd"; + groups = "mmcsd_a_1", "mmcsd_b_1"; }; }; mmcsd_default_mode: mmcsd_default { mmcsd_default_cfg1 { /* MCCLK */ - ste,pins = "GPIO8_B10"; + pins = "GPIO8_B10"; ste,output = <0>; }; mmcsd_default_cfg2 { - /* MCCMDDIR, MCDAT0DIR, MCDAT31DIR */ - ste,pins = "GPIO10_C11", "GPIO15_A12", - "GPIO16_C13"; + /* MCCMDDIR, MCDAT0DIR, MCDAT31DIR, MCDATDIR2 */ + pins = "GPIO10_C11", "GPIO15_A12", + "GPIO16_C13", "GPIO23_D15"; ste,output = <1>; }; mmcsd_default_cfg3 { /* MCCMD, MCDAT3-0, MCMSFBCLK */ - ste,pins = "GPIO9_A10", "GPIO11_B11", + pins = "GPIO9_A10", "GPIO11_B11", "GPIO12_A11", "GPIO13_C12", "GPIO14_B12", "GPIO24_C15"; ste,input = <1>; @@ -144,13 +144,13 @@ i2c0 { i2c0_default_mux: i2c0_mux { i2c0_default_mux { - ste,function = "i2c0"; - ste,pins = "i2c0_a_1"; + function = "i2c0"; + groups = "i2c0_a_1"; }; }; i2c0_default_mode: i2c0_default { i2c0_default_cfg { - ste,pins = "GPIO62_D3", "GPIO63_D2"; + pins = "GPIO62_D3", "GPIO63_D2"; ste,input = <0>; }; }; @@ -158,21 +158,13 @@ i2c1 { i2c1_default_mux: i2c1_mux { i2c1_default_mux { - ste,function = "i2c1"; - ste,pins = "i2c1_a_1"; + function = "i2c1"; + groups = "i2c1_a_1"; }; }; i2c1_default_mode: i2c1_default { i2c1_default_cfg { - ste,pins = "GPIO53_L4", "GPIO54_L3"; - ste,input = <0>; - }; - }; - }; - i2c2 { - i2c2_default_mode: i2c2_default { - i2c2_default_cfg { - ste,pins = "GPIO73_C21", "GPIO74_C20"; + pins = "GPIO53_L4", "GPIO54_L3"; ste,input = <0>; }; }; @@ -182,8 +174,6 @@ src: src@101e0000 { compatible = "stericsson,nomadik-src"; reg = <0x101e0000 0x1000>; - disable-sxtalo; - disable-mxtalo; /* * MXTAL "Main Chrystal" is a chrystal oscillator @19.2 MHz @@ -683,18 +673,6 @@ }; }; - external-bus@34000000 { - compatible = "simple-bus"; - reg = <0x34000000 0x1000000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x34000000 0x1000000>; - ethernet@300 { - compatible = "smsc,lan91c111"; - reg = <0x300 0x0fd00>; - }; - }; - /* I2C0 connected to the STw4811 power management chip */ i2c0 { compatible = "st,nomadik-i2c", "arm,primecell"; @@ -749,22 +727,6 @@ }; }; - /* I2C2 connected to the USB portions of the STw4811 only */ - i2c2 { - compatible = "i2c-gpio"; - gpios = <&gpio2 10 0>, /* sda */ - <&gpio2 9 0>; /* scl */ - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_default_mode>; - - stw4811@2d { - compatible = "st,stw4811-usb"; - reg = <0x2d>; - }; - }; - amba { compatible = "arm,amba-bus"; #address-cells = <1>; @@ -844,7 +806,6 @@ bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; - cd-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; pinctrl-names = "default"; pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>; vmmc-supply = <&vmmc_regulator>; diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts index 3e97a669f15e..206826a855c0 100644 --- a/arch/arm/boot/dts/ste-snowball.dts +++ b/arch/arm/boot/dts/ste-snowball.dts @@ -404,17 +404,17 @@ */ eth_snowball_mode: eth_snowball { snowball_mux { - ste,function = "sm"; - ste,pins = "sm_b_1"; + function = "sm"; + groups = "sm_b_1"; }; /* LAN IRQ pin */ snowball_cfg1 { - ste,pins = "GPIO140_B11"; + pins = "GPIO140_B11"; ste,config = <&in_nopull>; }; /* LAN reset pin */ snowball_cfg2 { - ste,pins = "GPIO141_C12"; + pins = "GPIO141_C12"; ste,config = <&gpio_out_hi>; }; @@ -423,11 +423,11 @@ sdi0 { sdi0_default_mode: sdi0_default { snowball_mux { - ste,function = "mc0"; - ste,pins = "mc0dat31dir_a_1"; + function = "mc0"; + groups = "mc0dat31dir_a_1"; }; snowball_cfg1 { - ste,pins = "GPIO21_AB3"; /* DAT31DIR */ + pins = "GPIO21_AB3"; /* DAT31DIR */ ste,config = <&out_hi>; }; @@ -436,19 +436,19 @@ ssp0 { ssp0_snowball_mode: ssp0_snowball_default { snowball_mux { - ste,function = "ssp0"; - ste,pins = "ssp0_a_1"; + function = "ssp0"; + groups = "ssp0_a_1"; }; snowball_cfg1 { - ste,pins = "GPIO144_B13"; /* FRM */ + pins = "GPIO144_B13"; /* FRM */ ste,config = <&gpio_out_hi>; }; snowball_cfg2 { - ste,pins = "GPIO145_C13"; /* RXD */ + pins = "GPIO145_C13"; /* RXD */ ste,config = <&in_pd>; }; snowball_cfg3 { - ste,pins = + pins = "GPIO146_D13", /* TXD */ "GPIO143_D12"; /* CLK */ ste,config = <&out_lo>; @@ -459,7 +459,7 @@ gpio_led { gpioled_snowball_mode: gpioled_default { snowball_cfg1 { - ste,pins = "GPIO142_C11"; + pins = "GPIO142_C11"; ste,config = <&gpio_out_hi>; }; @@ -469,7 +469,7 @@ accel_snowball_mode: accel_snowball { /* Accelerometer lines */ snowball_cfg1 { - ste,pins = + pins = "GPIO163_C20", /* ACCEL_IRQ1 */ "GPIO164_B21"; /* ACCEL_IRQ2 */ ste,config = <&gpio_in_pu>; @@ -479,7 +479,7 @@ magnetometer { magneto_snowball_mode: magneto_snowball { snowball_cfg1 { - ste,pins = "GPIO165_C21"; /* MAG_DRDY */ + pins = "GPIO165_C21"; /* MAG_DRDY */ ste,config = <&gpio_in_pu>; }; }; @@ -491,7 +491,7 @@ * pull low to reset state */ snowball_cfg1 { - ste,pins = "GPIO171_D23"; /* GBF_ENA_RESET */ + pins = "GPIO171_D23"; /* GBF_ENA_RESET */ ste,config = <&gpio_out_lo>; }; }; @@ -503,13 +503,13 @@ * These are plain GPIO pins used by WLAN */ snowball_cfg1 { - ste,pins = + pins = "GPIO161_D21", /* WLAN_PMU_EN */ "GPIO215_AH13"; /* WLAN_ENA */ ste,config = <&gpio_out_lo>; }; snowball_cfg2 { - ste,pins = "GPIO216_AG12"; /* WLAN_IRQ */ + pins = "GPIO216_AG12"; /* WLAN_IRQ */ ste,config = <&gpio_in_pu>; }; }; diff --git a/arch/arm/boot/dts/stih407-b2120.dts b/arch/arm/boot/dts/stih407-b2120.dts index fe69f92e5f82..261d5e2c48d2 100644 --- a/arch/arm/boot/dts/stih407-b2120.dts +++ b/arch/arm/boot/dts/stih407-b2120.dts @@ -7,13 +7,15 @@ * published by the Free Software Foundation. */ /dts-v1/; -#include "stih407.dtsi" +#include "stih407-clock.dtsi" +#include "stih407-family.dtsi" +#include "stihxxx-b2120.dtsi" / { model = "STiH407 B2120"; compatible = "st,stih407-b2120", "st,stih407"; chosen { - bootargs = "console=ttyAS0,115200"; + bootargs = "console=ttyAS0,115200 clk_ignore_unused"; linux,stdout-path = &sbc_serial0; }; @@ -26,53 +28,4 @@ ttyAS0 = &sbc_serial0; }; - soc { - sbc_serial0: serial@9530000 { - status = "okay"; - }; - - leds { - compatible = "gpio-leds"; - red { - #gpio-cells = <2>; - label = "Front Panel LED"; - gpios = <&pio4 1 0>; - linux,default-trigger = "heartbeat"; - }; - green { - #gpio-cells = <2>; - gpios = <&pio1 3 0>; - default-state = "off"; - }; - }; - - i2c@9842000 { - status = "okay"; - }; - - i2c@9843000 { - status = "okay"; - }; - - i2c@9844000 { - status = "okay"; - }; - - i2c@9845000 { - status = "okay"; - }; - - i2c@9540000 { - status = "okay"; - }; - - /* SSC11 to HDMI */ - i2c@9541000 { - status = "okay"; - /* HDMI V1.3a supports Standard mode only */ - clock-frequency = <100000>; - st,i2c-min-scl-pulse-width-us = <0>; - st,i2c-min-sda-pulse-width-us = <5>; - }; - }; }; diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi index 800f46f009f3..e65744fc12ab 100644 --- a/arch/arm/boot/dts/stih407-clock.dtsi +++ b/arch/arm/boot/dts/stih407-clock.dtsi @@ -5,8 +5,13 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ +#include <dt-bindings/clock/stih407-clks.h> / { clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + /* * Fixed 30MHz oscillator inputs to SoC */ @@ -19,10 +24,59 @@ /* * ARM Peripheral clock for timers */ - arm_periph_clk: arm-periph-clk { + arm_periph_clk: clk-m-a9-periphs { #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <600000000>; + compatible = "fixed-factor-clock"; + + clocks = <&clk_m_a9>; + clock-div = <2>; + clock-mult = <1>; + }; + + /* + * A9 PLL. + */ + clockgen-a9@92b0000 { + compatible = "st,clkgen-c32"; + reg = <0x92b0000 0xffff>; + + clockgen_a9_pll: clockgen-a9-pll { + #clock-cells = <1>; + compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32"; + + clocks = <&clk_sysin>; + + clock-output-names = "clockgen-a9-pll-odf"; + }; + }; + + /* + * ARM CPU related clocks. + */ + clk_m_a9: clk-m-a9@92b0000 { + #clock-cells = <0>; + compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; + reg = <0x92b0000 0x10000>; + + clocks = <&clockgen_a9_pll 0>, + <&clockgen_a9_pll 0>, + <&clk_s_c0_flexgen 13>, + <&clk_m_a9_ext2f_div2>; + }; + + /* + * ARM Peripheral clock for timers + */ + clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + + clocks = <&clk_s_c0_flexgen 13>; + + clock-output-names = "clk-m-a9-ext2f-div2"; + + clock-div = <2>; + clock-mult = <1>; }; /* @@ -35,5 +89,238 @@ clock-frequency = <200000000>; clock-output-names = "clk-s-icn-reg-0"; }; + + clockgen-a@090ff000 { + compatible = "st,clkgen-c32"; + reg = <0x90ff000 0x1000>; + + clk_s_a0_pll: clk-s-a0-pll { + #clock-cells = <1>; + compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32"; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-s-a0-pll-ofd-0"; + }; + + clk_s_a0_flexgen: clk-s-a0-flexgen { + compatible = "st,flexgen"; + + #clock-cells = <1>; + + clocks = <&clk_s_a0_pll 0>, + <&clk_sysin>; + + clock-output-names = "clk-ic-lmi0"; + }; + }; + + clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { + #clock-cells = <1>; + compatible = "st,stih407-quadfs660-C", "st,quadfs"; + reg = <0x9103000 0x1000>; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-s-c0-fs0-ch0", + "clk-s-c0-fs0-ch1", + "clk-s-c0-fs0-ch2", + "clk-s-c0-fs0-ch3"; + }; + + clk_s_c0: clockgen-c@09103000 { + compatible = "st,clkgen-c32"; + reg = <0x9103000 0x1000>; + + clk_s_c0_pll0: clk-s-c0-pll0 { + #clock-cells = <1>; + compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-s-c0-pll0-odf-0"; + }; + + clk_s_c0_pll1: clk-s-c0-pll1 { + #clock-cells = <1>; + compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-s-c0-pll1-odf-0"; + }; + + clk_s_c0_flexgen: clk-s-c0-flexgen { + #clock-cells = <1>; + compatible = "st,flexgen"; + + clocks = <&clk_s_c0_pll0 0>, + <&clk_s_c0_pll1 0>, + <&clk_s_c0_quadfs 0>, + <&clk_s_c0_quadfs 1>, + <&clk_s_c0_quadfs 2>, + <&clk_s_c0_quadfs 3>, + <&clk_sysin>; + + clock-output-names = "clk-icn-gpu", + "clk-fdma", + "clk-nand", + "clk-hva", + "clk-proc-stfe", + "clk-proc-tp", + "clk-rx-icn-dmu", + "clk-rx-icn-hva", + "clk-icn-cpu", + "clk-tx-icn-dmu", + "clk-mmc-0", + "clk-mmc-1", + "clk-jpegdec", + "clk-ext2fa9", + "clk-ic-bdisp-0", + "clk-ic-bdisp-1", + "clk-pp-dmu", + "clk-vid-dmu", + "clk-dss-lpc", + "clk-st231-aud-0", + "clk-st231-gp-1", + "clk-st231-dmu", + "clk-icn-lmi", + "clk-tx-icn-disp-1", + "clk-icn-sbc", + "clk-stfe-frc2", + "clk-eth-phy", + "clk-eth-ref-phyclk", + "clk-flash-promip", + "clk-main-disp", + "clk-aux-disp", + "clk-compo-dvp"; + }; + }; + + clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { + #clock-cells = <1>; + compatible = "st,stih407-quadfs660-D", "st,quadfs"; + reg = <0x9104000 0x1000>; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-s-d0-fs0-ch0", + "clk-s-d0-fs0-ch1", + "clk-s-d0-fs0-ch2", + "clk-s-d0-fs0-ch3"; + }; + + clockgen-d0@09104000 { + compatible = "st,clkgen-c32"; + reg = <0x9104000 0x1000>; + + clk_s_d0_flexgen: clk-s-d0-flexgen { + #clock-cells = <1>; + compatible = "st,flexgen"; + + clocks = <&clk_s_d0_quadfs 0>, + <&clk_s_d0_quadfs 1>, + <&clk_s_d0_quadfs 2>, + <&clk_s_d0_quadfs 3>, + <&clk_sysin>; + + clock-output-names = "clk-pcm-0", + "clk-pcm-1", + "clk-pcm-2", + "clk-spdiff"; + }; + }; + + clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { + #clock-cells = <1>; + compatible = "st,stih407-quadfs660-D", "st,quadfs"; + reg = <0x9106000 0x1000>; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-s-d2-fs0-ch0", + "clk-s-d2-fs0-ch1", + "clk-s-d2-fs0-ch2", + "clk-s-d2-fs0-ch3"; + }; + + clk_tmdsout_hdmi: clk-tmdsout-hdmi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + clockgen-d2@x9106000 { + compatible = "st,clkgen-c32"; + reg = <0x9106000 0x1000>; + + clk_s_d2_flexgen: clk-s-d2-flexgen { + #clock-cells = <1>; + compatible = "st,flexgen"; + + clocks = <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>, + <&clk_s_d2_quadfs 2>, + <&clk_s_d2_quadfs 3>, + <&clk_sysin>, + <&clk_sysin>, + <&clk_tmdsout_hdmi>; + + clock-output-names = "clk-pix-main-disp", + "clk-pix-pip", + "clk-pix-gdp1", + "clk-pix-gdp2", + "clk-pix-gdp3", + "clk-pix-gdp4", + "clk-pix-aux-disp", + "clk-denc", + "clk-pix-hddac", + "clk-hddac", + "clk-sddac", + "clk-pix-dvo", + "clk-dvo", + "clk-pix-hdmi", + "clk-tmds-hdmi", + "clk-ref-hdmiphy"; + }; + }; + + clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { + #clock-cells = <1>; + compatible = "st,stih407-quadfs660-D", "st,quadfs"; + reg = <0x9107000 0x1000>; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-s-d3-fs0-ch0", + "clk-s-d3-fs0-ch1", + "clk-s-d3-fs0-ch2", + "clk-s-d3-fs0-ch3"; + }; + + clockgen-d3@9107000 { + compatible = "st,clkgen-c32"; + reg = <0x9107000 0x1000>; + + clk_s_d3_flexgen: clk-s-d3-flexgen { + #clock-cells = <1>; + compatible = "st,flexgen"; + + clocks = <&clk_s_d3_quadfs 0>, + <&clk_s_d3_quadfs 1>, + <&clk_s_d3_quadfs 2>, + <&clk_s_d3_quadfs 3>, + <&clk_sysin>; + + clock-output-names = "clk-stfe-frc1", + "clk-tsout-0", + "clk-tsout-1", + "clk-mchi", + "clk-vsens-compo", + "clk-frc1-remote", + "clk-lpc-0", + "clk-lpc-1"; + }; + }; }; }; diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407-family.dtsi index 4f9024f19866..3e31d32133b8 100644 --- a/arch/arm/boot/dts/stih407.dtsi +++ b/arch/arm/boot/dts/stih407-family.dtsi @@ -6,8 +6,8 @@ * it under the terms of the GNU General Public License version 2 as * publishhed by the Free Software Foundation. */ -#include "stih407-clock.dtsi" #include "stih407-pinctrl.dtsi" +#include <dt-bindings/reset-controller/stih407-resets.h> / { #address-cells = <1>; #size-cells = <1>; @@ -63,6 +63,21 @@ ranges; compatible = "simple-bus"; + powerdown: powerdown-controller { + compatible = "st,stih407-powerdown"; + #reset-cells = <1>; + }; + + softreset: softreset-controller { + compatible = "st,stih407-softreset"; + #reset-cells = <1>; + }; + + picophyreset: picophyreset-controller { + compatible = "st,stih407-picophyreset"; + #reset-cells = <1>; + }; + syscfg_sbc: sbc-syscfg@9620000 { compatible = "st,stih407-sbc-syscfg", "syscon"; reg = <0x9620000 0x1000>; @@ -104,7 +119,7 @@ interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_serial0>; - clocks = <&clk_ext2f_a9>; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; status = "disabled"; }; @@ -115,7 +130,7 @@ interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_serial1>; - clocks = <&clk_ext2f_a9>; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; status = "disabled"; }; @@ -126,7 +141,7 @@ interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_serial2>; - clocks = <&clk_ext2f_a9>; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; status = "disabled"; }; @@ -158,7 +173,7 @@ compatible = "st,comms-ssc4-i2c"; interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; reg = <0x9840000 0x110>; - clocks = <&clk_ext2f_a9>; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; @@ -171,7 +186,7 @@ compatible = "st,comms-ssc4-i2c"; reg = <0x9841000 0x110>; interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_ext2f_a9>; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; @@ -184,7 +199,7 @@ compatible = "st,comms-ssc4-i2c"; reg = <0x9842000 0x110>; interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_ext2f_a9>; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; @@ -197,7 +212,7 @@ compatible = "st,comms-ssc4-i2c"; reg = <0x9843000 0x110>; interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_ext2f_a9>; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; @@ -210,7 +225,7 @@ compatible = "st,comms-ssc4-i2c"; reg = <0x9844000 0x110>; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_ext2f_a9>; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; @@ -223,7 +238,7 @@ compatible = "st,comms-ssc4-i2c"; reg = <0x9845000 0x110>; interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_ext2f_a9>; + clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; clock-names = "ssc"; clock-frequency = <400000>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/stih410-b2120.dts b/arch/arm/boot/dts/stih410-b2120.dts new file mode 100644 index 000000000000..2f61a9960dee --- /dev/null +++ b/arch/arm/boot/dts/stih410-b2120.dts @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2014 STMicroelectronics (R&D) Limited. + * Author: Peter Griffin <peter.griffin@linaro.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; +#include "stih410.dtsi" +#include "stihxxx-b2120.dtsi" +/ { + model = "STiH410 B2120"; + compatible = "st,stih410-b2120", "st,stih410"; + + chosen { + bootargs = "console=ttyAS0,115200 clk_ignore_unused"; + linux,stdout-path = &sbc_serial0; + }; + + memory { + device_type = "memory"; + reg = <0x40000000 0x80000000>; + }; + + aliases { + ttyAS0 = &sbc_serial0; + }; +}; diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi new file mode 100644 index 000000000000..6b5803a30096 --- /dev/null +++ b/arch/arm/boot/dts/stih410-clock.dtsi @@ -0,0 +1,338 @@ +/* + * Copyright (C) 2014 STMicroelectronics R&D Limited + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#include <dt-bindings/clock/stih410-clks.h> +/ { + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + compatible = "st,stih410-clk", "simple-bus"; + + /* + * Fixed 30MHz oscillator inputs to SoC + */ + clk_sysin: clk-sysin { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <30000000>; + clock-output-names = "CLK_SYSIN"; + }; + + /* + * ARM Peripheral clock for timers + */ + arm_periph_clk: clk-m-a9-periphs { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + clocks = <&clk_m_a9>; + clock-div = <2>; + clock-mult = <1>; + }; + + /* + * A9 PLL. + */ + clockgen-a9@92b0000 { + compatible = "st,clkgen-c32"; + reg = <0x92b0000 0xffff>; + + clockgen_a9_pll: clockgen-a9-pll { + #clock-cells = <1>; + compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32"; + + clocks = <&clk_sysin>; + + clock-output-names = "clockgen-a9-pll-odf"; + }; + }; + + /* + * ARM CPU related clocks. + */ + clk_m_a9: clk-m-a9@92b0000 { + #clock-cells = <0>; + compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; + reg = <0x92b0000 0x10000>; + + clocks = <&clockgen_a9_pll 0>, + <&clockgen_a9_pll 0>, + <&clk_s_c0_flexgen 13>, + <&clk_m_a9_ext2f_div2>; + }; + + /* + * ARM Peripheral clock for timers + */ + clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { + #clock-cells = <0>; + compatible = "fixed-factor-clock"; + + clocks = <&clk_s_c0_flexgen 13>; + + clock-output-names = "clk-m-a9-ext2f-div2"; + + clock-div = <2>; + clock-mult = <1>; + }; + + /* + * Bootloader initialized system infrastructure clock for + * serial devices. + */ + clk_ext2f_a9: clockgen-c0@13 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + clock-output-names = "clk-s-icn-reg-0"; + }; + + clockgen-a@090ff000 { + compatible = "st,clkgen-c32"; + reg = <0x90ff000 0x1000>; + + clk_s_a0_pll: clk-s-a0-pll { + #clock-cells = <1>; + compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32"; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-s-a0-pll-ofd-0"; + }; + + clk_s_a0_flexgen: clk-s-a0-flexgen { + compatible = "st,flexgen"; + + #clock-cells = <1>; + + clocks = <&clk_s_a0_pll 0>, + <&clk_sysin>; + + clock-output-names = "clk-ic-lmi0", + "clk-ic-lmi1"; + }; + }; + + clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { + #clock-cells = <1>; + compatible = "st,stih407-quadfs660-C", "st,quadfs"; + reg = <0x9103000 0x1000>; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-s-c0-fs0-ch0", + "clk-s-c0-fs0-ch1", + "clk-s-c0-fs0-ch2", + "clk-s-c0-fs0-ch3"; + }; + + clk_s_c0: clockgen-c@09103000 { + compatible = "st,clkgen-c32"; + reg = <0x9103000 0x1000>; + + clk_s_c0_pll0: clk-s-c0-pll0 { + #clock-cells = <1>; + compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-s-c0-pll0-odf-0"; + }; + + clk_s_c0_pll1: clk-s-c0-pll1 { + #clock-cells = <1>; + compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-s-c0-pll1-odf-0"; + }; + + clk_s_c0_flexgen: clk-s-c0-flexgen { + #clock-cells = <1>; + compatible = "st,flexgen"; + + clocks = <&clk_s_c0_pll0 0>, + <&clk_s_c0_pll1 0>, + <&clk_s_c0_quadfs 0>, + <&clk_s_c0_quadfs 1>, + <&clk_s_c0_quadfs 2>, + <&clk_s_c0_quadfs 3>, + <&clk_sysin>; + + clock-output-names = "clk-icn-gpu", + "clk-fdma", + "clk-nand", + "clk-hva", + "clk-proc-stfe", + "clk-proc-tp", + "clk-rx-icn-dmu", + "clk-rx-icn-hva", + "clk-icn-cpu", + "clk-tx-icn-dmu", + "clk-mmc-0", + "clk-mmc-1", + "clk-jpegdec", + "clk-ext2fa9", + "clk-ic-bdisp-0", + "clk-ic-bdisp-1", + "clk-pp-dmu", + "clk-vid-dmu", + "clk-dss-lpc", + "clk-st231-aud-0", + "clk-st231-gp-1", + "clk-st231-dmu", + "clk-icn-lmi", + "clk-tx-icn-disp-1", + "clk-icn-sbc", + "clk-stfe-frc2", + "clk-eth-phy", + "clk-eth-ref-phyclk", + "clk-flash-promip", + "clk-main-disp", + "clk-aux-disp", + "clk-compo-dvp", + "clk-tx-icn-hades", + "clk-rx-icn-hades", + "clk-icn-reg-16", + "clk-pp-hades", + "clk-clust-hades", + "clk-hwpe-hades", + "clk-fc-hades"; + }; + }; + + clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { + #clock-cells = <1>; + compatible = "st,stih407-quadfs660-D", "st,quadfs"; + reg = <0x9104000 0x1000>; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-s-d0-fs0-ch0", + "clk-s-d0-fs0-ch1", + "clk-s-d0-fs0-ch2", + "clk-s-d0-fs0-ch3"; + }; + + clockgen-d0@09104000 { + compatible = "st,clkgen-c32"; + reg = <0x9104000 0x1000>; + + clk_s_d0_flexgen: clk-s-d0-flexgen { + #clock-cells = <1>; + compatible = "st,flexgen"; + + clocks = <&clk_s_d0_quadfs 0>, + <&clk_s_d0_quadfs 1>, + <&clk_s_d0_quadfs 2>, + <&clk_s_d0_quadfs 3>, + <&clk_sysin>; + + clock-output-names = "clk-pcm-0", + "clk-pcm-1", + "clk-pcm-2", + "clk-spdiff", + "clk-pcmr10-master", + "clk-usb2-phy"; + }; + }; + + clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { + #clock-cells = <1>; + compatible = "st,stih407-quadfs660-D", "st,quadfs"; + reg = <0x9106000 0x1000>; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-s-d2-fs0-ch0", + "clk-s-d2-fs0-ch1", + "clk-s-d2-fs0-ch2", + "clk-s-d2-fs0-ch3"; + }; + + clk_tmdsout_hdmi: clk-tmdsout-hdmi { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <0>; + }; + + clockgen-d2@x9106000 { + compatible = "st,clkgen-c32"; + reg = <0x9106000 0x1000>; + + clk_s_d2_flexgen: clk-s-d2-flexgen { + #clock-cells = <1>; + compatible = "st,flexgen"; + + clocks = <&clk_s_d2_quadfs 0>, + <&clk_s_d2_quadfs 1>, + <&clk_s_d2_quadfs 2>, + <&clk_s_d2_quadfs 3>, + <&clk_sysin>, + <&clk_sysin>, + <&clk_tmdsout_hdmi>; + + clock-output-names = "clk-pix-main-disp", + "clk-pix-pip", + "clk-pix-gdp1", + "clk-pix-gdp2", + "clk-pix-gdp3", + "clk-pix-gdp4", + "clk-pix-aux-disp", + "clk-denc", + "clk-pix-hddac", + "clk-hddac", + "clk-sddac", + "clk-pix-dvo", + "clk-dvo", + "clk-pix-hdmi", + "clk-tmds-hdmi", + "clk-ref-hdmiphy"; + }; + }; + + clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { + #clock-cells = <1>; + compatible = "st,stih407-quadfs660-D", "st,quadfs"; + reg = <0x9107000 0x1000>; + + clocks = <&clk_sysin>; + + clock-output-names = "clk-s-d3-fs0-ch0", + "clk-s-d3-fs0-ch1", + "clk-s-d3-fs0-ch2", + "clk-s-d3-fs0-ch3"; + }; + + clockgen-d3@9107000 { + compatible = "st,clkgen-c32"; + reg = <0x9107000 0x1000>; + + clk_s_d3_flexgen: clk-s-d3-flexgen { + #clock-cells = <1>; + compatible = "st,flexgen"; + + clocks = <&clk_s_d3_quadfs 0>, + <&clk_s_d3_quadfs 1>, + <&clk_s_d3_quadfs 2>, + <&clk_s_d3_quadfs 3>, + <&clk_sysin>; + + clock-output-names = "clk-stfe-frc1", + "clk-tsout-0", + "clk-tsout-1", + "clk-mchi", + "clk-vsens-compo", + "clk-frc1-remote", + "clk-lpc-0", + "clk-lpc-1"; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/stih410-pinctrl.dtsi b/arch/arm/boot/dts/stih410-pinctrl.dtsi new file mode 100644 index 000000000000..b3e9dfc81c07 --- /dev/null +++ b/arch/arm/boot/dts/stih410-pinctrl.dtsi @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2014 STMicroelectronics Limited. + * Author: Peter Griffin <peter.griffin@linaro.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ +#include "st-pincfg.h" +/ { + + soc { + pin-controller-rear { + + usb0 { + pinctrl_usb0: usb2-0 { + st,pins { + usb-oc-detect = <&pio35 0 ALT1 IN>; + usb-pwr-enable = <&pio35 1 ALT1 OUT>; + }; + }; + }; + + usb1 { + pinctrl_usb1: usb2-1 { + st,pins { + usb-oc-detect = <&pio35 2 ALT1 IN>; + usb-pwr-enable = <&pio35 3 ALT1 OUT>; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi new file mode 100644 index 000000000000..c05627eb717d --- /dev/null +++ b/arch/arm/boot/dts/stih410.dtsi @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2014 STMicroelectronics Limited. + * Author: Peter Griffin <peter.griffin@linaro.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * publishhed by the Free Software Foundation. + */ +#include "stih410-clock.dtsi" +#include "stih407-family.dtsi" +#include "stih410-pinctrl.dtsi" +/ { + +}; diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi index 8509a037ae21..3791ad95dbaf 100644 --- a/arch/arm/boot/dts/stih415-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi @@ -11,33 +11,33 @@ / { aliases { - gpio0 = &PIO0; - gpio1 = &PIO1; - gpio2 = &PIO2; - gpio3 = &PIO3; - gpio4 = &PIO4; - gpio5 = &PIO5; - gpio6 = &PIO6; - gpio7 = &PIO7; - gpio8 = &PIO8; - gpio9 = &PIO9; - gpio10 = &PIO10; - gpio11 = &PIO11; - gpio12 = &PIO12; - gpio13 = &PIO13; - gpio14 = &PIO14; - gpio15 = &PIO15; - gpio16 = &PIO16; - gpio17 = &PIO17; - gpio18 = &PIO18; - gpio19 = &PIO100; - gpio20 = &PIO101; - gpio21 = &PIO102; - gpio22 = &PIO103; - gpio23 = &PIO104; - gpio24 = &PIO105; - gpio25 = &PIO106; - gpio26 = &PIO107; + gpio0 = &pio0; + gpio1 = &pio1; + gpio2 = &pio2; + gpio3 = &pio3; + gpio4 = &pio4; + gpio5 = &pio5; + gpio6 = &pio6; + gpio7 = &pio7; + gpio8 = &pio8; + gpio9 = &pio9; + gpio10 = &pio10; + gpio11 = &pio11; + gpio12 = &pio12; + gpio13 = &pio13; + gpio14 = &pio14; + gpio15 = &pio15; + gpio16 = &pio16; + gpio17 = &pio17; + gpio18 = &pio18; + gpio19 = &pio100; + gpio20 = &pio101; + gpio21 = &pio102; + gpio22 = &pio103; + gpio23 = &pio104; + gpio24 = &pio105; + gpio25 = &pio106; + gpio26 = &pio107; }; soc { @@ -52,7 +52,7 @@ interrupt-names = "irqmux"; ranges = <0 0xfe610000 0x5000>; - PIO0: gpio@fe610000 { + pio0: gpio@fe610000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -60,7 +60,7 @@ reg = <0 0x100>; st,bank-name = "PIO0"; }; - PIO1: gpio@fe611000 { + pio1: gpio@fe611000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -68,7 +68,7 @@ reg = <0x1000 0x100>; st,bank-name = "PIO1"; }; - PIO2: gpio@fe612000 { + pio2: gpio@fe612000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -76,7 +76,7 @@ reg = <0x2000 0x100>; st,bank-name = "PIO2"; }; - PIO3: gpio@fe613000 { + pio3: gpio@fe613000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -84,7 +84,7 @@ reg = <0x3000 0x100>; st,bank-name = "PIO3"; }; - PIO4: gpio@fe614000 { + pio4: gpio@fe614000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -96,8 +96,8 @@ sbc_serial1 { pinctrl_sbc_serial1:sbc_serial1 { st,pins { - tx = <&PIO2 6 ALT3 OUT>; - rx = <&PIO2 7 ALT3 IN>; + tx = <&pio2 6 ALT3 OUT>; + rx = <&pio2 7 ALT3 IN>; }; }; }; @@ -105,15 +105,15 @@ keyscan { pinctrl_keyscan: keyscan { st,pins { - keyin0 = <&PIO0 2 ALT2 IN>; - keyin1 = <&PIO0 3 ALT2 IN>; - keyin2 = <&PIO0 4 ALT2 IN>; - keyin3 = <&PIO2 6 ALT2 IN>; - - keyout0 = <&PIO1 6 ALT2 OUT>; - keyout1 = <&PIO1 7 ALT2 OUT>; - keyout2 = <&PIO0 6 ALT2 OUT>; - keyout3 = <&PIO2 7 ALT2 OUT>; + keyin0 = <&pio0 2 ALT2 IN>; + keyin1 = <&pio0 3 ALT2 IN>; + keyin2 = <&pio0 4 ALT2 IN>; + keyin3 = <&pio2 6 ALT2 IN>; + + keyout0 = <&pio1 6 ALT2 OUT>; + keyout1 = <&pio1 7 ALT2 OUT>; + keyout2 = <&pio0 6 ALT2 OUT>; + keyout3 = <&pio2 7 ALT2 OUT>; }; }; }; @@ -121,8 +121,8 @@ sbc_i2c0 { pinctrl_sbc_i2c0_default: sbc_i2c0-default { st,pins { - sda = <&PIO4 6 ALT1 BIDIR>; - scl = <&PIO4 5 ALT1 BIDIR>; + sda = <&pio4 6 ALT1 BIDIR>; + scl = <&pio4 5 ALT1 BIDIR>; }; }; }; @@ -130,8 +130,8 @@ sbc_i2c1 { pinctrl_sbc_i2c1_default: sbc_i2c1-default { st,pins { - sda = <&PIO3 2 ALT2 BIDIR>; - scl = <&PIO3 1 ALT2 BIDIR>; + sda = <&pio3 2 ALT2 BIDIR>; + scl = <&pio3 1 ALT2 BIDIR>; }; }; }; @@ -139,7 +139,7 @@ rc{ pinctrl_ir: ir0 { st,pins { - ir = <&PIO4 0 ALT2 IN>; + ir = <&pio4 0 ALT2 IN>; }; }; }; @@ -147,49 +147,49 @@ gmac1 { pinctrl_mii1: mii1 { st,pins { - txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>; - col = <&PIO0 7 ALT1 IN BYPASS 1000>; - mdio = <&PIO1 0 ALT1 OUT BYPASS 0>; - mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>; - crs = <&PIO1 2 ALT1 IN BYPASS 1000>; - mdint = <&PIO1 3 ALT1 IN BYPASS 0>; - rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&PIO2 3 ALT1 IN NICLK 1000 CLK_A>; + txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; + col = <&pio0 7 ALT1 IN BYPASS 1000>; + mdio = <&pio1 0 ALT1 OUT BYPASS 0>; + mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; + crs = <&pio1 2 ALT1 IN BYPASS 1000>; + mdint = <&pio1 3 ALT1 IN BYPASS 0>; + rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; + phyclk = <&pio2 3 ALT1 IN NICLK 1000 CLK_A>; }; }; pinctrl_rgmii1: rgmii1-0 { st,pins { - txd0 = <&PIO0 0 ALT1 OUT DE_IO 1000 CLK_A>; - txd1 = <&PIO0 1 ALT1 OUT DE_IO 1000 CLK_A>; - txd2 = <&PIO0 2 ALT1 OUT DE_IO 1000 CLK_A>; - txd3 = <&PIO0 3 ALT1 OUT DE_IO 1000 CLK_A>; - txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>; - txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>; - mdio = <&PIO1 0 ALT1 OUT BYPASS 0>; - mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>; - rxd0 = <&PIO1 4 ALT1 IN DE_IO 0 CLK_A>; - rxd1 = <&PIO1 5 ALT1 IN DE_IO 0 CLK_A>; - rxd2 = <&PIO1 6 ALT1 IN DE_IO 0 CLK_A>; - rxd3 = <&PIO1 7 ALT1 IN DE_IO 0 CLK_A>; - - rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>; - rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>; - - clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>; + txd0 = <&pio0 0 ALT1 OUT DE_IO 1000 CLK_A>; + txd1 = <&pio0 1 ALT1 OUT DE_IO 1000 CLK_A>; + txd2 = <&pio0 2 ALT1 OUT DE_IO 1000 CLK_A>; + txd3 = <&pio0 3 ALT1 OUT DE_IO 1000 CLK_A>; + txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>; + txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; + mdio = <&pio1 0 ALT1 OUT BYPASS 0>; + mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; + rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>; + rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>; + rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>; + rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>; + + rxdv = <&pio2 0 ALT1 IN DE_IO 500 CLK_A>; + rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; + phyclk = <&pio2 3 ALT4 OUT NICLK 0 CLK_B>; + + clk125= <&pio3 7 ALT4 IN NICLK 0 CLK_A>; }; }; }; @@ -206,7 +206,7 @@ interrupt-names = "irqmux"; ranges = <0 0xfee00000 0x8000>; - PIO5: gpio@fee00000 { + pio5: gpio@fee00000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -214,7 +214,7 @@ reg = <0 0x100>; st,bank-name = "PIO5"; }; - PIO6: gpio@fee01000 { + pio6: gpio@fee01000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -222,7 +222,7 @@ reg = <0x1000 0x100>; st,bank-name = "PIO6"; }; - PIO7: gpio@fee02000 { + pio7: gpio@fee02000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -230,7 +230,7 @@ reg = <0x2000 0x100>; st,bank-name = "PIO7"; }; - PIO8: gpio@fee03000 { + pio8: gpio@fee03000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -238,7 +238,7 @@ reg = <0x3000 0x100>; st,bank-name = "PIO8"; }; - PIO9: gpio@fee04000 { + pio9: gpio@fee04000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -246,7 +246,7 @@ reg = <0x4000 0x100>; st,bank-name = "PIO9"; }; - PIO10: gpio@fee05000 { + pio10: gpio@fee05000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -254,7 +254,7 @@ reg = <0x5000 0x100>; st,bank-name = "PIO10"; }; - PIO11: gpio@fee06000 { + pio11: gpio@fee06000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -262,7 +262,7 @@ reg = <0x6000 0x100>; st,bank-name = "PIO11"; }; - PIO12: gpio@fee07000 { + pio12: gpio@fee07000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -274,8 +274,8 @@ i2c0 { pinctrl_i2c0_default: i2c0-default { st,pins { - sda = <&PIO9 3 ALT1 BIDIR>; - scl = <&PIO9 2 ALT1 BIDIR>; + sda = <&pio9 3 ALT1 BIDIR>; + scl = <&pio9 2 ALT1 BIDIR>; }; }; }; @@ -283,8 +283,8 @@ i2c1 { pinctrl_i2c1_default: i2c1-default { st,pins { - sda = <&PIO12 1 ALT1 BIDIR>; - scl = <&PIO12 0 ALT1 BIDIR>; + sda = <&pio12 1 ALT1 BIDIR>; + scl = <&pio12 0 ALT1 BIDIR>; }; }; }; @@ -301,7 +301,7 @@ interrupt-names = "irqmux"; ranges = <0 0xfe820000 0x8000>; - PIO13: gpio@fe820000 { + pio13: gpio@fe820000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -309,7 +309,7 @@ reg = <0 0x100>; st,bank-name = "PIO13"; }; - PIO14: gpio@fe821000 { + pio14: gpio@fe821000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -317,7 +317,7 @@ reg = <0x1000 0x100>; st,bank-name = "PIO14"; }; - PIO15: gpio@fe822000 { + pio15: gpio@fe822000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -325,7 +325,7 @@ reg = <0x2000 0x100>; st,bank-name = "PIO15"; }; - PIO16: gpio@fe823000 { + pio16: gpio@fe823000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -333,7 +333,7 @@ reg = <0x3000 0x100>; st,bank-name = "PIO16"; }; - PIO17: gpio@fe824000 { + pio17: gpio@fe824000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -341,7 +341,7 @@ reg = <0x4000 0x100>; st,bank-name = "PIO17"; }; - PIO18: gpio@fe825000 { + pio18: gpio@fe825000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -353,8 +353,8 @@ serial2 { pinctrl_serial2: serial2-0 { st,pins { - tx = <&PIO17 4 ALT2 OUT>; - rx = <&PIO17 5 ALT2 IN>; + tx = <&pio17 4 ALT2 OUT>; + rx = <&pio17 5 ALT2 IN>; }; }; }; @@ -362,73 +362,94 @@ gmac0{ pinctrl_mii0: mii0 { st,pins { - mdint = <&PIO13 6 ALT2 IN BYPASS 0>; - txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - - txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>; - txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>; - - txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>; - txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - crs = <&PIO15 2 ALT2 IN BYPASS 1000>; - col = <&PIO15 3 ALT2 IN BYPASS 1000>; - mdio = <&PIO15 4 ALT2 OUT BYPASS 3000>; - mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>; - - rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>; - phyclk = <&PIO13 5 ALT2 OUT NICLK 1000 CLK_A>; + mdint = <&pio13 6 ALT2 IN BYPASS 0>; + txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; + + txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; + txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; + txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>; + txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>; + + txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>; + txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; + crs = <&pio15 2 ALT2 IN BYPASS 1000>; + col = <&pio15 3 ALT2 IN BYPASS 1000>; + mdio = <&pio15 4 ALT2 OUT BYPASS 3000>; + mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>; + + rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>; + phyclk = <&pio13 5 ALT2 OUT NICLK 1000 CLK_A>; }; }; pinctrl_gmii0: gmii0 { st,pins { - mdint = <&PIO13 6 ALT2 IN BYPASS 0>; - mdio = <&PIO15 4 ALT2 OUT BYPASS 3000>; - mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>; - txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; - - txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; - txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; - txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - txd4 = <&PIO14 4 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - txd5 = <&PIO14 5 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - txd6 = <&PIO14 6 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - txd7 = <&PIO14 7 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; - - txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>; - txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; - crs = <&PIO15 2 ALT2 IN BYPASS 1000>; - col = <&PIO15 3 ALT2 IN BYPASS 1000>; - rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - - rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd4 = <&PIO16 4 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd5 = <&PIO16 5 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd6 = <&PIO16 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - rxd7 = <&PIO16 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>; - - rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>; - clk125 = <&PIO17 6 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&PIO13 5 ALT4 OUT NICLK 0 CLK_B>; + mdint = <&pio13 6 ALT2 IN BYPASS 0>; + mdio = <&pio15 4 ALT2 OUT BYPASS 3000>; + mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>; + txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; + + txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; + txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; + txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; + txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; + txd4 = <&pio14 4 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; + txd5 = <&pio14 5 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; + txd6 = <&pio14 6 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; + txd7 = <&pio14 7 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; + + txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>; + txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; + crs = <&pio15 2 ALT2 IN BYPASS 1000>; + col = <&pio15 3 ALT2 IN BYPASS 1000>; + rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>; + rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>; + + rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 1500 CLK_A>; + rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 1500 CLK_A>; + rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 1500 CLK_A>; + rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 1500 CLK_A>; + rxd4 = <&pio16 4 ALT2 IN SE_NICLK_IO 1500 CLK_A>; + rxd5 = <&pio16 5 ALT2 IN SE_NICLK_IO 1500 CLK_A>; + rxd6 = <&pio16 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>; + rxd7 = <&pio16 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>; + + rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>; + clk125 = <&pio17 6 ALT1 IN NICLK 0 CLK_A>; + phyclk = <&pio13 5 ALT4 OUT NICLK 0 CLK_B>; }; }; }; + + mmc0 { + pinctrl_mmc0: mmc0 { + st,pins { + mmcclk = <&pio13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>; + data0 = <&pio14 4 ALT4 BIDIR_PU BYPASS 0>; + data1 = <&pio14 5 ALT4 BIDIR_PU BYPASS 0>; + data2 = <&pio14 6 ALT4 BIDIR_PU BYPASS 0>; + data3 = <&pio14 7 ALT4 BIDIR_PU BYPASS 0>; + cmd = <&pio15 1 ALT4 BIDIR_PU BYPASS 0>; + wp = <&pio15 3 ALT4 IN>; + data4 = <&pio16 4 ALT4 BIDIR_PU BYPASS 0>; + data5 = <&pio16 5 ALT4 BIDIR_PU BYPASS 0>; + data6 = <&pio16 6 ALT4 BIDIR_PU BYPASS 0>; + data7 = <&pio16 7 ALT4 BIDIR_PU BYPASS 0>; + pwr = <&pio17 1 ALT4 OUT>; + cd = <&pio17 2 ALT4 IN>; + led = <&pio17 3 ALT4 OUT>; + }; + }; + }; }; pin-controller-left { @@ -442,7 +463,7 @@ interrupt-names = "irqmux"; ranges = <0 0xfd6b0000 0x3000>; - PIO100: gpio@fd6b0000 { + pio100: gpio@fd6b0000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -450,7 +471,7 @@ reg = <0 0x100>; st,bank-name = "PIO100"; }; - PIO101: gpio@fd6b1000 { + pio101: gpio@fd6b1000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -458,7 +479,7 @@ reg = <0x1000 0x100>; st,bank-name = "PIO101"; }; - PIO102: gpio@fd6b2000 { + pio102: gpio@fd6b2000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -479,7 +500,7 @@ interrupt-names = "irqmux"; ranges = <0 0xfd330000 0x5000>; - PIO103: gpio@fd330000 { + pio103: gpio@fd330000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -487,7 +508,7 @@ reg = <0 0x100>; st,bank-name = "PIO103"; }; - PIO104: gpio@fd331000 { + pio104: gpio@fd331000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -495,7 +516,7 @@ reg = <0x1000 0x100>; st,bank-name = "PIO104"; }; - PIO105: gpio@fd332000 { + pio105: gpio@fd332000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -503,7 +524,7 @@ reg = <0x2000 0x100>; st,bank-name = "PIO105"; }; - PIO106: gpio@fd333000 { + pio106: gpio@fd333000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -511,7 +532,7 @@ reg = <0x3000 0x100>; st,bank-name = "PIO106"; }; - PIO107: gpio@fd334000 { + pio107: gpio@fd334000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi index a0f6f75fe3b5..9198c12765ea 100644 --- a/arch/arm/boot/dts/stih415.dtsi +++ b/arch/arm/boot/dts/stih415.dtsi @@ -218,5 +218,17 @@ resets = <&powerdown STIH415_KEYSCAN_POWERDOWN>, <&softreset STIH415_KEYSCAN_SOFTRESET>; }; + + mmc0: sdhci@fe81e000 { + compatible = "st,sdhci"; + status = "disabled"; + reg = <0xfe81e000 0x1000>; + interrupts = <GIC_SPI 145 IRQ_TYPE_NONE>; + interrupt-names = "mmcirq"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0>; + clock-names = "mmc"; + clocks = <&clk_s_a1_ls 1>; + }; }; }; diff --git a/arch/arm/boot/dts/stih416-b2020.dts b/arch/arm/boot/dts/stih416-b2020.dts index 4e2df66b99ea..200a81844765 100644 --- a/arch/arm/boot/dts/stih416-b2020.dts +++ b/arch/arm/boot/dts/stih416-b2020.dts @@ -12,4 +12,26 @@ / { model = "STiH416 B2020"; compatible = "st,stih416-b2020", "st,stih416"; + + soc { + mmc1: sdhci@fe81f000 { + status = "okay"; + bus-width = <8>; + non-removable; + }; + + miphy365x_phy: phy@fe382000 { + phy_port0: port@fe382000 { + st,sata-gen = <3>; + }; + + phy_port1: port@fe38a000 { + st,pcie-tx-pol-inv; + }; + }; + + sata0: sata@fe380000{ + status = "okay"; + }; + }; }; diff --git a/arch/arm/boot/dts/stih416-b2020e.dts b/arch/arm/boot/dts/stih416-b2020e.dts index ba0fa2caaf18..961799e1dc51 100644 --- a/arch/arm/boot/dts/stih416-b2020e.dts +++ b/arch/arm/boot/dts/stih416-b2020e.dts @@ -19,17 +19,37 @@ red { #gpio-cells = <1>; label = "Front Panel LED"; - gpios = <&PIO4 1>; + gpios = <&pio4 1>; linux,default-trigger = "heartbeat"; }; green { - gpios = <&PIO1 3>; + gpios = <&pio1 3>; default-state = "off"; }; }; ethernet1: dwmac@fef08000 { - snps,reset-gpio = <&PIO0 7>; + snps,reset-gpio = <&pio0 7>; + }; + + mmc1: sdhci@fe81f000 { + status = "okay"; + bus-width = <8>; + non-removable; + }; + + miphy365x_phy: phy@fe382000 { + phy_port0: port@fe382000 { + st,sata-gen = <3>; + }; + + phy_port1: port@fe38a000 { + st,pcie-tx-pol-inv; + }; + }; + + sata0: sata@fe380000{ + status = "okay"; }; }; }; diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi index ee6c119e261e..9cccf2d6aa26 100644 --- a/arch/arm/boot/dts/stih416-pinctrl.dtsi +++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi @@ -12,36 +12,36 @@ / { aliases { - gpio0 = &PIO0; - gpio1 = &PIO1; - gpio2 = &PIO2; - gpio3 = &PIO3; - gpio4 = &PIO4; - gpio5 = &PIO40; - gpio6 = &PIO5; - gpio7 = &PIO6; - gpio8 = &PIO7; - gpio9 = &PIO8; - gpio10 = &PIO9; - gpio11 = &PIO10; - gpio12 = &PIO11; - gpio13 = &PIO12; - gpio14 = &PIO30; - gpio15 = &PIO31; - gpio16 = &PIO13; - gpio17 = &PIO14; - gpio18 = &PIO15; - gpio19 = &PIO16; - gpio20 = &PIO17; - gpio21 = &PIO18; - gpio22 = &PIO100; - gpio23 = &PIO101; - gpio24 = &PIO102; - gpio25 = &PIO103; - gpio26 = &PIO104; - gpio27 = &PIO105; - gpio28 = &PIO106; - gpio29 = &PIO107; + gpio0 = &pio0; + gpio1 = &pio1; + gpio2 = &pio2; + gpio3 = &pio3; + gpio4 = &pio4; + gpio5 = &pio40; + gpio6 = &pio5; + gpio7 = &pio6; + gpio8 = &pio7; + gpio9 = &pio8; + gpio10 = &pio9; + gpio11 = &pio10; + gpio12 = &pio11; + gpio13 = &pio12; + gpio14 = &pio30; + gpio15 = &pio31; + gpio16 = &pio13; + gpio17 = &pio14; + gpio18 = &pio15; + gpio19 = &pio16; + gpio20 = &pio17; + gpio21 = &pio18; + gpio22 = &pio100; + gpio23 = &pio101; + gpio24 = &pio102; + gpio25 = &pio103; + gpio26 = &pio104; + gpio27 = &pio105; + gpio28 = &pio106; + gpio29 = &pio107; }; soc { @@ -56,7 +56,7 @@ interrupt-names = "irqmux"; ranges = <0 0xfe610000 0x6000>; - PIO0: gpio@fe610000 { + pio0: gpio@fe610000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -64,7 +64,7 @@ reg = <0 0x100>; st,bank-name = "PIO0"; }; - PIO1: gpio@fe611000 { + pio1: gpio@fe611000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -72,7 +72,7 @@ reg = <0x1000 0x100>; st,bank-name = "PIO1"; }; - PIO2: gpio@fe612000 { + pio2: gpio@fe612000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -80,7 +80,7 @@ reg = <0x2000 0x100>; st,bank-name = "PIO2"; }; - PIO3: gpio@fe613000 { + pio3: gpio@fe613000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -88,7 +88,7 @@ reg = <0x3000 0x100>; st,bank-name = "PIO3"; }; - PIO4: gpio@fe614000 { + pio4: gpio@fe614000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -96,7 +96,7 @@ reg = <0x4000 0x100>; st,bank-name = "PIO4"; }; - PIO40: gpio@fe615000 { + pio40: gpio@fe615000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -109,15 +109,15 @@ rc{ pinctrl_ir: ir0 { st,pins { - ir = <&PIO4 0 ALT2 IN>; + ir = <&pio4 0 ALT2 IN>; }; }; }; sbc_serial1 { pinctrl_sbc_serial1: sbc_serial1 { st,pins { - tx = <&PIO2 6 ALT3 OUT>; - rx = <&PIO2 7 ALT3 IN>; + tx = <&pio2 6 ALT3 OUT>; + rx = <&pio2 7 ALT3 IN>; }; }; }; @@ -125,15 +125,15 @@ keyscan { pinctrl_keyscan: keyscan { st,pins { - keyin0 = <&PIO0 2 ALT2 IN>; - keyin1 = <&PIO0 3 ALT2 IN>; - keyin2 = <&PIO0 4 ALT2 IN>; - keyin3 = <&PIO2 6 ALT2 IN>; - - keyout0 = <&PIO1 6 ALT2 OUT>; - keyout1 = <&PIO1 7 ALT2 OUT>; - keyout2 = <&PIO0 6 ALT2 OUT>; - keyout3 = <&PIO2 7 ALT2 OUT>; + keyin0 = <&pio0 2 ALT2 IN>; + keyin1 = <&pio0 3 ALT2 IN>; + keyin2 = <&pio0 4 ALT2 IN>; + keyin3 = <&pio2 6 ALT2 IN>; + + keyout0 = <&pio1 6 ALT2 OUT>; + keyout1 = <&pio1 7 ALT2 OUT>; + keyout2 = <&pio0 6 ALT2 OUT>; + keyout3 = <&pio2 7 ALT2 OUT>; }; }; }; @@ -141,8 +141,17 @@ sbc_i2c0 { pinctrl_sbc_i2c0_default: sbc_i2c0-default { st,pins { - sda = <&PIO4 6 ALT1 BIDIR>; - scl = <&PIO4 5 ALT1 BIDIR>; + sda = <&pio4 6 ALT1 BIDIR>; + scl = <&pio4 5 ALT1 BIDIR>; + }; + }; + }; + + usb { + pinctrl_usb3: usb3 { + st,pins { + oc-detect = <&pio40 0 ALT1 IN>; + pwr-enable = <&pio40 1 ALT1 OUT>; }; }; }; @@ -150,8 +159,8 @@ sbc_i2c1 { pinctrl_sbc_i2c1_default: sbc_i2c1-default { st,pins { - sda = <&PIO3 2 ALT2 BIDIR>; - scl = <&PIO3 1 ALT2 BIDIR>; + sda = <&pio3 2 ALT2 BIDIR>; + scl = <&pio3 1 ALT2 BIDIR>; }; }; }; @@ -159,51 +168,51 @@ gmac1 { pinctrl_mii1: mii1 { st,pins { - txd0 = <&PIO0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd1 = <&PIO0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd2 = <&PIO0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txd3 = <&PIO0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txer = <&PIO0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txen = <&PIO0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; - txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>; - col = <&PIO0 7 ALT1 IN BYPASS 1000>; - - mdio = <&PIO1 0 ALT1 OUT BYPASS 1500>; - mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>; - crs = <&PIO1 2 ALT1 IN BYPASS 1000>; - mdint = <&PIO1 3 ALT1 IN BYPASS 0>; - rxd0 = <&PIO1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd1 = <&PIO1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd2 = <&PIO1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxd3 = <&PIO1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; - - rxdv = <&PIO2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rx_er = <&PIO2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; - rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&PIO2 3 ALT1 OUT NICLK 0 CLK_A>; + txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; + txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; + col = <&pio0 7 ALT1 IN BYPASS 1000>; + + mdio = <&pio1 0 ALT1 OUT BYPASS 1500>; + mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; + crs = <&pio1 2 ALT1 IN BYPASS 1000>; + mdint = <&pio1 3 ALT1 IN BYPASS 0>; + rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; + + rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; + rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; + phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>; }; }; pinctrl_rgmii1: rgmii1-0 { st,pins { - txd0 = <&PIO0 0 ALT1 OUT DE_IO 500 CLK_A>; - txd1 = <&PIO0 1 ALT1 OUT DE_IO 500 CLK_A>; - txd2 = <&PIO0 2 ALT1 OUT DE_IO 500 CLK_A>; - txd3 = <&PIO0 3 ALT1 OUT DE_IO 500 CLK_A>; - txen = <&PIO0 5 ALT1 OUT DE_IO 0 CLK_A>; - txclk = <&PIO0 6 ALT1 IN NICLK 0 CLK_A>; - - mdio = <&PIO1 0 ALT1 OUT BYPASS 0>; - mdc = <&PIO1 1 ALT1 OUT NICLK 0 CLK_A>; - rxd0 = <&PIO1 4 ALT1 IN DE_IO 500 CLK_A>; - rxd1 = <&PIO1 5 ALT1 IN DE_IO 500 CLK_A>; - rxd2 = <&PIO1 6 ALT1 IN DE_IO 500 CLK_A>; - rxd3 = <&PIO1 7 ALT1 IN DE_IO 500 CLK_A>; - - rxdv = <&PIO2 0 ALT1 IN DE_IO 500 CLK_A>; - rxclk = <&PIO2 2 ALT1 IN NICLK 0 CLK_A>; - phyclk = <&PIO2 3 ALT4 OUT NICLK 0 CLK_B>; - - clk125= <&PIO3 7 ALT4 IN NICLK 0 CLK_A>; + txd0 = <&pio0 0 ALT1 OUT DE_IO 500 CLK_A>; + txd1 = <&pio0 1 ALT1 OUT DE_IO 500 CLK_A>; + txd2 = <&pio0 2 ALT1 OUT DE_IO 500 CLK_A>; + txd3 = <&pio0 3 ALT1 OUT DE_IO 500 CLK_A>; + txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>; + txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; + + mdio = <&pio1 0 ALT1 OUT BYPASS 0>; + mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; + rxd0 = <&pio1 4 ALT1 IN DE_IO 500 CLK_A>; + rxd1 = <&pio1 5 ALT1 IN DE_IO 500 CLK_A>; + rxd2 = <&pio1 6 ALT1 IN DE_IO 500 CLK_A>; + rxd3 = <&pio1 7 ALT1 IN DE_IO 500 CLK_A>; + + rxdv = <&pio2 0 ALT1 IN DE_IO 500 CLK_A>; + rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; + phyclk = <&pio2 3 ALT4 OUT NICLK 0 CLK_B>; + + clk125= <&pio3 7 ALT4 IN NICLK 0 CLK_A>; }; }; }; @@ -220,7 +229,7 @@ interrupt-names = "irqmux"; ranges = <0 0xfee00000 0x10000>; - PIO5: gpio@fee00000 { + pio5: gpio@fee00000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -228,7 +237,7 @@ reg = <0 0x100>; st,bank-name = "PIO5"; }; - PIO6: gpio@fee01000 { + pio6: gpio@fee01000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -236,7 +245,7 @@ reg = <0x1000 0x100>; st,bank-name = "PIO6"; }; - PIO7: gpio@fee02000 { + pio7: gpio@fee02000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -244,7 +253,7 @@ reg = <0x2000 0x100>; st,bank-name = "PIO7"; }; - PIO8: gpio@fee03000 { + pio8: gpio@fee03000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -252,7 +261,7 @@ reg = <0x3000 0x100>; st,bank-name = "PIO8"; }; - PIO9: gpio@fee04000 { + pio9: gpio@fee04000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -260,7 +269,7 @@ reg = <0x4000 0x100>; st,bank-name = "PIO9"; }; - PIO10: gpio@fee05000 { + pio10: gpio@fee05000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -268,7 +277,7 @@ reg = <0x5000 0x100>; st,bank-name = "PIO10"; }; - PIO11: gpio@fee06000 { + pio11: gpio@fee06000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -276,7 +285,7 @@ reg = <0x6000 0x100>; st,bank-name = "PIO11"; }; - PIO12: gpio@fee07000 { + pio12: gpio@fee07000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -284,7 +293,7 @@ reg = <0x7000 0x100>; st,bank-name = "PIO12"; }; - PIO30: gpio@fee08000 { + pio30: gpio@fee08000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -292,7 +301,7 @@ reg = <0x8000 0x100>; st,bank-name = "PIO30"; }; - PIO31: gpio@fee09000 { + pio31: gpio@fee09000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -304,7 +313,7 @@ serial2-oe { pinctrl_serial2_oe: serial2-1 { st,pins { - output-enable = <&PIO11 3 ALT2 OUT>; + output-enable = <&pio11 3 ALT2 OUT>; }; }; }; @@ -312,17 +321,27 @@ i2c0 { pinctrl_i2c0_default: i2c0-default { st,pins { - sda = <&PIO9 3 ALT1 BIDIR>; - scl = <&PIO9 2 ALT1 BIDIR>; + sda = <&pio9 3 ALT1 BIDIR>; + scl = <&pio9 2 ALT1 BIDIR>; + }; + }; + }; + + usb { + pinctrl_usb0: usb0 { + st,pins { + oc-detect = <&pio9 4 ALT1 IN>; + pwr-enable = <&pio9 5 ALT1 OUT>; }; }; }; + i2c1 { pinctrl_i2c1_default: i2c1-default { st,pins { - sda = <&PIO12 1 ALT1 BIDIR>; - scl = <&PIO12 0 ALT1 BIDIR>; + sda = <&pio12 1 ALT1 BIDIR>; + scl = <&pio12 0 ALT1 BIDIR>; }; }; }; @@ -330,12 +349,12 @@ fsm { pinctrl_fsm: fsm { st,pins { - spi-fsm-clk = <&PIO12 2 ALT1 OUT>; - spi-fsm-cs = <&PIO12 3 ALT1 OUT>; - spi-fsm-mosi = <&PIO12 4 ALT1 OUT>; - spi-fsm-miso = <&PIO12 5 ALT1 IN>; - spi-fsm-hol = <&PIO12 6 ALT1 OUT>; - spi-fsm-wp = <&PIO12 7 ALT1 OUT>; + spi-fsm-clk = <&pio12 2 ALT1 OUT>; + spi-fsm-cs = <&pio12 3 ALT1 OUT>; + spi-fsm-mosi = <&pio12 4 ALT1 OUT>; + spi-fsm-miso = <&pio12 5 ALT1 IN>; + spi-fsm-hol = <&pio12 6 ALT1 OUT>; + spi-fsm-wp = <&pio12 7 ALT1 OUT>; }; }; }; @@ -352,7 +371,7 @@ interrupt-names = "irqmux"; ranges = <0 0xfe820000 0x6000>; - PIO13: gpio@fe820000 { + pio13: gpio@fe820000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -360,7 +379,7 @@ reg = <0 0x100>; st,bank-name = "PIO13"; }; - PIO14: gpio@fe821000 { + pio14: gpio@fe821000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -368,7 +387,7 @@ reg = <0x1000 0x100>; st,bank-name = "PIO14"; }; - PIO15: gpio@fe822000 { + pio15: gpio@fe822000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -376,7 +395,7 @@ reg = <0x2000 0x100>; st,bank-name = "PIO15"; }; - PIO16: gpio@fe823000 { + pio16: gpio@fe823000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -384,7 +403,7 @@ reg = <0x3000 0x100>; st,bank-name = "PIO16"; }; - PIO17: gpio@fe824000 { + pio17: gpio@fe824000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -392,7 +411,7 @@ reg = <0x4000 0x100>; st,bank-name = "PIO17"; }; - PIO18: gpio@fe825000 { + pio18: gpio@fe825000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -405,8 +424,8 @@ serial2 { pinctrl_serial2: serial2-0 { st,pins { - tx = <&PIO17 4 ALT2 OUT>; - rx = <&PIO17 5 ALT2 IN>; + tx = <&pio17 4 ALT2 OUT>; + rx = <&pio17 5 ALT2 IN>; }; }; }; @@ -414,28 +433,28 @@ gmac0 { pinctrl_mii0: mii0 { st,pins { - mdint = <&PIO13 6 ALT2 IN BYPASS 0>; - txen = <&PIO13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - txd0 = <&PIO14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - txd1 = <&PIO14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - txd2 = <&PIO14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>; - txd3 = <&PIO14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>; - - txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>; - txer = <&PIO15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; - crs = <&PIO15 2 ALT2 IN BYPASS 1000>; - col = <&PIO15 3 ALT2 IN BYPASS 1000>; - mdio= <&PIO15 4 ALT2 OUT BYPASS 1500>; - mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>; - - rxd0 = <&PIO16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd1 = <&PIO16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd2 = <&PIO16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxd3 = <&PIO16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxdv = <&PIO15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rx_er = <&PIO15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>; - rxclk = <&PIO17 0 ALT2 IN NICLK 0 CLK_A>; - phyclk = <&PIO13 5 ALT2 OUT NICLK 0 CLK_B>; + mdint = <&pio13 6 ALT2 IN BYPASS 0>; + txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; + txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; + txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; + txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>; + txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>; + + txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>; + txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; + crs = <&pio15 2 ALT2 IN BYPASS 1000>; + col = <&pio15 3 ALT2 IN BYPASS 1000>; + mdio= <&pio15 4 ALT2 OUT BYPASS 1500>; + mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>; + + rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>; + rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>; + phyclk = <&pio13 5 ALT2 OUT NICLK 0 CLK_B>; }; }; @@ -445,25 +464,79 @@ }; pinctrl_rgmii0: rgmii0 { st,pins { - phyclk = <&PIO13 5 ALT4 OUT NICLK 0 CLK_B>; - txen = <&PIO13 7 ALT2 OUT DE_IO 0 CLK_A>; - txd0 = <&PIO14 0 ALT2 OUT DE_IO 500 CLK_A>; - txd1 = <&PIO14 1 ALT2 OUT DE_IO 500 CLK_A>; - txd2 = <&PIO14 2 ALT2 OUT DE_IO 500 CLK_B>; - txd3 = <&PIO14 3 ALT2 OUT DE_IO 500 CLK_B>; - txclk = <&PIO15 0 ALT2 IN NICLK 0 CLK_A>; - - mdio = <&PIO15 4 ALT2 OUT BYPASS 0>; - mdc = <&PIO15 5 ALT2 OUT NICLK 0 CLK_B>; - - rxdv = <&PIO15 6 ALT2 IN DE_IO 500 CLK_A>; - rxd0 =<&PIO16 0 ALT2 IN DE_IO 500 CLK_A>; - rxd1 =<&PIO16 1 ALT2 IN DE_IO 500 CLK_A>; - rxd2 =<&PIO16 2 ALT2 IN DE_IO 500 CLK_A>; - rxd3 =<&PIO16 3 ALT2 IN DE_IO 500 CLK_A>; - rxclk =<&PIO17 0 ALT2 IN NICLK 0 CLK_A>; - - clk125=<&PIO17 6 ALT1 IN NICLK 0 CLK_A>; + phyclk = <&pio13 5 ALT4 OUT NICLK 0 CLK_B>; + txen = <&pio13 7 ALT2 OUT DE_IO 0 CLK_A>; + txd0 = <&pio14 0 ALT2 OUT DE_IO 500 CLK_A>; + txd1 = <&pio14 1 ALT2 OUT DE_IO 500 CLK_A>; + txd2 = <&pio14 2 ALT2 OUT DE_IO 500 CLK_B>; + txd3 = <&pio14 3 ALT2 OUT DE_IO 500 CLK_B>; + txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>; + + mdio = <&pio15 4 ALT2 OUT BYPASS 0>; + mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>; + + rxdv = <&pio15 6 ALT2 IN DE_IO 500 CLK_A>; + rxd0 =<&pio16 0 ALT2 IN DE_IO 500 CLK_A>; + rxd1 =<&pio16 1 ALT2 IN DE_IO 500 CLK_A>; + rxd2 =<&pio16 2 ALT2 IN DE_IO 500 CLK_A>; + rxd3 =<&pio16 3 ALT2 IN DE_IO 500 CLK_A>; + rxclk =<&pio17 0 ALT2 IN NICLK 0 CLK_A>; + + clk125=<&pio17 6 ALT1 IN NICLK 0 CLK_A>; + }; + }; + }; + + mmc0 { + pinctrl_mmc0: mmc0 { + st,pins { + mmcclk = <&pio13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>; + data0 = <&pio14 4 ALT4 BIDIR_PU BYPASS 0>; + data1 = <&pio14 5 ALT4 BIDIR_PU BYPASS 0>; + data2 = <&pio14 6 ALT4 BIDIR_PU BYPASS 0>; + data3 = <&pio14 7 ALT4 BIDIR_PU BYPASS 0>; + cmd = <&pio15 1 ALT4 BIDIR_PU BYPASS 0>; + wp = <&pio15 3 ALT4 IN>; + data4 = <&pio16 4 ALT4 BIDIR_PU BYPASS 0>; + data5 = <&pio16 5 ALT4 BIDIR_PU BYPASS 0>; + data6 = <&pio16 6 ALT4 BIDIR_PU BYPASS 0>; + data7 = <&pio16 7 ALT4 BIDIR_PU BYPASS 0>; + pwr = <&pio17 1 ALT4 OUT>; + cd = <&pio17 2 ALT4 IN>; + led = <&pio17 3 ALT4 OUT>; + }; + }; + }; + mmc1 { + pinctrl_mmc1: mmc1 { + st,pins { + mmcclk = <&pio15 0 ALT3 BIDIR_PU NICLK 0 CLK_B>; + data0 = <&pio13 7 ALT3 BIDIR_PU BYPASS 0>; + data1 = <&pio14 1 ALT3 BIDIR_PU BYPASS 0>; + data2 = <&pio14 2 ALT3 BIDIR_PU BYPASS 0>; + data3 = <&pio14 3 ALT3 BIDIR_PU BYPASS 0>; + cmd = <&pio15 4 ALT3 BIDIR_PU BYPASS 0>; + data4 = <&pio15 6 ALT3 BIDIR_PU BYPASS 0>; + data5 = <&pio15 7 ALT3 BIDIR_PU BYPASS 0>; + data6 = <&pio16 0 ALT3 BIDIR_PU BYPASS 0>; + data7 = <&pio16 1 ALT3 BIDIR_PU BYPASS 0>; + pwr = <&pio16 2 ALT3 OUT>; + nreset = <&pio13 6 ALT3 OUT>; + }; + }; + }; + + usb { + pinctrl_usb1: usb1 { + st,pins { + oc-detect = <&pio18 0 ALT1 IN>; + pwr-enable = <&pio18 1 ALT1 OUT>; + }; + }; + pinctrl_usb2: usb2 { + st,pins { + oc-detect = <&pio18 2 ALT1 IN>; + pwr-enable = <&pio18 3 ALT1 OUT>; }; }; }; @@ -480,7 +553,7 @@ interrupt-names = "irqmux"; ranges = <0 0xfd6b0000 0x3000>; - PIO100: gpio@fd6b0000 { + pio100: gpio@fd6b0000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -488,7 +561,7 @@ reg = <0 0x100>; st,bank-name = "PIO100"; }; - PIO101: gpio@fd6b1000 { + pio101: gpio@fd6b1000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -496,7 +569,7 @@ reg = <0x1000 0x100>; st,bank-name = "PIO101"; }; - PIO102: gpio@fd6b2000 { + pio102: gpio@fd6b2000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -517,7 +590,7 @@ interrupt-names = "irqmux"; ranges = <0 0xfd330000 0x5000>; - PIO103: gpio@fd330000 { + pio103: gpio@fd330000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -525,7 +598,7 @@ reg = <0 0x100>; st,bank-name = "PIO103"; }; - PIO104: gpio@fd331000 { + pio104: gpio@fd331000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -533,7 +606,7 @@ reg = <0x1000 0x100>; st,bank-name = "PIO104"; }; - PIO105: gpio@fd332000 { + pio105: gpio@fd332000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -541,7 +614,7 @@ reg = <0x2000 0x100>; st,bank-name = "PIO105"; }; - PIO106: gpio@fd333000 { + pio106: gpio@fd333000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; @@ -550,7 +623,7 @@ st,bank-name = "PIO106"; }; - PIO107: gpio@fd334000 { + pio107: gpio@fd334000 { gpio-controller; #gpio-cells = <1>; interrupt-controller; diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi index 84758d76d064..fad9073ddeed 100644 --- a/arch/arm/boot/dts/stih416.dtsi +++ b/arch/arm/boot/dts/stih416.dtsi @@ -9,6 +9,8 @@ #include "stih41x.dtsi" #include "stih416-clock.dtsi" #include "stih416-pinctrl.dtsi" + +#include <dt-bindings/phy/phy-miphy365x.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/reset-controller/stih416-resets.h> / { @@ -236,5 +238,212 @@ resets = <&powerdown STIH416_KEYSCAN_POWERDOWN>, <&softreset STIH416_KEYSCAN_SOFTRESET>; }; + + temp0 { + compatible = "st,stih416-sas-thermal"; + clock-names = "thermal"; + clocks = <&clockgen_c_vcc 14>; + + status = "okay"; + }; + + temp1@fdfe8000 { + compatible = "st,stih416-mpe-thermal"; + reg = <0xfdfe8000 0x10>; + clocks = <&clockgen_e 3>; + clock-names = "thermal"; + interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>; + + status = "okay"; + }; + + mmc0: sdhci@fe81e000 { + compatible = "st,sdhci"; + status = "disabled"; + reg = <0xfe81e000 0x1000>; + interrupts = <GIC_SPI 127 IRQ_TYPE_NONE>; + interrupt-names = "mmcirq"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc0>; + clock-names = "mmc"; + clocks = <&clk_s_a1_ls 1>; + }; + + mmc1: sdhci@fe81f000 { + compatible = "st,sdhci"; + status = "disabled"; + reg = <0xfe81f000 0x1000>; + interrupts = <GIC_SPI 128 IRQ_TYPE_NONE>; + interrupt-names = "mmcirq"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mmc1>; + clock-names = "mmc"; + clocks = <&clk_s_a1_ls 8>; + }; + + miphy365x_phy: phy@fe382000 { + compatible = "st,miphy365x-phy"; + st,syscfg = <&syscfg_rear>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + phy_port0: port@fe382000 { + #phy-cells = <1>; + reg = <0xfe382000 0x100>, <0xfe394000 0x100>, <0x824 0x4>; + reg-names = "sata", "pcie", "syscfg"; + }; + + phy_port1: port@fe38a000 { + #phy-cells = <1>; + reg = <0xfe38a000 0x100>, <0xfe804000 0x100>, <0x828 0x4>; + reg-names = "sata", "pcie", "syscfg"; + }; + }; + + sata0: sata@fe380000 { + compatible = "st,sti-ahci"; + reg = <0xfe380000 0x1000>; + interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>; + interrupt-names = "hostc"; + phys = <&phy_port0 MIPHY_TYPE_SATA>; + phy-names = "sata-phy"; + resets = <&powerdown STIH416_SATA0_POWERDOWN>, + <&softreset STIH416_SATA0_SOFTRESET>; + reset-names = "pwr-dwn", "sw-rst"; + clock-names = "ahci_clk"; + clocks = <&clk_s_a0_ls CLK_ICN_REG>; + + status = "disabled"; + }; + + usb2_phy: phy@0 { + compatible = "st,stih416-usb-phy"; + #phy-cells = <0>; + st,syscfg = <&syscfg_rear>; + clocks = <&clk_sysin>; + clock-names = "osc_phy"; + }; + + ehci0: usb@fe1ffe00 { + compatible = "st,st-ehci-300x"; + reg = <0xfe1ffe00 0x100>; + interrupts = <GIC_SPI 148 IRQ_TYPE_NONE>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; + clocks = <&clk_s_a1_ls 0>, + <&clockgen_b0 0>; + clock-names = "ic", "clk48"; + phys = <&usb2_phy>; + phy-names = "usb"; + resets = <&powerdown STIH416_USB0_POWERDOWN>, + <&softreset STIH416_USB0_SOFTRESET>; + reset-names = "power", "softreset"; + }; + + ohci0: usb@fe1ffc00 { + compatible = "st,st-ohci-300x"; + reg = <0xfe1ffc00 0x100>; + interrupts = <GIC_SPI 149 IRQ_TYPE_NONE>; + clocks = <&clk_s_a1_ls 0>, + <&clockgen_b0 0>; + clock-names = "ic", "clk48"; + phys = <&usb2_phy>; + phy-names = "usb"; + status = "okay"; + resets = <&powerdown STIH416_USB0_POWERDOWN>, + <&softreset STIH416_USB0_SOFTRESET>; + reset-names = "power", "softreset"; + }; + + ehci1: usb@fe203e00 { + compatible = "st,st-ehci-300x"; + reg = <0xfe203e00 0x100>; + interrupts = <GIC_SPI 150 IRQ_TYPE_NONE>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; + clocks = <&clk_s_a1_ls 0>, + <&clockgen_b0 0>; + clock-names = "ic", "clk48"; + phys = <&usb2_phy>; + phy-names = "usb"; + resets = <&powerdown STIH416_USB1_POWERDOWN>, + <&softreset STIH416_USB1_SOFTRESET>; + reset-names = "power", "softreset"; + }; + + ohci1: usb@fe203c00 { + compatible = "st,st-ohci-300x"; + reg = <0xfe203c00 0x100>; + interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>; + clocks = <&clk_s_a1_ls 0>, + <&clockgen_b0 0>; + clock-names = "ic", "clk48"; + phys = <&usb2_phy>; + phy-names = "usb"; + resets = <&powerdown STIH416_USB1_POWERDOWN>, + <&softreset STIH416_USB1_SOFTRESET>; + reset-names = "power", "softreset"; + }; + + ehci2: usb@fe303e00 { + compatible = "st,st-ehci-300x"; + reg = <0xfe303e00 0x100>; + interrupts = <GIC_SPI 152 IRQ_TYPE_NONE>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; + clocks = <&clk_s_a1_ls 0>, + <&clockgen_b0 0>; + clock-names = "ic", "clk48"; + phys = <&usb2_phy>; + phy-names = "usb"; + resets = <&powerdown STIH416_USB2_POWERDOWN>, + <&softreset STIH416_USB2_SOFTRESET>; + reset-names = "power", "softreset"; + }; + + ohci2: usb@fe303c00 { + compatible = "st,st-ohci-300x"; + reg = <0xfe303c00 0x100>; + interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>; + clocks = <&clk_s_a1_ls 0>, + <&clockgen_b0 0>; + clock-names = "ic", "clk48"; + phys = <&usb2_phy>; + phy-names = "usb"; + resets = <&powerdown STIH416_USB2_POWERDOWN>, + <&softreset STIH416_USB2_SOFTRESET>; + reset-names = "power", "softreset"; + }; + + ehci3: usb@fe343e00 { + compatible = "st,st-ehci-300x"; + reg = <0xfe343e00 0x100>; + interrupts = <GIC_SPI 154 IRQ_TYPE_NONE>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3>; + clocks = <&clk_s_a1_ls 0>, + <&clockgen_b0 0>; + clock-names = "ic", "clk48"; + phys = <&usb2_phy>; + phy-names = "usb"; + resets = <&powerdown STIH416_USB3_POWERDOWN>, + <&softreset STIH416_USB3_SOFTRESET>; + reset-names = "power", "softreset"; + }; + + ohci3: usb@fe343c00 { + compatible = "st,st-ohci-300x"; + reg = <0xfe343c00 0x100>; + interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>; + clocks = <&clk_s_a1_ls 0>, + <&clockgen_b0 0>; + clock-names = "ic", "clk48"; + phys = <&usb2_phy>; + phy-names = "usb"; + resets = <&powerdown STIH416_USB3_POWERDOWN>, + <&softreset STIH416_USB3_SOFTRESET>; + reset-names = "power", "softreset"; + }; }; }; diff --git a/arch/arm/boot/dts/stih41x-b2000.dtsi b/arch/arm/boot/dts/stih41x-b2000.dtsi index b3dd6ca5c2ae..5f91f455f05b 100644 --- a/arch/arm/boot/dts/stih41x-b2000.dtsi +++ b/arch/arm/boot/dts/stih41x-b2000.dtsi @@ -35,7 +35,7 @@ fp_led { #gpio-cells = <1>; label = "Front Panel LED"; - gpios = <&PIO105 7>; + gpios = <&pio105 7>; linux,default-trigger = "heartbeat"; }; }; @@ -55,7 +55,7 @@ phy-mode = "mii"; pinctrl-0 = <&pinctrl_mii0>; - snps,reset-gpio = <&PIO106 2>; + snps,reset-gpio = <&pio106 2>; snps,reset-active-low; snps,reset-delays-us = <0 10000 10000>; }; @@ -65,7 +65,7 @@ phy-mode = "mii"; st,tx-retime-src = "txclk"; - snps,reset-gpio = <&PIO4 7>; + snps,reset-gpio = <&pio4 7>; snps,reset-active-low; snps,reset-delays-us = <0 10000 10000>; }; diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi index d8a84295c328..487d7d87dbef 100644 --- a/arch/arm/boot/dts/stih41x-b2020.dtsi +++ b/arch/arm/boot/dts/stih41x-b2020.dtsi @@ -32,11 +32,11 @@ red { #gpio-cells = <1>; label = "Front Panel LED"; - gpios = <&PIO4 1>; + gpios = <&pio4 1>; linux,default-trigger = "heartbeat"; }; green { - gpios = <&PIO4 7>; + gpios = <&pio4 7>; default-state = "off"; }; }; @@ -68,11 +68,15 @@ phy-mode = "rgmii-id"; max-speed = <1000>; st,tx-retime-src = "clk_125"; - snps,reset-gpio = <&PIO3 0>; + snps,reset-gpio = <&pio3 0>; snps,reset-active-low; snps,reset-delays-us = <0 10000 10000>; pinctrl-0 = <&pinctrl_rgmii1>; }; + + mmc0: sdhci@fe81e000 { + bus-width = <8>; + }; }; }; diff --git a/arch/arm/boot/dts/stih41x-b2020x.dtsi b/arch/arm/boot/dts/stih41x-b2020x.dtsi index df01c1211b32..f797a0607382 100644 --- a/arch/arm/boot/dts/stih41x-b2020x.dtsi +++ b/arch/arm/boot/dts/stih41x-b2020x.dtsi @@ -8,6 +8,10 @@ */ / { soc { + mmc0: sdhci@fe81e000 { + status = "okay"; + }; + spifsm: spifsm@fe902000 { #address-cells = <1>; #size-cells = <1>; diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi new file mode 100644 index 000000000000..0074bd49797c --- /dev/null +++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2014 STMicroelectronics (R&D) Limited. + * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/ { + soc { + sbc_serial0: serial@9530000 { + status = "okay"; + }; + + leds { + compatible = "gpio-leds"; + red { + #gpio-cells = <2>; + label = "Front Panel LED"; + gpios = <&pio4 1 0>; + linux,default-trigger = "heartbeat"; + }; + green { + #gpio-cells = <2>; + gpios = <&pio1 3 0>; + default-state = "off"; + }; + }; + + i2c@9842000 { + status = "okay"; + }; + + i2c@9843000 { + status = "okay"; + }; + + i2c@9844000 { + status = "okay"; + }; + + i2c@9845000 { + status = "okay"; + }; + + i2c@9540000 { + status = "okay"; + }; + + /* SSC11 to HDMI */ + i2c@9541000 { + status = "okay"; + /* HDMI V1.3a supports Standard mode only */ + clock-frequency = <100000>; + st,i2c-min-scl-pulse-width-us = <0>; + st,i2c-min-sda-pulse-width-us = <5>; + }; + }; +}; diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts index 9e99ade35e37..3bcfd81837f0 100644 --- a/arch/arm/boot/dts/sun4i-a10-a1000.dts +++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts @@ -3,12 +3,48 @@ * * Emilio López <emilio@elopez.com.ar> * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts index 1763cc7ec023..f3f2974658e4 100644 --- a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts +++ b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts @@ -1,12 +1,48 @@ /* * Copyright 2014 Hans de Goede <hdegoede@redhat.com> * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts index 3ce56bfbc0b5..6a310da53f18 100644 --- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts +++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts @@ -2,12 +2,48 @@ * Copyright 2012 Stefan Roese * Stefan Roese <sr@denx.de> * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts index 891ea446abae..efc116287e0f 100644 --- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts +++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts @@ -3,12 +3,48 @@ * * Maxime Ripard <maxime.ripard@free-electrons.com> * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts index 6b0c37812ade..3e25ee4d3248 100644 --- a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts +++ b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts @@ -3,12 +3,48 @@ * * David Lanzendörfer <david.lanzendoerfer@o2s.ch> * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts index b9ecce60f2e7..8b3f97470249 100644 --- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts +++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts @@ -3,12 +3,48 @@ * * Maxime Ripard <maxime.ripard@free-electrons.com> * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts index d046d568f5a1..88cf1a531155 100644 --- a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts +++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts @@ -1,12 +1,48 @@ /* * Copyright 2014 - Hans de Goede <hdegoede@redhat.com> * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts index 6675bcd7860e..ce5994597407 100644 --- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts +++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts @@ -2,12 +2,48 @@ * Copyright 2014 Zoltan HERPAI * Zoltan HERPAI <wigyori@uid0.hu> * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 459cb6377764..7b4099fcf817 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -27,6 +27,20 @@ serial7 = &uart7; }; + chosen { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + framebuffer@0 { + compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; + allwinner,pipeline = "de_be0-lcd0-hdmi"; + clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, + <&ahb_gates 44>; + status = "disabled"; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -174,19 +188,11 @@ "apb0_ir1", "apb0_keypad"; }; - apb1_mux: apb1_mux@01c20058 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb1-mux-clk"; - reg = <0x01c20058 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&osc32k>; - clock-output-names = "apb1_mux"; - }; - - apb1: apb1@01c20058 { + apb1: clk@01c20058 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-apb1-clk"; reg = <0x01c20058 0x4>; - clocks = <&apb1_mux>; + clocks = <&osc24M>, <&pll6 1>, <&osc32k>; clock-output-names = "apb1"; }; @@ -339,12 +345,22 @@ #size-cells = <1>; ranges; + dma: dma-controller@01c02000 { + compatible = "allwinner,sun4i-a10-dma"; + reg = <0x01c02000 0x1000>; + interrupts = <27>; + clocks = <&ahb_gates 6>; + #dma-cells = <2>; + }; + spi0: spi@01c05000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c05000 0x1000>; interrupts = <10>; clocks = <&ahb_gates 20>, <&spi0_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 1 27>, <&dma 1 26>; + dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -356,6 +372,8 @@ interrupts = <11>; clocks = <&ahb_gates 21>, <&spi1_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 1 9>, <&dma 1 8>; + dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -451,6 +469,8 @@ interrupts = <12>; clocks = <&ahb_gates 22>, <&spi2_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 1 29>, <&dma 1 28>; + dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -490,6 +510,8 @@ interrupts = <50>; clocks = <&ahb_gates 23>, <&spi3_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 1 31>, <&dma 1 30>; + dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -749,7 +771,6 @@ reg = <0x01c2ac00 0x400>; interrupts = <7>; clocks = <&apb1_gates 0>; - clock-frequency = <100000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -760,7 +781,6 @@ reg = <0x01c2b000 0x400>; interrupts = <8>; clocks = <&apb1_gates 1>; - clock-frequency = <100000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -771,7 +791,6 @@ reg = <0x01c2b400 0x400>; interrupts = <9>; clocks = <&apb1_gates 2>; - clock-frequency = <100000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts index ea9519da5764..fe3c559ca6a8 100644 --- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts @@ -3,12 +3,48 @@ * * Maxime Ripard <maxime.ripard@free-electrons.com> * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts index 43a93762d4f2..1fa2916eafc2 100644 --- a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts +++ b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts @@ -1,12 +1,48 @@ /* * Copyright 2014 Hans de Goede <hdegoede@redhat.com> * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi index 24b0ad3a7c07..1b76667f3182 100644 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi @@ -24,6 +24,20 @@ serial3 = &uart3; }; + chosen { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + framebuffer@0 { + compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; + allwinner,pipeline = "de_be0-lcd0-hdmi"; + clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, + <&ahb_gates 44>; + status = "disabled"; + }; + }; + cpus { cpu@0 { compatible = "arm,cortex-a8"; @@ -162,19 +176,11 @@ "apb0_ir", "apb0_keypad"; }; - apb1_mux: apb1_mux@01c20058 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb1-mux-clk"; - reg = <0x01c20058 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&osc32k>; - clock-output-names = "apb1_mux"; - }; - - apb1: apb1@01c20058 { + apb1: clk@01c20058 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-apb1-clk"; reg = <0x01c20058 0x4>; - clocks = <&apb1_mux>; + clocks = <&osc24M>, <&pll6 1>, <&osc32k>; clock-output-names = "apb1"; }; @@ -287,7 +293,7 @@ mbus_clk: clk@01c2015c { #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; + compatible = "allwinner,sun5i-a13-mbus-clk"; reg = <0x01c2015c 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "mbus"; @@ -300,12 +306,22 @@ #size-cells = <1>; ranges; + dma: dma-controller@01c02000 { + compatible = "allwinner,sun4i-a10-dma"; + reg = <0x01c02000 0x1000>; + interrupts = <27>; + clocks = <&ahb_gates 6>; + #dma-cells = <2>; + }; + spi0: spi@01c05000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c05000 0x1000>; interrupts = <10>; clocks = <&ahb_gates 20>, <&spi0_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 1 27>, <&dma 1 26>; + dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -317,6 +333,8 @@ interrupts = <11>; clocks = <&ahb_gates 21>, <&spi1_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 1 9>, <&dma 1 8>; + dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -403,6 +421,8 @@ interrupts = <12>; clocks = <&ahb_gates 22>, <&spi2_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 1 29>, <&dma 1 28>; + dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -564,7 +584,6 @@ reg = <0x01c2ac00 0x400>; interrupts = <7>; clocks = <&apb1_gates 0>; - clock-frequency = <100000>; status = "disabled"; }; @@ -575,7 +594,6 @@ reg = <0x01c2b000 0x400>; interrupts = <8>; clocks = <&apb1_gates 1>; - clock-frequency = <100000>; status = "disabled"; }; @@ -586,7 +604,6 @@ reg = <0x01c2b400 0x400>; interrupts = <9>; clocks = <&apb1_gates 2>; - clock-frequency = <100000>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts new file mode 100644 index 000000000000..eeed1f236ee8 --- /dev/null +++ b/arch/arm/boot/dts/sun5i-a13-hsg-h702.dts @@ -0,0 +1,130 @@ +/* + * Copyright 2014 Chen-Yu Tsai <wens@csie.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +/include/ "sun5i-a13.dtsi" +/include/ "sunxi-common-regulators.dtsi" + +/ { + model = "HSG H702"; + compatible = "hsg,h702", "allwinner,sun5i-a13"; + + soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_h702>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 6 0 0>; /* PG0 */ + cd-inverted; + status = "okay"; + }; + + usbphy: phy@01c13400 { + /* + * There doesn't seem to be a GPIO for controlling + * usb1 vbus, despite the fex file saying otherwise. + */ + usb1_vbus-supply = <®_vcc5v0>; + status = "okay"; + }; + + ehci0: usb@01c14000 { + status = "okay"; + }; + + ohci0: usb@01c14400 { + status = "okay"; + }; + + pinctrl@01c20800 { + mmc0_cd_pin_h702: mmc0_cd_pin@0 { + allwinner,pins = "PG0"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + }; + + uart1: serial@01c28400 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_b>; + status = "okay"; + }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupts = <0>; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + i2c1: i2c@01c2b000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + + pcf8563: rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + }; + }; + + i2c2: i2c@01c2b400 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; + }; + }; +}; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts index fa44b026483b..916ee8bb826f 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts @@ -1,15 +1,49 @@ /* - * Copyright 2012 Maxime Ripard + * Copyright 2012 Maxime Ripard <maxime.ripard@free-electrons.com> * Copyright 2013 Hans de Goede <hdegoede@redhat.com> * - * Maxime Ripard <maxime.ripard@free-electrons.com> + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts index 429994e1943e..e31d291d14cb 100644 --- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts +++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts @@ -3,12 +3,48 @@ * * Maxime Ripard <maxime.ripard@free-electrons.com> * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi index bf86e65dd167..c35217ea1f64 100644 --- a/arch/arm/boot/dts/sun5i-a13.dtsi +++ b/arch/arm/boot/dts/sun5i-a13.dtsi @@ -161,19 +161,11 @@ clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir"; }; - apb1_mux: apb1_mux@01c20058 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb1-mux-clk"; - reg = <0x01c20058 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&osc32k>; - clock-output-names = "apb1_mux"; - }; - - apb1: apb1@01c20058 { + apb1: clk@01c20058 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-apb1-clk"; reg = <0x01c20058 0x4>; - clocks = <&apb1_mux>; + clocks = <&osc24M>, <&pll6 1>, <&osc32k>; clock-output-names = "apb1"; }; @@ -285,7 +277,7 @@ mbus_clk: clk@01c2015c { #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; + compatible = "allwinner,sun5i-a13-mbus-clk"; reg = <0x01c2015c 0x4>; clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; clock-output-names = "mbus"; @@ -298,12 +290,22 @@ #size-cells = <1>; ranges; + dma: dma-controller@01c02000 { + compatible = "allwinner,sun4i-a10-dma"; + reg = <0x01c02000 0x1000>; + interrupts = <27>; + clocks = <&ahb_gates 6>; + #dma-cells = <2>; + }; + spi0: spi@01c05000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c05000 0x1000>; interrupts = <10>; clocks = <&ahb_gates 20>, <&spi0_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 1 27>, <&dma 1 26>; + dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -315,6 +317,8 @@ interrupts = <11>; clocks = <&ahb_gates 21>, <&spi1_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 1 9>, <&dma 1 8>; + dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -376,6 +380,8 @@ interrupts = <12>; clocks = <&ahb_gates 22>, <&spi2_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 1 29>, <&dma 1 28>; + dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -490,7 +496,6 @@ reg = <0x01c2ac00 0x400>; interrupts = <7>; clocks = <&apb1_gates 0>; - clock-frequency = <100000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -501,7 +506,6 @@ reg = <0x01c2b000 0x400>; interrupts = <8>; clocks = <&apb1_gates 1>; - clock-frequency = <100000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -512,7 +516,6 @@ reg = <0x01c2b400 0x400>; interrupts = <9>; clocks = <&apb1_gates 2>; - clock-frequency = <100000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts b/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts index 2bbf8867362b..c74a63a39531 100644 --- a/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts +++ b/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts @@ -3,12 +3,48 @@ * * Boris Brezillon <boris.brezillon@free-electrons.com> * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/sun6i-a31-colombus.dts index 546cf6eff5c7..c36b4dc89c13 100644 --- a/arch/arm/boot/dts/sun6i-a31-colombus.dts +++ b/arch/arm/boot/dts/sun6i-a31-colombus.dts @@ -3,12 +3,48 @@ * * Maxime Ripard <maxime.ripard@free-electrons.com> * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts index f142065b3c1f..6e924d9d2912 100644 --- a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts +++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts @@ -3,12 +3,48 @@ * * Maxime Ripard <maxime.ripard@free-electrons.com> * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/sun6i-a31-m9.dts b/arch/arm/boot/dts/sun6i-a31-m9.dts index bc6115da5ae1..3ab544f3af4a 100644 --- a/arch/arm/boot/dts/sun6i-a31-m9.dts +++ b/arch/arm/boot/dts/sun6i-a31-m9.dts @@ -1,12 +1,48 @@ /* * Copyright 2014 Hans de Goede <hdegoede@redhat.com> * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; @@ -32,13 +68,40 @@ status = "okay"; }; + usbphy: phy@01c19400 { + usb1_vbus-supply = <®_usb1_vbus>; + status = "okay"; + }; + + ehci0: usb@01c1a000 { + status = "okay"; + }; + + ehci1: usb@01c1b000 { + status = "okay"; + }; + pio: pinctrl@01c20800 { + led_pins_m9: led_pins@0 { + allwinner,pins = "PH13"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + mmc0_cd_pin_m9: mmc0_cd_pin@0 { allwinner,pins = "PH22"; allwinner,function = "gpio_in"; allwinner,drive = <0>; allwinner,pull = <1>; }; + + usb1_vbus_pin_m9: usb1_vbus_pin@0 { + allwinner,pins = "PC27"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; }; uart0: serial@01c28000 { @@ -46,5 +109,35 @@ pinctrl-0 = <&uart0_pins_a>; status = "okay"; }; + + gmac: ethernet@01c30000 { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_mii_a>; + phy = <&phy1>; + phy-mode = "mii"; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_m9>; + + blue { + label = "m9:blue:usr"; + gpios = <&pio 7 13 0>; + }; + }; + + reg_usb1_vbus: usb1-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&usb1_vbus_pin_m9>; + gpio = <&pio 2 27 0>; + status = "okay"; }; }; diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index e06fbfc55bb7..f47156b6572b 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -3,12 +3,48 @@ * * Maxime Ripard <maxime.ripard@free-electrons.com> * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /include/ "skeleton.dtsi" @@ -26,6 +62,18 @@ ethernet0 = &gmac; }; + chosen { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + framebuffer@0 { + compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; + allwinner,pipeline = "de_be0-lcd0-hdmi"; + clocks = <&pll6 0>; + status = "disabled"; + }; + }; cpus { enable-method = "allwinner,sun6i-a31"; @@ -96,11 +144,11 @@ }; pll6: clk@01c20028 { - #clock-cells = <0>; + #clock-cells = <1>; compatible = "allwinner,sun6i-a31-pll6-clk"; reg = <0x01c20028 0x4>; clocks = <&osc24M>; - clock-output-names = "pll6"; + clock-output-names = "pll6", "pll6x2"; }; cpu: cpu@01c20050 { @@ -130,7 +178,7 @@ #clock-cells = <0>; compatible = "allwinner,sun6i-a31-ahb1-mux-clk"; reg = <0x01c20054 0x4>; - clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>; + clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>; clock-output-names = "ahb1_mux"; }; @@ -181,19 +229,11 @@ "apb1_daudio1"; }; - apb2_mux: apb2_mux@01c20058 { + apb2: clk@01c20058 { #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb1-mux-clk"; + compatible = "allwinner,sun4i-a10-apb1-clk"; reg = <0x01c20058 0x4>; - clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; - clock-output-names = "apb2_mux"; - }; - - apb2: apb2@01c20058 { - #clock-cells = <0>; - compatible = "allwinner,sun6i-a31-apb2-div-clk"; - reg = <0x01c20058 0x4>; - clocks = <&apb2_mux>; + clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; clock-output-names = "apb2"; }; @@ -212,7 +252,7 @@ #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20088 0x4>; - clocks = <&osc24M>, <&pll6>; + clocks = <&osc24M>, <&pll6 0>; clock-output-names = "mmc0"; }; @@ -220,7 +260,7 @@ #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c2008c 0x4>; - clocks = <&osc24M>, <&pll6>; + clocks = <&osc24M>, <&pll6 0>; clock-output-names = "mmc1"; }; @@ -228,7 +268,7 @@ #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20090 0x4>; - clocks = <&osc24M>, <&pll6>; + clocks = <&osc24M>, <&pll6 0>; clock-output-names = "mmc2"; }; @@ -236,7 +276,7 @@ #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c20094 0x4>; - clocks = <&osc24M>, <&pll6>; + clocks = <&osc24M>, <&pll6 0>; clock-output-names = "mmc3"; }; @@ -244,7 +284,7 @@ #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200a0 0x4>; - clocks = <&osc24M>, <&pll6>; + clocks = <&osc24M>, <&pll6 0>; clock-output-names = "spi0"; }; @@ -252,7 +292,7 @@ #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200a4 0x4>; - clocks = <&osc24M>, <&pll6>; + clocks = <&osc24M>, <&pll6 0>; clock-output-names = "spi1"; }; @@ -260,7 +300,7 @@ #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200a8 0x4>; - clocks = <&osc24M>, <&pll6>; + clocks = <&osc24M>, <&pll6 0>; clock-output-names = "spi2"; }; @@ -268,7 +308,7 @@ #clock-cells = <0>; compatible = "allwinner,sun4i-a10-mod0-clk"; reg = <0x01c200ac 0x4>; - clocks = <&osc24M>, <&pll6>; + clocks = <&osc24M>, <&pll6 0>; clock-output-names = "spi3"; }; @@ -325,6 +365,10 @@ clocks = <&ahb1_gates 6>; resets = <&ahb1_rst 6>; #dma-cells = <1>; + + /* DMA controller requires AHB1 clocked from PLL6 */ + assigned-clocks = <&ahb1_mux>; + assigned-clock-parents = <&pll6 0>; }; mmc0: mmc@01c0f000 { @@ -657,7 +701,6 @@ reg = <0x01c2ac00 0x400>; interrupts = <0 6 4>; clocks = <&apb2_gates 0>; - clock-frequency = <100000>; resets = <&apb2_rst 0>; status = "disabled"; #address-cells = <1>; @@ -669,7 +712,6 @@ reg = <0x01c2b000 0x400>; interrupts = <0 7 4>; clocks = <&apb2_gates 1>; - clock-frequency = <100000>; resets = <&apb2_rst 1>; status = "disabled"; #address-cells = <1>; @@ -681,7 +723,6 @@ reg = <0x01c2b400 0x400>; interrupts = <0 8 4>; clocks = <&apb2_gates 2>; - clock-frequency = <100000>; resets = <&apb2_rst 2>; status = "disabled"; #address-cells = <1>; @@ -693,7 +734,6 @@ reg = <0x01c2b800 0x400>; interrupts = <0 9 4>; clocks = <&apb2_gates 3>; - clock-frequency = <100000>; resets = <&apb2_rst 3>; status = "disabled"; #address-cells = <1>; @@ -787,6 +827,12 @@ interrupts = <1 9 0xf04>; }; + rtc: rtc@01f00000 { + compatible = "allwinner,sun6i-a31-rtc"; + reg = <0x01f00000 0x54>; + interrupts = <0 40 4>, <0 41 4>; + }; + nmi_intc: interrupt-controller@01f00c0c { compatible = "allwinner,sun6i-a31-sc-nmi"; interrupt-controller; @@ -802,7 +848,7 @@ ar100: ar100_clk { compatible = "allwinner,sun6i-a31-ar100-clk"; #clock-cells = <0>; - clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; + clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>; clock-output-names = "ar100"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi.dts b/arch/arm/boot/dts/sun7i-a20-bananapi.dts new file mode 100644 index 000000000000..1cf1214cc068 --- /dev/null +++ b/arch/arm/boot/dts/sun7i-a20-bananapi.dts @@ -0,0 +1,214 @@ +/* + * Copyright 2014 Hans de Goede <hdegoede@redhat.com> + * + * Hans de Goede <hdegoede@redhat.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +/include/ "sun7i-a20.dtsi" +/include/ "sunxi-common-regulators.dtsi" + +/ { + model = "LeMaker Banana Pi"; + compatible = "lemaker,bananapi", "allwinner,sun7i-a20"; + + soc@01c00000 { + spi0: spi@01c05000 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins_a>; + status = "okay"; + }; + + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bananapi>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 10 0>; /* PH10 */ + cd-inverted; + status = "okay"; + }; + + usbphy: phy@01c13400 { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; + }; + + ehci0: usb@01c14000 { + status = "okay"; + }; + + ohci0: usb@01c14400 { + status = "okay"; + }; + + ahci: sata@01c18000 { + status = "okay"; + }; + + ehci1: usb@01c1c000 { + status = "okay"; + }; + + ohci1: usb@01c1c400 { + status = "okay"; + }; + + pinctrl@01c20800 { + mmc0_cd_pin_bananapi: mmc0_cd_pin@0 { + allwinner,pins = "PH10"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + + gmac_power_pin_bananapi: gmac_power_pin@0 { + allwinner,pins = "PH23"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + led_pins_bananapi: led_pins@0 { + allwinner,pins = "PH24"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + }; + + ir0: ir@01c21800 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_pins_a>; + status = "okay"; + }; + + uart0: serial@01c28000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; + }; + + uart3: serial@01c28c00 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins_b>; + status = "okay"; + }; + + uart7: serial@01c29c00 { + pinctrl-names = "default"; + pinctrl-0 = <&uart7_pins_a>; + status = "okay"; + }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 8>; + + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + i2c2: i2c@01c2b400 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; + }; + + gmac: ethernet@01c50000 { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_rgmii_a>; + phy = <&phy1>; + phy-mode = "rgmii"; + phy-supply = <®_gmac_3v3>; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_bananapi>; + + green { + label = "bananapi:green:usr"; + gpios = <&pio 7 24 0>; + }; + }; + + reg_usb1_vbus: usb1-vbus { + status = "okay"; + }; + + reg_usb2_vbus: usb2-vbus { + status = "okay"; + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac_power_pin_bananapi>; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 7 23 0>; + }; +}; diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts index a6c1a3c717bc..a281d259b9b8 100644 --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts @@ -40,6 +40,7 @@ }; usbphy: phy@01c13400 { + usb0_vbus-supply = <®_usb0_vbus>; usb1_vbus-supply = <®_usb1_vbus>; usb2_vbus-supply = <®_usb2_vbus>; status = "okay"; @@ -92,6 +93,13 @@ allwinner,drive = <0>; allwinner,pull = <0>; }; + + usb0_vbus_pin_a: usb0_vbus_pin@0 { + allwinner,pins = "PH17"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; }; pwm: pwm@01c20e00 { @@ -185,6 +193,12 @@ status = "okay"; }; + reg_usb0_vbus: usb0-vbus { + pinctrl-0 = <&usb0_vbus_pin_a>; + gpio = <&pio 7 17 0>; + status = "okay"; + }; + reg_usb1_vbus: usb1-vbus { status = "okay"; }; diff --git a/arch/arm/boot/dts/sun7i-a20-hummingbird.dts b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts new file mode 100644 index 000000000000..0e4bfa3b2b85 --- /dev/null +++ b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts @@ -0,0 +1,236 @@ +/* + * Copyright 2013 Wills Wang + * + * Wills Wang <wills.wang.open@gmail.com> + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +/include/ "sun7i-a20.dtsi" +/include/ "sunxi-common-regulators.dtsi" + +/ { + model = "Merrii A20 Hummingbird"; + compatible = "merrii,a20-hummingbird", "allwinner,sun7i-a20"; + + soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v0>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + + mmc3: mmc@01c12000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_pins_a>; + vmmc-supply = <®_mmc3_vdd>; + bus-width = <4>; + non-removable; + status = "okay"; + }; + + usbphy: phy@01c13400 { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; + }; + + ehci0: usb@01c14000 { + status = "okay"; + }; + + ohci0: usb@01c14400 { + status = "okay"; + }; + + ahci: sata@01c18000 { + target-supply = <®_ahci_5v>; + status = "okay"; + }; + + ehci1: usb@01c1c000 { + status = "okay"; + }; + + ohci1: usb@01c1c400 { + status = "okay"; + }; + + pio: pinctrl@01c20800 { + ahci_pwr_pin_a20_hummingbird: ahci_pwr_pin@0 { + allwinner,pins = "PH15"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + usb1_vbus_pin_a20_hummingbird: usb1_vbus_pin@0 { + allwinner,pins = "PH2"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + mmc3_vdd_pin_a20_hummingbird: mmc3_vdd_pin@0 { + allwinner,pins = "PH9"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + gmac_vdd_pin_a20_hummingbird: gmac_vdd_pin@0 { + allwinner,pins = "PH16"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + }; + + pwm: pwm@01c20e00 { + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins_a>; + status = "okay"; + }; + + ir0: ir@01c21800 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_pins_a>; + status = "okay"; + }; + + uart0: serial@01c28000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; + }; + + uart2: serial@01c28800 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins_a>; + status = "okay"; + }; + + uart3: serial@01c28c00 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins_a>; + status = "okay"; + }; + + uart4: serial@01c29000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + status = "okay"; + }; + + uart5: serial@01c29400 { + pinctrl-names = "default"; + pinctrl-0 = <&uart5_pins_a>; + status = "okay"; + }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 8>; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + i2c1: i2c@01c2b000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + }; + + i2c2: i2c@01c2b400 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; + }; + + i2c3: i2c@01c2b800 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins_a>; + status = "okay"; + }; + + spi2: spi@01c17000 { + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_b>; + status = "okay"; + }; + + gmac: ethernet@01c50000 { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_rgmii_a>; + phy = <&phy1>; + phy-mode = "rgmii"; + phy-supply = <®_gmac_vdd>; + /* phy reset config */ + snps,reset-gpio = <&pio 0 17 0>; /* PA17 */ + snps,reset-active-low; + /* wait 1s after reset, otherwise fail to read phy id */ + snps,reset-delays-us = <0 10000 1000000>; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + }; + + reg_ahci_5v: ahci-5v { + pinctrl-0 = <&ahci_pwr_pin_a20_hummingbird>; + gpio = <&pio 7 15 0>; /* PH15 */ + status = "okay"; + }; + + reg_usb1_vbus: usb1-vbus { + pinctrl-0 = <&usb1_vbus_pin_a20_hummingbird>; + gpio = <&pio 7 2 0>; /* PH2 */ + status = "okay"; + }; + + reg_usb2_vbus: usb2-vbus { + status = "okay"; + }; + + reg_mmc3_vdd: mmc3_vdd { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc3_vdd_pin_a20_hummingbird>; + regulator-name = "mmc3_vdd"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + enable-active-high; + gpio = <&pio 7 9 0>; /* PH9 */ + }; + + reg_gmac_vdd: gmac_vdd { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac_vdd_pin_a20_hummingbird>; + regulator-name = "gmac_vdd"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + enable-active-high; + gpio = <&pio 7 16 0>; /* PH16 */ + }; +}; diff --git a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts index 6a67712d417a..f38bb1a6656c 100644 --- a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts +++ b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts @@ -1,12 +1,48 @@ /* * Copyright 2014 Hans de Goede <hdegoede@redhat.com> * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/sun7i-a20-m3.dts b/arch/arm/boot/dts/sun7i-a20-m3.dts new file mode 100644 index 000000000000..b8e568c55271 --- /dev/null +++ b/arch/arm/boot/dts/sun7i-a20-m3.dts @@ -0,0 +1,168 @@ +/* + * Copyright 2014 Hans de Goede <hdegoede@redhat.com> + * + * Hans de Goede <hdegoede@redhat.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +/include/ "sun7i-a20.dtsi" +/include/ "sunxi-common-regulators.dtsi" + +/ { + model = "Mele M3"; + compatible = "mele,m3", "allwinner,sun7i-a20"; + + soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + + mmc2: mmc@01c11000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins_a>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + non-removable; + status = "okay"; + }; + + usbphy: phy@01c13400 { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; + }; + + ehci0: usb@01c14000 { + status = "okay"; + }; + + ohci0: usb@01c14400 { + status = "okay"; + }; + + ehci1: usb@01c1c000 { + status = "okay"; + }; + + ohci1: usb@01c1c400 { + status = "okay"; + }; + + pinctrl@01c20800 { + led_pins_m3: led_pins@0 { + allwinner,pins = "PH20"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + }; + + ir0: ir@01c21800 { + pinctrl-names = "default"; + pinctrl-0 = <&ir0_pins_a>; + status = "okay"; + }; + + uart0: serial@01c28000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; + }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 8>; + + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + gmac: ethernet@01c50000 { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_mii_a>; + phy = <&phy1>; + phy-mode = "mii"; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_m3>; + + blue { + label = "m3:blue:usr"; + gpios = <&pio 7 20 0>; + }; + }; + + reg_usb1_vbus: usb1-vbus { + status = "okay"; + }; + + reg_usb2_vbus: usb2-vbus { + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts new file mode 100644 index 000000000000..3f3ff9693992 --- /dev/null +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts @@ -0,0 +1,173 @@ +/* + * This is based on sun4i-a10-olinuxino-lime.dts + * + * Copyright 2014 - Hans de Goede <hdegoede@redhat.com> + * Copyright (c) 2014 FUKAUMI Naoki <naobsd@gmail.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +/include/ "sun7i-a20.dtsi" +/include/ "sunxi-common-regulators.dtsi" + +/ { + model = "Olimex A20-OLinuXino-LIME"; + compatible = "olimex,a20-olinuxino-lime", "allwinner,sun7i-a20"; + + soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + + usbphy: phy@01c13400 { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; + }; + + ehci0: usb@01c14000 { + status = "okay"; + }; + + ohci0: usb@01c14400 { + status = "okay"; + }; + + ahci: sata@01c18000 { + target-supply = <®_ahci_5v>; + status = "okay"; + }; + + ehci1: usb@01c1c000 { + status = "okay"; + }; + + ohci1: usb@01c1c400 { + status = "okay"; + }; + + pinctrl@01c20800 { + ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 { + allwinner,pins = "PC3"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + led_pins_olinuxinolime: led_pins@0 { + allwinner,pins = "PH2"; + allwinner,function = "gpio_out"; + allwinner,drive = <1>; + allwinner,pull = <0>; + }; + }; + + uart0: serial@01c28000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; + }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 8>; + + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + gmac: ethernet@01c50000 { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_mii_a>; + phy = <&phy1>; + phy-mode = "mii"; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_olinuxinolime>; + + green { + label = "a20-olinuxino-lime:green:usr"; + gpios = <&pio 7 2 0>; + default-state = "on"; + }; + }; + + reg_ahci_5v: ahci-5v { + pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>; + gpio = <&pio 2 3 0>; + status = "okay"; + }; + + reg_usb1_vbus: usb1-vbus { + status = "okay"; + }; + + reg_usb2_vbus: usb2-vbus { + status = "okay"; + }; +}; diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts new file mode 100644 index 000000000000..ed364d5e755e --- /dev/null +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts @@ -0,0 +1,228 @@ +/* + * Copyright 2014 - Iain Paton <ipaton0@gmail.com> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +/include/ "sun7i-a20.dtsi" +/include/ "sunxi-common-regulators.dtsi" + +/ { + model = "Olimex A20-OLinuXino-LIME2"; + compatible = "olimex,a20-olinuxino-lime2", "allwinner,sun7i-a20"; + + soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>; + vmmc-supply = <®_vcc3v3>; + bus-width = <4>; + cd-gpios = <&pio 7 1 0>; /* PH1 */ + cd-inverted; + status = "okay"; + }; + + usbphy: phy@01c13400 { + usb1_vbus-supply = <®_usb1_vbus>; + usb2_vbus-supply = <®_usb2_vbus>; + status = "okay"; + }; + + ehci0: usb@01c14000 { + status = "okay"; + }; + + ohci0: usb@01c14400 { + status = "okay"; + }; + + ahci: sata@01c18000 { + target-supply = <®_ahci_5v>; + status = "okay"; + }; + + ehci1: usb@01c1c000 { + status = "okay"; + }; + + ohci1: usb@01c1c400 { + status = "okay"; + }; + + pinctrl@01c20800 { + ahci_pwr_pin_olinuxinolime: ahci_pwr_pin@1 { + allwinner,pins = "PC3"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + led_pins_olinuxinolime: led_pins@0 { + allwinner,pins = "PH2"; + allwinner,function = "gpio_out"; + allwinner,drive = <1>; + allwinner,pull = <0>; + }; + }; + + uart0: serial@01c28000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; + }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + + axp209: pmic@34 { + compatible = "x-powers,axp209"; + reg = <0x34>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 8>; + + interrupt-controller; + #interrupt-cells = <1>; + + acin-supply = <®_axp_ipsout>; + vin2-supply = <®_axp_ipsout>; + vin3-supply = <®_axp_ipsout>; + ldo24in-supply = <®_axp_ipsout>; + ldo3in-supply = <®_axp_ipsout>; + + regulators { + vdd_rtc: ldo1 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + }; + + avcc: ldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vcc_csi0: ldo3 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3500000>; + regulator-always-on; + }; + + vcc_csi1: ldo4 { + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_cpu: dcdc2 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <2275000>; + regulator-always-on; + }; + + vdd_int: dcdc3 { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3500000>; + regulator-always-on; + }; + }; + }; + }; + + i2c1: i2c@01c2b000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + }; + + gmac: ethernet@01c50000 { + pinctrl-names = "default"; + pinctrl-0 = <&gmac_pins_rgmii_a>; + phy = <&phy1>; + phy-mode = "rgmii"; + status = "okay"; + + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_olinuxinolime>; + + green { + label = "a20-olinuxino-lime2:green:usr"; + gpios = <&pio 7 2 0>; + default-state = "on"; + }; + }; + + reg_ahci_5v: ahci-5v { + pinctrl-0 = <&ahci_pwr_pin_olinuxinolime>; + gpio = <&pio 2 3 0>; + status = "okay"; + }; + + reg_usb1_vbus: usb1-vbus { + status = "okay"; + }; + + reg_usb2_vbus: usb2-vbus { + status = "okay"; + }; + + reg_axp_ipsout: axp_ipsout { + compatible = "regulator-fixed"; + regulator-name = "axp-ipsout"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts index 046dfc0d45d8..8dca49b2477b 100644 --- a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts +++ b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts @@ -2,12 +2,48 @@ * Copyright 2014 Zoltan HERPAI * Zoltan HERPAI <wigyori@uid0.hu> * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi index 4011628c7381..e21ce5992d56 100644 --- a/arch/arm/boot/dts/sun7i-a20.dtsi +++ b/arch/arm/boot/dts/sun7i-a20.dtsi @@ -3,12 +3,48 @@ * * Maxime Ripard <maxime.ripard@free-electrons.com> * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /include/ "skeleton.dtsi" @@ -28,6 +64,20 @@ serial7 = &uart7; }; + chosen { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + framebuffer@0 { + compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; + allwinner,pipeline = "de_be0-lcd0-hdmi"; + clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, + <&ahb_gates 44>; + status = "disabled"; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -186,19 +236,11 @@ "apb0_iis2", "apb0_keypad"; }; - apb1_mux: apb1_mux@01c20058 { - #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb1-mux-clk"; - reg = <0x01c20058 0x4>; - clocks = <&osc24M>, <&pll6 1>, <&osc32k>; - clock-output-names = "apb1_mux"; - }; - - apb1: apb1@01c20058 { + apb1: clk@01c20058 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-apb1-clk"; reg = <0x01c20058 0x4>; - clocks = <&apb1_mux>; + clocks = <&osc24M>, <&pll6 1>, <&osc32k>; clock-output-names = "apb1"; }; @@ -346,7 +388,7 @@ mbus_clk: clk@01c2015c { #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-mod0-clk"; + compatible = "allwinner,sun5i-a13-mbus-clk"; reg = <0x01c2015c 0x4>; clocks = <&osc24M>, <&pll6 2>, <&pll5 1>; clock-output-names = "mbus"; @@ -423,12 +465,22 @@ interrupts = <0 0 4>; }; + dma: dma-controller@01c02000 { + compatible = "allwinner,sun4i-a10-dma"; + reg = <0x01c02000 0x1000>; + interrupts = <0 27 4>; + clocks = <&ahb_gates 6>; + #dma-cells = <2>; + }; + spi0: spi@01c05000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c05000 0x1000>; interrupts = <0 10 4>; clocks = <&ahb_gates 20>, <&spi0_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 1 27>, <&dma 1 26>; + dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -440,6 +492,8 @@ interrupts = <0 11 4>; clocks = <&ahb_gates 21>, <&spi1_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 1 9>, <&dma 1 8>; + dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -504,8 +558,8 @@ reg-names = "phy_ctrl", "pmu1", "pmu2"; clocks = <&usb_clk 8>; clock-names = "usb_phy"; - resets = <&usb_clk 1>, <&usb_clk 2>; - reset-names = "usb1_reset", "usb2_reset"; + resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>; + reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; status = "disabled"; }; @@ -535,6 +589,8 @@ interrupts = <0 12 4>; clocks = <&ahb_gates 22>, <&spi2_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 1 29>, <&dma 1 28>; + dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -574,6 +630,8 @@ interrupts = <0 50 4>; clocks = <&ahb_gates 23>, <&spi3_clk>; clock-names = "ahb", "mod"; + dmas = <&dma 1 31>, <&dma 1 30>; + dma-names = "rx", "tx"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -618,6 +676,34 @@ allwinner,pull = <0>; }; + uart3_pins_a: uart3@0 { + allwinner,pins = "PG6", "PG7", "PG8", "PG9"; + allwinner,function = "uart3"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + uart3_pins_b: uart3@1 { + allwinner,pins = "PH0", "PH1"; + allwinner,function = "uart3"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + uart4_pins_a: uart4@0 { + allwinner,pins = "PG10", "PG11"; + allwinner,function = "uart4"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + uart5_pins_a: uart5@0 { + allwinner,pins = "PI10", "PI11"; + allwinner,function = "uart5"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + uart6_pins_a: uart6@0 { allwinner,pins = "PI12", "PI13"; allwinner,function = "uart6"; @@ -653,6 +739,13 @@ allwinner,pull = <0>; }; + i2c3_pins_a: i2c3@0 { + allwinner,pins = "PI0", "PI1"; + allwinner,function = "i2c3"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + emac_pins_a: emac0@0 { allwinner,pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", @@ -704,6 +797,13 @@ allwinner,pull = <0>; }; + spi0_pins_a: spi0@0 { + allwinner,pins = "PI10", "PI11", "PI12", "PI13", "PI14"; + allwinner,function = "spi0"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + spi1_pins_a: spi1@0 { allwinner,pins = "PI16", "PI17", "PI18", "PI19"; allwinner,function = "spi1"; @@ -718,6 +818,13 @@ allwinner,pull = <0>; }; + spi2_pins_b: spi2@1 { + allwinner,pins = "PB14", "PB15", "PB16", "PB17"; + allwinner,function = "spi2"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + mmc0_pins_a: mmc0@0 { allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; allwinner,function = "mmc0"; @@ -732,6 +839,13 @@ allwinner,pull = <1>; }; + mmc2_pins_a: mmc2@0 { + allwinner,pins = "PC6","PC7","PC8","PC9","PC10","PC11"; + allwinner,function = "mmc2"; + allwinner,drive = <2>; + allwinner,pull = <1>; + }; + mmc3_pins_a: mmc3@0 { allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9"; allwinner,function = "mmc3"; @@ -899,7 +1013,6 @@ reg = <0x01c2ac00 0x400>; interrupts = <0 7 4>; clocks = <&apb1_gates 0>; - clock-frequency = <100000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -910,7 +1023,6 @@ reg = <0x01c2b000 0x400>; interrupts = <0 8 4>; clocks = <&apb1_gates 1>; - clock-frequency = <100000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -921,7 +1033,6 @@ reg = <0x01c2b400 0x400>; interrupts = <0 9 4>; clocks = <&apb1_gates 2>; - clock-frequency = <100000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -932,7 +1043,6 @@ reg = <0x01c2b800 0x400>; interrupts = <0 88 4>; clocks = <&apb1_gates 3>; - clock-frequency = <100000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -943,7 +1053,6 @@ reg = <0x01c2c000 0x400>; interrupts = <0 89 4>; clocks = <&apb1_gates 15>; - clock-frequency = <100000>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts index 34002e3eba9d..7f2117ce6985 100644 --- a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts +++ b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts @@ -3,16 +3,53 @@ * * Chen-Yu Tsai <wens@csie.org> * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; /include/ "sun8i-a23.dtsi" +/include/ "sunxi-common-regulators.dtsi" / { model = "Ippo Q8H Dual Core Tablet (v5)"; @@ -23,7 +60,47 @@ }; soc@01c00000 { + mmc0: mmc@01c0f000 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8h>; + vmmc-supply = <®_vcc3v0>; + bus-width = <4>; + cd-gpios = <&pio 1 4 0>; /* PB4 */ + cd-inverted; + status = "okay"; + }; + + pinctrl@01c20800 { + mmc0_cd_pin_q8h: mmc0_cd_pin@0 { + allwinner,pins = "PB4"; + allwinner,function = "gpio_in"; + allwinner,drive = <0>; + allwinner,pull = <1>; + }; + }; + + i2c0: i2c@01c2ac00 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + status = "okay"; + }; + + i2c1: i2c@01c2b000 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; + }; + + i2c2: i2c@01c2b400 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + /* pull-ups and devices require PMIC regulator */ + status = "failed"; + }; + r_uart: serial@01f02800 { + pinctrl-names = "default"; + pinctrl-0 = <&r_uart_pins_a>; status = "okay"; }; }; diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi index 54ac0787216a..0746cd1024d7 100644 --- a/arch/arm/boot/dts/sun8i-a23.dtsi +++ b/arch/arm/boot/dts/sun8i-a23.dtsi @@ -3,12 +3,48 @@ * * Chen-Yu Tsai <wens@csie.org> * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ /include/ "skeleton.dtsi" @@ -153,19 +189,11 @@ "apb1_daudio0", "apb1_daudio1"; }; - apb2_mux: apb2_mux_clk@01c20058 { + apb2: clk@01c20058 { #clock-cells = <0>; - compatible = "allwinner,sun4i-a10-apb1-mux-clk"; + compatible = "allwinner,sun4i-a10-apb1-clk"; reg = <0x01c20058 0x4>; clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>; - clock-output-names = "apb2_mux"; - }; - - apb2: apb2_clk@01c20058 { - #clock-cells = <0>; - compatible = "allwinner,sun6i-a31-apb2-div-clk"; - reg = <0x01c20058 0x4>; - clocks = <&apb2_mux>; clock-output-names = "apb2"; }; @@ -179,6 +207,30 @@ "apb2_uart1", "apb2_uart2", "apb2_uart3", "apb2_uart4"; }; + + mmc0_clk: clk@01c20088 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20088 0x4>; + clocks = <&osc24M>, <&pll6>; + clock-output-names = "mmc0"; + }; + + mmc1_clk: clk@01c2008c { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c2008c 0x4>; + clocks = <&osc24M>, <&pll6>; + clock-output-names = "mmc1"; + }; + + mmc2_clk: clk@01c20090 { + #clock-cells = <0>; + compatible = "allwinner,sun4i-a10-mod0-clk"; + reg = <0x01c20090 0x4>; + clocks = <&osc24M>, <&pll6>; + clock-output-names = "mmc2"; + }; }; soc@01c00000 { @@ -187,6 +239,104 @@ #size-cells = <1>; ranges; + dma: dma-controller@01c02000 { + compatible = "allwinner,sun8i-a23-dma"; + reg = <0x01c02000 0x1000>; + interrupts = <0 50 4>; + clocks = <&ahb1_gates 6>; + resets = <&ahb1_rst 6>; + #dma-cells = <1>; + }; + + mmc0: mmc@01c0f000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c0f000 0x1000>; + clocks = <&ahb1_gates 8>, <&mmc0_clk>; + clock-names = "ahb", "mmc"; + resets = <&ahb1_rst 8>; + reset-names = "ahb"; + interrupts = <0 60 4>; + status = "disabled"; + }; + + mmc1: mmc@01c10000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c10000 0x1000>; + clocks = <&ahb1_gates 9>, <&mmc1_clk>; + clock-names = "ahb", "mmc"; + resets = <&ahb1_rst 9>; + reset-names = "ahb"; + interrupts = <0 61 4>; + status = "disabled"; + }; + + mmc2: mmc@01c11000 { + compatible = "allwinner,sun5i-a13-mmc"; + reg = <0x01c11000 0x1000>; + clocks = <&ahb1_gates 10>, <&mmc2_clk>; + clock-names = "ahb", "mmc"; + resets = <&ahb1_rst 10>; + reset-names = "ahb"; + interrupts = <0 62 4>; + status = "disabled"; + }; + + pio: pinctrl@01c20800 { + compatible = "allwinner,sun8i-a23-pinctrl"; + reg = <0x01c20800 0x400>; + interrupts = <0 11 4>, + <0 15 4>, + <0 17 4>; + clocks = <&apb1_gates 5>; + gpio-controller; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + #gpio-cells = <3>; + + uart0_pins_a: uart0@0 { + allwinner,pins = "PF2", "PF4"; + allwinner,function = "uart0"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + mmc0_pins_a: mmc0@0 { + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; + allwinner,function = "mmc0"; + allwinner,drive = <2>; + allwinner,pull = <0>; + }; + + mmc1_pins_a: mmc1@0 { + allwinner,pins = "PG0","PG1","PG2","PG3","PG4","PG5"; + allwinner,function = "mmc1"; + allwinner,drive = <2>; + allwinner,pull = <0>; + }; + + i2c0_pins_a: i2c0@0 { + allwinner,pins = "PH2", "PH3"; + allwinner,function = "i2c0"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + i2c1_pins_a: i2c1@0 { + allwinner,pins = "PH4", "PH5"; + allwinner,function = "i2c1"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + i2c2_pins_a: i2c2@0 { + allwinner,pins = "PE12", "PE13"; + allwinner,function = "i2c2"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + }; + ahb1_rst: reset@01c202c0 { #reset-cells = <1>; compatible = "allwinner,sun6i-a31-clock-reset"; @@ -227,6 +377,8 @@ reg-io-width = <4>; clocks = <&apb2_gates 16>; resets = <&apb2_rst 16>; + dmas = <&dma 6>, <&dma 6>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -238,6 +390,8 @@ reg-io-width = <4>; clocks = <&apb2_gates 17>; resets = <&apb2_rst 17>; + dmas = <&dma 7>, <&dma 7>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -249,6 +403,8 @@ reg-io-width = <4>; clocks = <&apb2_gates 18>; resets = <&apb2_rst 18>; + dmas = <&dma 8>, <&dma 8>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -260,6 +416,8 @@ reg-io-width = <4>; clocks = <&apb2_gates 19>; resets = <&apb2_rst 19>; + dmas = <&dma 9>, <&dma 9>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -271,9 +429,44 @@ reg-io-width = <4>; clocks = <&apb2_gates 20>; resets = <&apb2_rst 20>; + dmas = <&dma 10>, <&dma 10>; + dma-names = "rx", "tx"; status = "disabled"; }; + i2c0: i2c@01c2ac00 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = <0 6 4>; + clocks = <&apb2_gates 0>; + resets = <&apb2_rst 0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@01c2b000 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = <0 7 4>; + clocks = <&apb2_gates 1>; + resets = <&apb2_rst 1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@01c2b400 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b400 0x400>; + interrupts = <0 8 4>; + clocks = <&apb2_gates 2>; + resets = <&apb2_rst 2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + gic: interrupt-controller@01c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, @@ -285,6 +478,12 @@ interrupts = <1 9 0xf04>; }; + rtc: rtc@01f00000 { + compatible = "allwinner,sun6i-a31-rtc"; + reg = <0x01f00000 0x54>; + interrupts = <0 40 4>, <0 41 4>; + }; + prcm@01f01400 { compatible = "allwinner,sun8i-a23-prcm"; reg = <0x01f01400 0x200>; @@ -339,5 +538,25 @@ resets = <&apb0_rst 4>; status = "disabled"; }; + + r_pio: pinctrl@01f02c00 { + compatible = "allwinner,sun8i-a23-r-pinctrl"; + reg = <0x01f02c00 0x400>; + interrupts = <0 45 4>; + clocks = <&apb0_gates 0>; + resets = <&apb0_rst 0>; + gpio-controller; + interrupt-controller; + #address-cells = <1>; + #size-cells = <0>; + #gpio-cells = <3>; + + r_uart_pins_a: r_uart@0 { + allwinner,pins = "PL2", "PL3"; + allwinner,function = "s_uart"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + }; }; }; diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts new file mode 100644 index 000000000000..506948f582ee --- /dev/null +++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts @@ -0,0 +1,119 @@ +/* + * Copyright 2014 Chen-Yu Tsai + * + * Chen-Yu Tsai <wens@csie.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; +/include/ "sun9i-a80.dtsi" + +/ { + model = "Merrii A80 Optimus Board"; + compatible = "merrii,a80-optimus", "allwinner,sun9i-a80"; + + chosen { + bootargs = "earlyprintk console=ttyS0,115200"; + }; + + soc { + pio: pinctrl@06000800 { + i2c3_pins_a: i2c3@0 { + /* Enable internal pull-up */ + allwinner,pull = <1>; + }; + + led_pins_optimus: led-pins@0 { + allwinner,pins = "PH0", "PH1"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + uart4_pins_a: uart4@0 { + /* Enable internal pull-up */ + allwinner,pull = <1>; + }; + }; + + uart0: serial@07000000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; + status = "okay"; + }; + + uart4: serial@07001000 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + status = "okay"; + }; + + i2c3: i2c@07003400 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins_a>; + status = "okay"; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins_optimus>; + + /* The LED names match those found on the board */ + + led2 { + label = "optimus:led2:usr"; + gpios = <&pio 7 1 0>; + }; + + /* led3 is on PM15, in R_PIO */ + + led4 { + label = "optimus:led4:usr"; + gpios = <&pio 7 0 0>; + }; + }; +}; diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi new file mode 100644 index 000000000000..494714f67b57 --- /dev/null +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -0,0 +1,514 @@ +/* + * Copyright 2014 Chen-Yu Tsai + * + * Chen-Yu Tsai <wens@csie.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/include/ "skeleton64.dtsi" + +/ { + interrupt-parent = <&gic>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &r_uart; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0x0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0x1>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0x2>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0x3>; + }; + + cpu4: cpu@100 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0x100>; + }; + + cpu5: cpu@101 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0x101>; + }; + + cpu6: cpu@102 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0x102>; + }; + + cpu7: cpu@103 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0x103>; + }; + }; + + memory { + /* 8GB max. with LPAE */ + reg = <0 0x20000000 0x02 0>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + /* + * map 64 bit address range down to 32 bits, + * as the peripherals are all under 512MB. + */ + ranges = <0 0 0 0x20000000>; + + osc24M: osc24M_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: osc32k_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + + pll4: clk@0600000c { + #clock-cells = <0>; + compatible = "allwinner,sun9i-a80-pll4-clk"; + reg = <0x0600000c 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll4"; + }; + + pll12: clk@0600002c { + #clock-cells = <0>; + compatible = "allwinner,sun9i-a80-pll4-clk"; + reg = <0x0600002c 0x4>; + clocks = <&osc24M>; + clock-output-names = "pll12"; + }; + + gt_clk: clk@0600005c { + #clock-cells = <0>; + compatible = "allwinner,sun9i-a80-gt-clk"; + reg = <0x0600005c 0x4>; + clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>; + clock-output-names = "gt"; + }; + + ahb0: clk@06000060 { + #clock-cells = <0>; + compatible = "allwinner,sun9i-a80-ahb-clk"; + reg = <0x06000060 0x4>; + clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>; + clock-output-names = "ahb0"; + }; + + ahb1: clk@06000064 { + #clock-cells = <0>; + compatible = "allwinner,sun9i-a80-ahb-clk"; + reg = <0x06000064 0x4>; + clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>; + clock-output-names = "ahb1"; + }; + + ahb2: clk@06000068 { + #clock-cells = <0>; + compatible = "allwinner,sun9i-a80-ahb-clk"; + reg = <0x06000068 0x4>; + clocks = <>_clk>, <&pll4>, <&pll12>, <&pll12>; + clock-output-names = "ahb2"; + }; + + apb0: clk@06000070 { + #clock-cells = <0>; + compatible = "allwinner,sun9i-a80-apb0-clk"; + reg = <0x06000070 0x4>; + clocks = <&osc24M>, <&pll4>; + clock-output-names = "apb0"; + }; + + apb1: clk@06000074 { + #clock-cells = <0>; + compatible = "allwinner,sun9i-a80-apb1-clk"; + reg = <0x06000074 0x4>; + clocks = <&osc24M>, <&pll4>; + clock-output-names = "apb1"; + }; + + cci400_clk: clk@06000078 { + #clock-cells = <0>; + compatible = "allwinner,sun9i-a80-gt-clk"; + reg = <0x06000078 0x4>; + clocks = <&osc24M>, <&pll4>, <&pll12>, <&pll12>; + clock-output-names = "cci400"; + }; + + ahb0_gates: clk@06000580 { + #clock-cells = <1>; + compatible = "allwinner,sun9i-a80-ahb0-gates-clk"; + reg = <0x06000580 0x4>; + clocks = <&ahb0>; + clock-output-names = "ahb0_fd", "ahb0_ve", "ahb0_gpu", + "ahb0_ss", "ahb0_sd", "ahb0_nand1", + "ahb0_nand0", "ahb0_sdram", + "ahb0_mipi_hsi", "ahb0_sata", "ahb0_ts", + "ahb0_spi0","ahb0_spi1", "ahb0_spi2", + "ahb0_spi3"; + }; + + ahb1_gates: clk@06000584 { + #clock-cells = <1>; + compatible = "allwinner,sun9i-a80-ahb1-gates-clk"; + reg = <0x06000584 0x4>; + clocks = <&ahb1>; + clock-output-names = "ahb1_usbotg", "ahb1_usbhci", + "ahb1_gmac", "ahb1_msgbox", + "ahb1_spinlock", "ahb1_hstimer", + "ahb1_dma"; + }; + + ahb2_gates: clk@06000588 { + #clock-cells = <1>; + compatible = "allwinner,sun9i-a80-ahb2-gates-clk"; + reg = <0x06000588 0x4>; + clocks = <&ahb2>; + clock-output-names = "ahb2_lcd0", "ahb2_lcd1", + "ahb2_edp", "ahb2_csi", "ahb2_hdmi", + "ahb2_de", "ahb2_mp", "ahb2_mipi_dsi"; + }; + + apb0_gates: clk@06000590 { + #clock-cells = <1>; + compatible = "allwinner,sun9i-a80-apb0-gates-clk"; + reg = <0x06000590 0x4>; + clocks = <&apb0>; + clock-output-names = "apb0_spdif", "apb0_pio", + "apb0_ac97", "apb0_i2s0", "apb0_i2s1", + "apb0_lradc", "apb0_gpadc", "apb0_twd", + "apb0_cirtx"; + }; + + apb1_gates: clk@06000594 { + #clock-cells = <1>; + compatible = "allwinner,sun9i-a80-apb1-gates-clk"; + reg = <0x06000594 0x4>; + clocks = <&apb1>; + clock-output-names = "apb1_i2c0", "apb1_i2c1", + "apb1_i2c2", "apb1_i2c3", "apb1_i2c4", + "apb1_uart0", "apb1_uart1", + "apb1_uart2", "apb1_uart3", + "apb1_uart4", "apb1_uart5"; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + /* + * map 64 bit address range down to 32 bits, + * as the peripherals are all under 512MB. + */ + ranges = <0 0 0 0x20000000>; + + gic: interrupt-controller@01c41000 { + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + reg = <0x01c41000 0x1000>, + <0x01c42000 0x1000>, + <0x01c44000 0x2000>, + <0x01c46000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <1 9 0xf04>; + }; + + ahb0_resets: reset@060005a0 { + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-clock-reset"; + reg = <0x060005a0 0x4>; + }; + + ahb1_resets: reset@060005a4 { + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-clock-reset"; + reg = <0x060005a4 0x4>; + }; + + ahb2_resets: reset@060005a8 { + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-clock-reset"; + reg = <0x060005a8 0x4>; + }; + + apb0_resets: reset@060005b0 { + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-clock-reset"; + reg = <0x060005b0 0x4>; + }; + + apb1_resets: reset@060005b4 { + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-clock-reset"; + reg = <0x060005b4 0x4>; + }; + + timer@06000c00 { + compatible = "allwinner,sun4i-a10-timer"; + reg = <0x06000c00 0xa0>; + interrupts = <0 18 4>, + <0 19 4>, + <0 20 4>, + <0 21 4>, + <0 22 4>, + <0 23 4>; + + clocks = <&osc24M>; + }; + + pio: pinctrl@06000800 { + compatible = "allwinner,sun9i-a80-pinctrl"; + reg = <0x06000800 0x400>; + interrupts = <0 11 4>, + <0 15 4>, + <0 16 4>, + <0 17 4>, + <0 120 4>; + clocks = <&apb0_gates 5>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + #size-cells = <0>; + #gpio-cells = <3>; + + i2c3_pins_a: i2c3@0 { + allwinner,pins = "PG10", "PG11"; + allwinner,function = "i2c3"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + uart0_pins_a: uart0@0 { + allwinner,pins = "PH12", "PH13"; + allwinner,function = "uart0"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + + uart4_pins_a: uart4@0 { + allwinner,pins = "PG12", "PG13", "PG14", "PG15"; + allwinner,function = "uart4"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + }; + + uart0: serial@07000000 { + compatible = "snps,dw-apb-uart"; + reg = <0x07000000 0x400>; + interrupts = <0 0 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb1_gates 16>; + resets = <&apb1_resets 16>; + status = "disabled"; + }; + + uart1: serial@07000400 { + compatible = "snps,dw-apb-uart"; + reg = <0x07000400 0x400>; + interrupts = <0 1 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb1_gates 17>; + resets = <&apb1_resets 17>; + status = "disabled"; + }; + + uart2: serial@07000800 { + compatible = "snps,dw-apb-uart"; + reg = <0x07000800 0x400>; + interrupts = <0 2 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb1_gates 18>; + resets = <&apb1_resets 18>; + status = "disabled"; + }; + + uart3: serial@07000c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x07000c00 0x400>; + interrupts = <0 3 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb1_gates 19>; + resets = <&apb1_resets 19>; + status = "disabled"; + }; + + uart4: serial@07001000 { + compatible = "snps,dw-apb-uart"; + reg = <0x07001000 0x400>; + interrupts = <0 4 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb1_gates 20>; + resets = <&apb1_resets 20>; + status = "disabled"; + }; + + uart5: serial@07001400 { + compatible = "snps,dw-apb-uart"; + reg = <0x07001400 0x400>; + interrupts = <0 5 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb1_gates 21>; + resets = <&apb1_resets 21>; + status = "disabled"; + }; + + i2c0: i2c@07002800 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x07002800 0x400>; + interrupts = <0 6 4>; + clocks = <&apb1_gates 0>; + resets = <&apb1_resets 0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@07002c00 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x07002c00 0x400>; + interrupts = <0 7 4>; + clocks = <&apb1_gates 1>; + resets = <&apb1_resets 1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@07003000 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x07003000 0x400>; + interrupts = <0 8 4>; + clocks = <&apb1_gates 2>; + resets = <&apb1_resets 2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c3: i2c@07003400 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x07003400 0x400>; + interrupts = <0 9 4>; + clocks = <&apb1_gates 3>; + resets = <&apb1_resets 3>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c4: i2c@07003800 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x07003800 0x400>; + interrupts = <0 10 4>; + clocks = <&apb1_gates 4>; + resets = <&apb1_resets 4>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + r_wdt: watchdog@08001000 { + compatible = "allwinner,sun6i-a31-wdt"; + reg = <0x08001000 0x20>; + interrupts = <0 36 4>; + }; + + r_uart: serial@08002800 { + compatible = "snps,dw-apb-uart"; + reg = <0x08002800 0x400>; + interrupts = <0 38 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc24M>; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/boot/dts/sunxi-common-regulators.dtsi b/arch/arm/boot/dts/sunxi-common-regulators.dtsi index 3d021efd1a38..d8876634f965 100644 --- a/arch/arm/boot/dts/sunxi-common-regulators.dtsi +++ b/arch/arm/boot/dts/sunxi-common-regulators.dtsi @@ -3,12 +3,48 @@ * * Copyright 2014 - Hans de Goede <hdegoede@redhat.com> * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this file; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. */ / { @@ -21,6 +57,13 @@ allwinner,pull = <0>; }; + usb0_vbus_pin_a: usb0_vbus_pin@0 { + allwinner,pins = "PB9"; + allwinner,function = "gpio_out"; + allwinner,drive = <0>; + allwinner,pull = <0>; + }; + usb1_vbus_pin_a: usb1_vbus_pin@0 { allwinner,pins = "PH6"; allwinner,function = "gpio_out"; @@ -44,11 +87,24 @@ regulator-name = "ahci-5v"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; + regulator-boot-on; enable-active-high; gpio = <&pio 1 8 0>; status = "disabled"; }; + reg_usb0_vbus: usb0-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&usb0_vbus_pin_a>; + regulator-name = "usb0-vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&pio 1 9 0>; + status = "disabled"; + }; + reg_usb1_vbus: usb1-vbus { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -86,4 +142,11 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; }; + + reg_vcc5v0: vcc5v0 { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; }; diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index 5c21d216515a..8b7aa0dcdc6e 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -15,6 +15,7 @@ aliases { rtc0 = "/i2c@7000d000/tps65913@58"; rtc1 = "/rtc@7000e000"; + serial0 = &uartd; }; memory { diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts index c7c6825f11fb..38acf78d7815 100644 --- a/arch/arm/boot/dts/tegra114-roth.dts +++ b/arch/arm/boot/dts/tegra114-roth.dts @@ -15,6 +15,10 @@ linux,initrd-end = <0x82800000>; }; + aliases { + serial0 = &uartd; + }; + firmware { trusted-foundations { compatible = "tlm,trusted-foundations"; @@ -916,8 +920,6 @@ regulator-name = "vddio-sdmmc3"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; - regulator-always-on; - regulator-boot-on; }; ldousb { @@ -962,7 +964,7 @@ sdhci@78000400 { status = "okay"; bus-width = <4>; - vmmc-supply = <&vddio_sdmmc3>; + vqmmc-supply = <&vddio_sdmmc3>; cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; power-gpios = <&gpio TEGRA_GPIO(H, 0) GPIO_ACTIVE_HIGH>; }; @@ -971,7 +973,6 @@ sdhci@78000600 { status = "okay"; bus-width = <8>; - vmmc-supply = <&vdd_1v8>; non-removable; }; diff --git a/arch/arm/boot/dts/tegra114-tn7.dts b/arch/arm/boot/dts/tegra114-tn7.dts index 963662145635..f91c2c9b2f94 100644 --- a/arch/arm/boot/dts/tegra114-tn7.dts +++ b/arch/arm/boot/dts/tegra114-tn7.dts @@ -15,6 +15,10 @@ linux,initrd-end = <0x82800000>; }; + aliases { + serial0 = &uartd; + }; + firmware { trusted-foundations { compatible = "tlm,trusted-foundations"; @@ -240,7 +244,6 @@ sdhci@78000600 { status = "okay"; bus-width = <8>; - vmmc-supply = <&vdd_1v8>; non-removable; }; diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 80b8eddb4105..4296b5398bf5 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -1,5 +1,6 @@ #include <dt-bindings/clock/tegra114-car.h> #include <dt-bindings/gpio/tegra-gpio.h> +#include <dt-bindings/memory/tegra114-mc.h> #include <dt-bindings/pinctrl/pinctrl-tegra.h> #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -9,13 +10,6 @@ compatible = "nvidia,tegra114"; interrupt-parent = <&gic>; - aliases { - serial0 = &uarta; - serial1 = &uartb; - serial2 = &uartc; - serial3 = &uartd; - }; - host1x@50000000 { compatible = "nvidia,tegra114-host1x", "simple-bus"; reg = <0x50000000 0x00028000>; @@ -57,6 +51,8 @@ resets = <&tegra_car 27>; reset-names = "dc"; + iommus = <&mc TEGRA_SWGROUP_DC>; + nvidia,head = <0>; rgb { @@ -74,6 +70,8 @@ resets = <&tegra_car 26>; reset-names = "dc"; + iommus = <&mc TEGRA_SWGROUP_DCB>; + nvidia,head = <1>; rgb { @@ -157,6 +155,11 @@ #reset-cells = <1>; }; + flow-controller@60007000 { + compatible = "nvidia,tegra114-flowctrl"; + reg = <0x60007000 0x1000>; + }; + apbdma: dma@6000a000 { compatible = "nvidia,tegra114-apbdma"; reg = <0x6000a000 0x1400>; @@ -500,15 +503,15 @@ reset-names = "fuse"; }; - iommu@70019010 { - compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu"; - reg = <0x70019010 0x02c - 0x700191f0 0x010 - 0x70019228 0x074>; - nvidia,#asids = <4>; - dma-window = <0 0x40000000>; - nvidia,swgroups = <0x18659fe>; - nvidia,ahb = <&ahb>; + mc: memory-controller@70019000 { + compatible = "nvidia,tegra114-mc"; + reg = <0x70019000 0x1000>; + clocks = <&tegra_car TEGRA114_CLK_MC>; + clock-names = "mc"; + + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + + #iommu-cells = <1>; }; ahub@70080000 { diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index 624b0fba2d0a..4eb540be368f 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -10,12 +10,33 @@ aliases { rtc0 = "/i2c@0,7000d000/pmic@40"; rtc1 = "/rtc@0,7000e000"; + serial0 = &uartd; }; memory { reg = <0x0 0x80000000 0x0 0x80000000>; }; + pcie-controller@0,01003000 { + status = "okay"; + + avddio-pex-supply = <&vdd_1v05_run>; + dvddio-pex-supply = <&vdd_1v05_run>; + avdd-pex-pll-supply = <&vdd_1v05_run>; + hvdd-pex-supply = <&vdd_3v3_lp0>; + hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>; + vddio-pex-ctl-supply = <&vdd_3v3_lp0>; + avdd-pll-erefe-supply = <&avdd_1v05_run>; + + pci@1,0 { + status = "okay"; + }; + + pci@2,0 { + status = "okay"; + }; + }; + host1x@0,50000000 { hdmi@0,54280000 { status = "okay"; @@ -31,10 +52,10 @@ }; pinmux: pinmux@0,70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&state_default>; + pinctrl-names = "boot"; + pinctrl-0 = <&state_boot>; - state_default: pinmux { + state_boot: pinmux { clk_32k_out_pa0 { nvidia,pins = "clk_32k_out_pa0"; nvidia,function = "soc"; @@ -1231,6 +1252,41 @@ nvidia,tristate = <TEGRA_PIN_DISABLE>; nvidia,enable-input = <TEGRA_PIN_DISABLE>; }; + pex_l0_rst_n_pdd1 { + nvidia,pins = "pex_l0_rst_n_pdd1"; + nvidia,function = "pe0"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pex_l0_clkreq_n_pdd2 { + nvidia,pins = "pex_l0_clkreq_n_pdd2"; + nvidia,function = "pe0"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pex_wake_n_pdd3 { + nvidia,pins = "pex_wake_n_pdd3"; + nvidia,function = "pe"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + pex_l1_rst_n_pdd5 { + nvidia,pins = "pex_l1_rst_n_pdd5"; + nvidia,function = "pe1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + pex_l1_clkreq_n_pdd6 { + nvidia,pins = "pex_l1_clkreq_n_pdd6"; + nvidia,function = "pe1"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; clk3_out_pee0 { nvidia,pins = "clk3_out_pee0"; nvidia,function = "extperiph3"; @@ -1515,7 +1571,7 @@ regulator-always-on; }; - ldo0 { + avdd_1v05_run: ldo0 { regulator-name = "+1.05V_RUN_AVDD"; regulator-min-microvolt = <1050000>; regulator-max-microvolt = <1050000>; @@ -1619,6 +1675,18 @@ nvidia,sys-clock-req-active-high; }; + /* Serial ATA */ + sata@0,70020000 { + status = "okay"; + + hvdd-supply = <&vdd_3v3_lp0>; + vddio-supply = <&vdd_1v05_run>; + avdd-supply = <&vdd_1v05_run>; + + target-5v-supply = <&vdd_5v0_sata>; + target-12v-supply = <&vdd_12v0_sata>; + }; + padctl@0,7009f000 { pinctrl-0 = <&padctl_default>; pinctrl-names = "default"; @@ -1828,6 +1896,29 @@ enable-active-high; vin-supply = <&vdd_5v0_sys>; }; + + /* Molex power connector */ + vdd_5v0_sata: regulator@13 { + compatible = "regulator-fixed"; + reg = <13>; + regulator-name = "+5V_SATA"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_12v0_sata: regulator@14 { + compatible = "regulator-fixed"; + reg = <14>; + regulator-name = "+12V_SATA"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&gpio TEGRA_GPIO(EE, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_mux>; + }; }; sound { @@ -1851,4 +1942,48 @@ <&tegra_car TEGRA124_CLK_EXTERN1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; + + thermal-zones { + cpu { + trips { + trip@0 { + temperature = <101000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + /* There are currently no cooling maps because there are no cooling devices */ + }; + }; + + mem { + trips { + trip@0 { + temperature = <101000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + /* There are currently no cooling maps because there are no cooling devices */ + }; + }; + + gpu { + trips { + trip@0 { + temperature = <101000>; + hysteresis = <0>; + type = "critical"; + }; + }; + + cooling-maps { + /* There are currently no cooling maps because there are no cooling devices */ + }; + }; + }; }; diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts b/arch/arm/boot/dts/tegra124-nyan-big.dts new file mode 100644 index 000000000000..53181d310247 --- /dev/null +++ b/arch/arm/boot/dts/tegra124-nyan-big.dts @@ -0,0 +1,1137 @@ +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include "tegra124.dtsi" + +/ { + model = "Acer Chromebook 13 CB5-311"; + compatible = "google,nyan-big", "nvidia,tegra124"; + + aliases { + rtc0 = "/i2c@0,7000d000/pmic@40"; + rtc1 = "/rtc@0,7000e000"; + serial0 = &uarta; + }; + + memory { + reg = <0x0 0x80000000 0x0 0x80000000>; + }; + + host1x@0,50000000 { + hdmi@0,54280000 { + status = "okay"; + + vdd-supply = <&vdd_3v3_hdmi>; + pll-supply = <&vdd_hdmi_pll>; + hdmi-supply = <&vdd_5v0_hdmi>; + + nvidia,ddc-i2c-bus = <&hdmi_ddc>; + nvidia,hpd-gpio = + <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; + }; + + sor@0,54540000 { + status = "okay"; + + nvidia,dpaux = <&dpaux>; + nvidia,panel = <&panel>; + }; + + dpaux@0,545c0000 { + vdd-supply = <&vdd_3v3_panel>; + status = "okay"; + }; + }; + + pinmux@0,70000868 { + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_default>; + + pinmux_default: common { + dap_mclk1_pw4 { + nvidia,pins = "dap_mclk1_pw4"; + nvidia,function = "extperiph1"; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + dap2_din_pa4 { + nvidia,pins = "dap2_din_pa4"; + nvidia,function = "i2s1"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + dap2_dout_pa5 { + nvidia,pins = "dap2_dout_pa5", + "dap2_fs_pa2", + "dap2_sclk_pa3"; + nvidia,function = "i2s1"; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + dvfs_pwm_px0 { + nvidia,pins = "dvfs_pwm_px0", + "dvfs_clk_px2"; + nvidia,function = "cldvfs"; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + ulpi_clk_py0 { + nvidia,pins = "ulpi_clk_py0", + "ulpi_nxt_py2", + "ulpi_stp_py3"; + nvidia,function = "spi1"; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + ulpi_dir_py1 { + nvidia,pins = "ulpi_dir_py1"; + nvidia,function = "spi1"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + cam_i2c_scl_pbb1 { + nvidia,pins = "cam_i2c_scl_pbb1", + "cam_i2c_sda_pbb2"; + nvidia,function = "i2c3"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + gen2_i2c_scl_pt5 { + nvidia,pins = "gen2_i2c_scl_pt5", + "gen2_i2c_sda_pt6"; + nvidia,function = "i2c2"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + pg4 { + nvidia,pins = "pg4", + "pg5", + "pg6", + "pi3"; + nvidia,function = "spi4"; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + pg7 { + nvidia,pins = "pg7"; + nvidia,function = "spi4"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + ph1 { + nvidia,pins = "ph1"; + nvidia,function = "pwm1"; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + pk0 { + nvidia,pins = "pk0", + "kb_row15_ps7", + "clk_32k_out_pa0"; + nvidia,function = "soc"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sdmmc1_clk_pz0 { + nvidia,pins = "sdmmc1_clk_pz0"; + nvidia,function = "sdmmc1"; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + sdmmc1_cmd_pz1 { + nvidia,pins = "sdmmc1_cmd_pz1", + "sdmmc1_dat0_py7", + "sdmmc1_dat1_py6", + "sdmmc1_dat2_py5", + "sdmmc1_dat3_py4"; + nvidia,function = "sdmmc1"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + sdmmc3_clk_pa6 { + nvidia,pins = "sdmmc3_clk_pa6"; + nvidia,function = "sdmmc3"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + sdmmc3_cmd_pa7 { + nvidia,pins = "sdmmc3_cmd_pa7", + "sdmmc3_dat0_pb7", + "sdmmc3_dat1_pb6", + "sdmmc3_dat2_pb5", + "sdmmc3_dat3_pb4", + "kb_col4_pq4", + "sdmmc3_clk_lb_out_pee4", + "sdmmc3_clk_lb_in_pee5", + "sdmmc3_cd_n_pv2"; + nvidia,function = "sdmmc3"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + sdmmc4_clk_pcc4 { + nvidia,pins = "sdmmc4_clk_pcc4"; + nvidia,function = "sdmmc4"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + sdmmc4_cmd_pt7 { + nvidia,pins = "sdmmc4_cmd_pt7", + "sdmmc4_dat0_paa0", + "sdmmc4_dat1_paa1", + "sdmmc4_dat2_paa2", + "sdmmc4_dat3_paa3", + "sdmmc4_dat4_paa4", + "sdmmc4_dat5_paa5", + "sdmmc4_dat6_paa6", + "sdmmc4_dat7_paa7"; + nvidia,function = "sdmmc4"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + pwr_i2c_scl_pz6 { + nvidia,pins = "pwr_i2c_scl_pz6", + "pwr_i2c_sda_pz7"; + nvidia,function = "i2cpwr"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + jtag_rtck { + nvidia,pins = "jtag_rtck"; + nvidia,function = "rtck"; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + clk_32k_in { + nvidia,pins = "clk_32k_in"; + nvidia,function = "clk"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + core_pwr_req { + nvidia,pins = "core_pwr_req"; + nvidia,function = "pwron"; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + cpu_pwr_req { + nvidia,pins = "cpu_pwr_req"; + nvidia,function = "cpu"; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + pwr_int_n { + nvidia,pins = "pwr_int_n"; + nvidia,function = "pmi"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + reset_out_n { + nvidia,pins = "reset_out_n"; + nvidia,function = "reset_out_n"; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + clk3_out_pee0 { + nvidia,pins = "clk3_out_pee0"; + nvidia,function = "extperiph3"; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + gen1_i2c_sda_pc5 { + nvidia,pins = "gen1_i2c_sda_pc5", + "gen1_i2c_scl_pc4"; + nvidia,function = "i2c1"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + hdmi_cec_pee3 { + nvidia,pins = "hdmi_cec_pee3"; + nvidia,function = "cec"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_DISABLE>; + }; + hdmi_int_pn7 { + nvidia,pins = "hdmi_int_pn7"; + nvidia,function = "rsvd1"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + }; + ddc_scl_pv4 { + nvidia,pins = "ddc_scl_pv4", + "ddc_sda_pv5"; + nvidia,function = "i2c4"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + nvidia,rcv-sel = <TEGRA_PIN_ENABLE>; + }; + kb_row10_ps2 { + nvidia,pins = "kb_row10_ps2"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_row9_ps1 { + nvidia,pins = "kb_row9_ps1"; + nvidia,function = "uarta"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + usb_vbus_en0_pn4 { + nvidia,pins = "usb_vbus_en0_pn4", + "usb_vbus_en1_pn5"; + nvidia,function = "usb"; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,lock = <TEGRA_PIN_DISABLE>; + nvidia,open-drain = <TEGRA_PIN_ENABLE>; + }; + drive_sdio1 { + nvidia,pins = "drive_sdio1"; + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,pull-down-strength = <36>; + nvidia,pull-up-strength = <20>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>; + }; + drive_sdio3 { + nvidia,pins = "drive_sdio3"; + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,pull-down-strength = <22>; + nvidia,pull-up-strength = <36>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + }; + drive_gma { + nvidia,pins = "drive_gma"; + nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; + nvidia,schmitt = <TEGRA_PIN_DISABLE>; + nvidia,pull-down-strength = <2>; + nvidia,pull-up-strength = <1>; + nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; + nvidia,drive-type = <1>; + }; + codec_irq_l { + nvidia,pins = "ph4"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lcd_bl_en { + nvidia,pins = "ph2"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + touch_irq_l { + nvidia,pins = "gpio_w3_aud_pw3"; + nvidia,function = "spi6"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + tpm_davint_l { + nvidia,pins = "ph6"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ts_irq_l { + nvidia,pins = "pk2"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + ts_reset_l { + nvidia,pins = "pk4"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ts_shdn_l { + nvidia,pins = "pk1"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ph7 { + nvidia,pins = "ph7"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + kb_col0_ap { + nvidia,pins = "kb_col0_pq0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + lid_open { + nvidia,pins = "kb_row4_pr4"; + nvidia,function = "rsvd3"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + en_vdd_sd { + nvidia,pins = "kb_row0_pr0"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + ac_ok { + nvidia,pins = "pj0"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + sensor_irq_l { + nvidia,pins = "pi6"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + wifi_en { + nvidia,pins = "gpio_x7_aud_px7"; + nvidia,function = "rsvd4"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + en_vdd_bl { + nvidia,pins = "dap3_dout_pp2"; + nvidia,function = "i2s2"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + en_vdd_hdmi { + nvidia,pins = "spdif_in_pk6"; + nvidia,function = "spdif"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + soc_warm_reset_l { + nvidia,pins = "pi5"; + nvidia,function = "gmi"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + hp_det_l { + nvidia,pins = "pi7"; + nvidia,function = "rsvd1"; + nvidia,pull = <TEGRA_PIN_PULL_NONE>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + mic_det_l { + nvidia,pins = "kb_row7_pr7"; + nvidia,function = "rsvd2"; + nvidia,pull = <TEGRA_PIN_PULL_UP>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_ENABLE>; + }; + }; + }; + + serial@0,70006000 { + /* Debug connector on the bottom of the board near SD card. */ + status = "okay"; + }; + + pwm@0,7000a000 { + status = "okay"; + }; + + i2c@0,7000c000 { + status = "okay"; + clock-frequency = <100000>; + + acodec: audio-codec@10 { + compatible = "maxim,max98090"; + reg = <0x10>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>; + }; + + temperature-sensor@4c { + compatible = "ti,tmp451"; + reg = <0x4c>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>; + + #thermal-sensor-cells = <1>; + }; + }; + + i2c@0,7000c400 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@0,7000c500 { + status = "okay"; + clock-frequency = <400000>; + + tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + }; + }; + + hdmi_ddc: i2c@0,7000c700 { + status = "okay"; + clock-frequency = <100000>; + }; + + i2c@0,7000d000 { + status = "okay"; + clock-frequency = <400000>; + + pmic: pmic@40 { + compatible = "ams,as3722"; + reg = <0x40>; + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; + + ams,system-power-controller; + + #interrupt-cells = <2>; + interrupt-controller; + + gpio-controller; + #gpio-cells = <2>; + + pinctrl-names = "default"; + pinctrl-0 = <&as3722_default>; + + as3722_default: pinmux { + gpio0 { + pins = "gpio0"; + function = "gpio"; + bias-pull-down; + }; + + gpio1 { + pins = "gpio1"; + function = "gpio"; + bias-pull-up; + }; + + gpio2_4_7 { + pins = "gpio2", "gpio4", "gpio7"; + function = "gpio"; + bias-pull-up; + }; + + gpio3_6 { + pins = "gpio3", "gpio6"; + bias-high-impedance; + }; + + gpio5 { + pins = "gpio5"; + function = "clk32k-out"; + bias-pull-down; + }; + }; + + regulators { + vsup-sd2-supply = <&vdd_5v0_sys>; + vsup-sd3-supply = <&vdd_5v0_sys>; + vsup-sd4-supply = <&vdd_5v0_sys>; + vsup-sd5-supply = <&vdd_5v0_sys>; + vin-ldo0-supply = <&vdd_1v35_lp0>; + vin-ldo1-6-supply = <&vdd_3v3_run>; + vin-ldo2-5-7-supply = <&vddio_1v8>; + vin-ldo3-4-supply = <&vdd_3v3_sys>; + vin-ldo9-10-supply = <&vdd_5v0_sys>; + vin-ldo11-supply = <&vdd_3v3_run>; + + sd0 { + regulator-name = "+VDD_CPU_AP"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-min-microamp = <3500000>; + regulator-max-microamp = <3500000>; + regulator-always-on; + regulator-boot-on; + ams,ext-control = <2>; + }; + + sd1 { + regulator-name = "+VDD_CORE"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1350000>; + regulator-min-microamp = <2500000>; + regulator-max-microamp = <4000000>; + regulator-always-on; + regulator-boot-on; + ams,ext-control = <1>; + }; + + vdd_1v35_lp0: sd2 { + regulator-name = "+1.35V_LP0(sd2)"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + sd3 { + regulator-name = "+1.35V_LP0(sd3)"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v05_run: sd4 { + regulator-name = "+1.05V_RUN"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + vddio_1v8: sd5 { + regulator-name = "+1.8V_VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + sd6 { + regulator-name = "+VDD_GPU_AP"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <1200000>; + regulator-min-microamp = <3500000>; + regulator-max-microamp = <3500000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo0 { + regulator-name = "+1.05V_RUN_AVDD"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + regulator-boot-on; + regulator-always-on; + ams,ext-control = <1>; + }; + + ldo1 { + regulator-name = "+1.8V_RUN_CAM"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo2 { + regulator-name = "+1.2V_GEN_AVDD"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3 { + regulator-name = "+1.00V_LP0_VDD_RTC"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-boot-on; + regulator-always-on; + ams,enable-tracking; + }; + + vdd_run_cam: ldo4 { + regulator-name = "+3.3V_RUN_CAM"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo5 { + regulator-name = "+1.2V_RUN_CAM_FRONT"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + vddio_sdmmc3: ldo6 { + regulator-name = "+VDDIO_SDMMC3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + ldo7 { + regulator-name = "+1.05V_RUN_CAM_REAR"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + ldo9 { + regulator-name = "+2.8V_RUN_TOUCH"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo10 { + regulator-name = "+2.8V_RUN_CAM_AF"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + ldo11 { + regulator-name = "+1.8V_RUN_VPP_FUSE"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; + }; + + spi@0,7000d400 { + status = "okay"; + + cros_ec: cros-ec@0 { + compatible = "google,cros-ec-spi"; + spi-max-frequency = <3000000>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>; + reg = <0>; + + google,cros-ec-spi-msg-delay = <2000>; + + i2c-tunnel { + compatible = "google,cros-ec-i2c-tunnel"; + #address-cells = <1>; + #size-cells = <0>; + + google,remote-bus = <0>; + + charger: bq24735@9 { + compatible = "ti,bq24735"; + reg = <0x9>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(J, 0) + GPIO_ACTIVE_HIGH>; + ti,ac-detect-gpios = <&gpio + TEGRA_GPIO(J, 0) + GPIO_ACTIVE_HIGH>; + }; + + battery: sbs-battery@b { + compatible = "sbs,sbs-battery"; + reg = <0xb>; + sbs,i2c-retry-count = <2>; + sbs,poll-retry-count = <10>; + power-supplies = <&charger>; + }; + }; + }; + }; + + spi@0,7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + + flash@0 { + compatible = "winbond,w25q32dw"; + reg = <0>; + }; + }; + + pmc@0,7000e400 { + nvidia,invert-interrupt; + nvidia,suspend-mode = <0>; + nvidia,cpu-pwr-good-time = <500>; + nvidia,cpu-pwr-off-time = <300>; + nvidia,core-pwr-good-time = <641 3845>; + nvidia,core-pwr-off-time = <61036>; + nvidia,core-power-req-active-high; + nvidia,sys-clock-req-active-high; + }; + + hda@0,70030000 { + status = "okay"; + }; + + sdhci@0,700b0000 { /* WiFi/BT on this bus */ + status = "okay"; + power-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>; + bus-width = <4>; + no-1-8-v; + non-removable; + }; + + sdhci@0,700b0400 { /* SD Card on this bus */ + status = "okay"; + cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; + bus-width = <4>; + no-1-8-v; + vqmmc-supply = <&vddio_sdmmc3>; + }; + + sdhci@0,700b0600 { /* eMMC on this bus */ + status = "okay"; + bus-width = <8>; + no-1-8-v; + non-removable; + }; + + ahub@0,70300000 { + i2s@0,70301100 { + status = "okay"; + }; + }; + + usb@0,7d000000 { /* Rear external USB port. */ + status = "okay"; + }; + + usb-phy@0,7d000000 { + status = "okay"; + vbus-supply = <&vdd_usb1_vbus>; + }; + + usb@0,7d004000 { /* Internal webcam. */ + status = "okay"; + }; + + usb-phy@0,7d004000 { + status = "okay"; + vbus-supply = <&vdd_run_cam>; + }; + + usb@0,7d008000 { /* Left external USB port. */ + status = "okay"; + }; + + usb-phy@0,7d008000 { + status = "okay"; + vbus-supply = <&vdd_usb3_vbus>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + + enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + power-supply = <&vdd_led>; + pwms = <&pwm 1 1000000>; + + default-brightness-level = <224>; + brightness-levels = + < 0 1 2 3 4 5 6 7 + 8 9 10 11 12 13 14 15 + 16 17 18 19 20 21 22 23 + 24 25 26 27 28 29 30 31 + 32 33 34 35 36 37 38 39 + 40 41 42 43 44 45 46 47 + 48 49 50 51 52 53 54 55 + 56 57 58 59 60 61 62 63 + 64 65 66 67 68 69 70 71 + 72 73 74 75 76 77 78 79 + 80 81 82 83 84 85 86 87 + 88 89 90 91 92 93 94 95 + 96 97 98 99 100 101 102 103 + 104 105 106 107 108 109 110 111 + 112 113 114 115 116 117 118 119 + 120 121 122 123 124 125 126 127 + 128 129 130 131 132 133 134 135 + 136 137 138 139 140 141 142 143 + 144 145 146 147 148 149 150 151 + 152 153 154 155 156 157 158 159 + 160 161 162 163 164 165 166 167 + 168 169 170 171 172 173 174 175 + 176 177 178 179 180 181 182 183 + 184 185 186 187 188 189 190 191 + 192 193 194 195 196 197 198 199 + 200 201 202 203 204 205 206 207 + 208 209 210 211 212 213 214 215 + 216 217 218 219 220 221 222 223 + 224 225 226 227 228 229 230 231 + 232 233 234 235 236 237 238 239 + 240 241 242 243 244 245 246 247 + 248 249 250 251 252 253 254 255 + 256>; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + clk32k_in: clock@0 { + compatible = "fixed-clock"; + reg = <0>; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + lid { + label = "Lid"; + gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>; + linux,input-type = <5>; + linux,code = <KEY_RESERVED>; + debounce-interval = <1>; + gpio-key,wakeup; + }; + + power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = <KEY_POWER>; + debounce-interval = <30>; + gpio-key,wakeup; + }; + }; + + panel: panel { + compatible = "auo,b133xtn01"; + + backlight = <&backlight>; + ddc-i2c-bus = <&dpaux>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_mux: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "+VDD_MUX"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_5v0_sys: regulator@1 { + compatible = "regulator-fixed"; + reg = <1>; + regulator-name = "+5V_SYS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; + + vdd_3v3_sys: regulator@2 { + compatible = "regulator-fixed"; + reg = <2>; + regulator-name = "+3.3V_SYS"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd_mux>; + }; + + vdd_3v3_run: regulator@3 { + compatible = "regulator-fixed"; + reg = <3>; + regulator-name = "+3.3V_RUN"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_3v3_hdmi: regulator@4 { + compatible = "regulator-fixed"; + reg = <4>; + regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vdd_3v3_run>; + }; + + vdd_led: regulator@5 { + compatible = "regulator-fixed"; + reg = <5>; + regulator-name = "+VDD_LED"; + gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_mux>; + }; + + vdd_5v0_ts: regulator@6 { + compatible = "regulator-fixed"; + reg = <6>; + regulator-name = "+5V_VDD_TS_SW"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_usb1_vbus: regulator@7 { + compatible = "regulator-fixed"; + reg = <7>; + regulator-name = "+5V_USB_HS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_usb3_vbus: regulator@8 { + compatible = "regulator-fixed"; + reg = <8>; + regulator-name = "+5V_USB_SS"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; + enable-active-high; + gpio-open-drain; + vin-supply = <&vdd_5v0_sys>; + }; + + vdd_3v3_panel: regulator@9 { + compatible = "regulator-fixed"; + reg = <9>; + regulator-name = "+3.3V_PANEL"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pmic 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_run>; + }; + + vdd_3v3_lp0: regulator@10 { + compatible = "regulator-fixed"; + reg = <10>; + regulator-name = "+3.3V_LP0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + /* + * TODO: find a way to wire this up with the USB EHCI + * controllers so that it can be enabled on demand. + */ + regulator-always-on; + gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_3v3_sys>; + }; + + vdd_hdmi_pll: regulator@11 { + compatible = "regulator-fixed"; + reg = <11>; + regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; + vin-supply = <&vdd_1v05_run>; + }; + + vdd_5v0_hdmi: regulator@12 { + compatible = "regulator-fixed"; + reg = <12>; + regulator-name = "+5V_HDMI_CON"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; + }; + + sound { + compatible = "nvidia,tegra-audio-max98090-nyan-big", + "nvidia,tegra-audio-max98090"; + nvidia,model = "Acer Chromebook 13"; + + nvidia,audio-routing = + "Headphones", "HPR", + "Headphones", "HPL", + "Speakers", "SPKR", + "Speakers", "SPKL", + "Mic Jack", "MICBIAS", + "DMICL", "Int Mic", + "DMICR", "Int Mic", + "IN34", "Mic Jack"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&acodec>; + + clocks = <&tegra_car TEGRA124_CLK_PLL_A>, + <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA124_CLK_EXTERN1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(I, 7) GPIO_ACTIVE_HIGH>; + }; +}; + +#include "cros-ec-keyboard.dtsi" diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts index 70ad91d1a20b..5c3f7813360d 100644 --- a/arch/arm/boot/dts/tegra124-venice2.dts +++ b/arch/arm/boot/dts/tegra124-venice2.dts @@ -10,6 +10,7 @@ aliases { rtc0 = "/i2c@0,7000d000/pmic@40"; rtc1 = "/rtc@0,7000e000"; + serial0 = &uarta; }; memory { @@ -36,17 +37,17 @@ nvidia,panel = <&panel>; }; - dpaux: dpaux@0,545c0000 { + dpaux@0,545c0000 { vdd-supply = <&vdd_3v3_panel>; status = "okay"; }; }; pinmux: pinmux@0,70000868 { - pinctrl-names = "default"; - pinctrl-0 = <&pinmux_default>; + pinctrl-names = "boot"; + pinctrl-0 = <&pinmux_boot>; - pinmux_default: common { + pinmux_boot: common { dap_mclk1_pw4 { nvidia,pins = "dap_mclk1_pw4"; nvidia,function = "extperiph1"; @@ -587,7 +588,7 @@ status = "okay"; }; - pwm: pwm@0,7000a000 { + pwm@0,7000a000 { status = "okay"; }; @@ -606,6 +607,14 @@ i2c@0,7000c400 { status = "okay"; clock-frequency = <100000>; + + trackpad@4b { + compatible = "atmel,maxtouch"; + reg = <0x4b>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_LOW>; + linux,gpio-keymap = <0 0 0 BTN_LEFT>; + }; }; i2c@0,7000c500 { diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 03916efd6fa9..4be06c6ea0c8 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -1,8 +1,10 @@ #include <dt-bindings/clock/tegra124-car.h> #include <dt-bindings/gpio/tegra-gpio.h> +#include <dt-bindings/memory/tegra124-mc.h> #include <dt-bindings/pinctrl/pinctrl-tegra.h> #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/thermal/tegra124-soctherm.h> #include "skeleton.dtsi" @@ -12,6 +14,72 @@ #address-cells = <2>; #size-cells = <2>; + pcie-controller@0,01003000 { + compatible = "nvidia,tegra124-pcie"; + device_type = "pci"; + reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */ + 0x0 0x01003800 0x0 0x00000800 /* AFI registers */ + 0x0 0x02000000 0x0 0x10000000>; /* configuration space */ + reg-names = "pads", "afi", "cs"; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ + interrupt-names = "intr", "msi"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + + bus-range = <0x00 0xff>; + #address-cells = <3>; + #size-cells = <2>; + + ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */ + 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */ + 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */ + 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */ + 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ + + clocks = <&tegra_car TEGRA124_CLK_PCIE>, + <&tegra_car TEGRA124_CLK_AFI>, + <&tegra_car TEGRA124_CLK_PLL_E>, + <&tegra_car TEGRA124_CLK_CML0>; + clock-names = "pex", "afi", "pll_e", "cml"; + resets = <&tegra_car 70>, + <&tegra_car 72>, + <&tegra_car 74>; + reset-names = "pex", "afi", "pcie_x"; + status = "disabled"; + + phys = <&padctl TEGRA_XUSB_PADCTL_PCIE>; + phy-names = "pcie"; + + pci@1,0 { + device_type = "pci"; + assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; + reg = <0x000800 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <2>; + }; + + pci@2,0 { + device_type = "pci"; + assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; + reg = <0x001000 0 0 0 0>; + status = "disabled"; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + nvidia,num-lanes = <1>; + }; + }; + host1x@0,50000000 { compatible = "nvidia,tegra124-host1x", "simple-bus"; reg = <0x0 0x50000000 0x0 0x00034000>; @@ -36,6 +104,8 @@ resets = <&tegra_car 27>; reset-names = "dc"; + iommus = <&mc TEGRA_SWGROUP_DC>; + nvidia,head = <0>; }; @@ -49,6 +119,8 @@ resets = <&tegra_car 26>; reset-names = "dc"; + iommus = <&mc TEGRA_SWGROUP_DCB>; + nvidia,head = <1>; }; @@ -78,7 +150,7 @@ status = "disabled"; }; - dpaux@0,545c0000 { + dpaux: dpaux@0,545c0000 { compatible = "nvidia,tegra124-dpaux"; reg = <0x0 0x545c0000 0x0 0x00040000>; interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; @@ -137,6 +209,11 @@ #reset-cells = <1>; }; + flow-controller@0,60007000 { + compatible = "nvidia,tegra124-flowctrl"; + reg = <0x0 0x60007000 0x0 0x1000>; + }; + gpio: gpio@0,6000d000 { compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; reg = <0x0 0x6000d000 0x0 0x1000>; @@ -204,7 +281,8 @@ pinmux: pinmux@0,70000868 { compatible = "nvidia,tegra124-pinmux"; reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ - <0x0 0x70003000 0x0 0x434>; /* Mux registers */ + <0x0 0x70003000 0x0 0x434>, /* Mux registers */ + <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */ }; /* @@ -215,7 +293,7 @@ * the APB DMA based serial driver, the comptible is * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". */ - serial@0,70006000 { + uarta: serial@0,70006000 { compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; reg = <0x0 0x70006000 0x0 0x40>; reg-shift = <2>; @@ -228,7 +306,7 @@ status = "disabled"; }; - serial@0,70006040 { + uartb: serial@0,70006040 { compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; reg = <0x0 0x70006040 0x0 0x40>; reg-shift = <2>; @@ -241,7 +319,7 @@ status = "disabled"; }; - serial@0,70006200 { + uartc: serial@0,70006200 { compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; reg = <0x0 0x70006200 0x0 0x40>; reg-shift = <2>; @@ -254,7 +332,7 @@ status = "disabled"; }; - serial@0,70006300 { + uartd: serial@0,70006300 { compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; reg = <0x0 0x70006300 0x0 0x40>; reg-shift = <2>; @@ -267,7 +345,7 @@ status = "disabled"; }; - pwm@0,7000a000 { + pwm: pwm@0,7000a000 { compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; reg = <0x0 0x7000a000 0x0 0x100>; #pwm-cells = <2>; @@ -480,6 +558,42 @@ reset-names = "fuse"; }; + mc: memory-controller@0,70019000 { + compatible = "nvidia,tegra124-mc"; + reg = <0x0 0x70019000 0x0 0x1000>; + clocks = <&tegra_car TEGRA124_CLK_MC>; + clock-names = "mc"; + + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + + #iommu-cells = <1>; + }; + + sata@0,70020000 { + compatible = "nvidia,tegra124-ahci"; + + reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ + <0x0 0x70020000 0x0 0x7000>; /* SATA */ + + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&tegra_car TEGRA124_CLK_SATA>, + <&tegra_car TEGRA124_CLK_SATA_OOB>, + <&tegra_car TEGRA124_CLK_CML1>, + <&tegra_car TEGRA124_CLK_PLL_E>; + clock-names = "sata", "sata-oob", "cml1", "pll_e"; + + resets = <&tegra_car 124>, + <&tegra_car 123>, + <&tegra_car 129>; + reset-names = "sata", "sata-oob", "sata-cold"; + + phys = <&padctl TEGRA_XUSB_PADCTL_SATA>; + phy-names = "sata-phy"; + + status = "disabled"; + }; + hda@0,70030000 { compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda"; reg = <0x0 0x70030000 0x0 0x10000>; @@ -544,6 +658,18 @@ status = "disabled"; }; + soctherm: thermal-sensor@0,700e2000 { + compatible = "nvidia,tegra124-soctherm"; + reg = <0x0 0x700e2000 0x0 0x1000>; + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, + <&tegra_car TEGRA124_CLK_SOC_THERM>; + clock-names = "tsensor", "soctherm"; + resets = <&tegra_car 78>; + reset-names = "soctherm"; + #thermal-sensor-cells = <1>; + }; + ahub@0,70300000 { compatible = "nvidia,tegra124-ahub"; reg = <0x0 0x70300000 0x0 0x200>, @@ -785,6 +911,40 @@ }; }; + thermal-zones { + cpu { + polling-delay-passive = <1000>; + polling-delay = <1000>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; + }; + + mem { + polling-delay-passive = <1000>; + polling-delay = <1000>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; + }; + + gpu { + polling-delay-passive = <1000>; + polling-delay = <1000>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; + }; + + pllx { + polling-delay-passive = <1000>; + polling-delay = <1000>; + + thermal-sensors = + <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; + }; + }; + timer { compatible = "arm,armv7-timer"; interrupts = <GIC_PPI 13 diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts index a37279af687c..b926a07b9443 100644 --- a/arch/arm/boot/dts/tegra20-harmony.dts +++ b/arch/arm/boot/dts/tegra20-harmony.dts @@ -10,6 +10,7 @@ aliases { rtc0 = "/i2c@7000d000/tps6586x@34"; rtc1 = "/rtc@7000e000"; + serial0 = &uartd; }; memory { diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts b/arch/arm/boot/dts/tegra20-iris-512.dts index 8cfb83f42e1f..1dd7d7bfdfcc 100644 --- a/arch/arm/boot/dts/tegra20-iris-512.dts +++ b/arch/arm/boot/dts/tegra20-iris-512.dts @@ -6,6 +6,11 @@ model = "Toradex Colibri T20 512MB on Iris"; compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20"; + aliases { + serial0 = &uarta; + serial1 = &uartd; + }; + host1x@50000000 { hdmi@54280000 { status = "okay"; diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts index 1b7c56b33aca..9b87526ab0b7 100644 --- a/arch/arm/boot/dts/tegra20-medcom-wide.dts +++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts @@ -6,6 +6,10 @@ model = "Avionic Design Medcom-Wide board"; compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20"; + aliases { + serial0 = &uartd; + }; + pwm@7000a000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index d4438e30de45..ed7e1009326c 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -10,6 +10,8 @@ aliases { rtc0 = "/i2c@7000d000/tps6586x@34"; rtc1 = "/rtc@7000e000"; + serial0 = &uarta; + serial1 = &uartc; }; memory { diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index a1d4bf9895d7..ea282c7c0ca5 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -10,6 +10,7 @@ aliases { rtc0 = "/i2c@7000d000/tps6586x@34"; rtc1 = "/rtc@7000e000"; + serial0 = &uartd; }; memory { diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index 80e7d386ce34..13d4e6185275 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -7,6 +7,7 @@ aliases { rtc0 = "/i2c@7000d000/tps6586x@34"; rtc1 = "/rtc@7000e000"; + serial0 = &uartd; }; memory { diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index 5ad87979ab13..d99af4ef9c64 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -10,6 +10,7 @@ aliases { rtc0 = "/i2c@7000c500/rtc@56"; rtc1 = "/rtc@7000e000"; + serial0 = &uarta; }; memory { diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index ca8484cccddc..04c58e9ca490 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -10,6 +10,7 @@ aliases { rtc0 = "/i2c@7000d000/tps6586x@34"; rtc1 = "/rtc@7000e000"; + serial0 = &uartd; }; memory { diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts index 1843725785c9..340d81108df1 100644 --- a/arch/arm/boot/dts/tegra20-whistler.dts +++ b/arch/arm/boot/dts/tegra20-whistler.dts @@ -10,6 +10,7 @@ aliases { rtc0 = "/i2c@7000d000/max8907@3c"; rtc1 = "/rtc@7000e000"; + serial0 = &uarta; }; memory { diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 1908f6937e53..8acf5d85c99d 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -9,14 +9,6 @@ compatible = "nvidia,tegra20"; interrupt-parent = <&intc>; - aliases { - serial0 = &uarta; - serial1 = &uartb; - serial2 = &uartc; - serial3 = &uartd; - serial4 = &uarte; - }; - host1x@50000000 { compatible = "nvidia,tegra20-host1x", "simple-bus"; reg = <0x50000000 0x00024000>; @@ -190,6 +182,11 @@ #reset-cells = <1>; }; + flow-controller@60007000 { + compatible = "nvidia,tegra20-flowctrl"; + reg = <0x60007000 0x1000>; + }; + apbdma: dma@6000a000 { compatible = "nvidia,tegra20-apbdma"; reg = <0x6000a000 0x1200>; diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts index 45d40f024585..6236bdecb48b 100644 --- a/arch/arm/boot/dts/tegra30-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts @@ -11,6 +11,10 @@ rtc0 = "/i2c@7000c000/rtc@68"; rtc1 = "/i2c@7000d000/tps65911@2d"; rtc2 = "/rtc@7000e000"; + serial0 = &uarta; + serial1 = &uartb; + serial2 = &uartc; + serial3 = &uartd; }; pcie-controller@00003000 { diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index cee8f2246fdb..6b157eeabcc5 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -9,6 +9,7 @@ aliases { rtc0 = "/i2c@7000d000/tps65911@2d"; rtc1 = "/rtc@7000e000"; + serial0 = &uarta; }; memory { diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 206379546244..cbf5a1ae0ca7 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -30,6 +30,8 @@ aliases { rtc0 = "/i2c@7000d000/tps65911@2d"; rtc1 = "/rtc@7000e000"; + serial0 = &uarta; + serial1 = &uartc; }; memory { @@ -187,7 +189,7 @@ /* ALS and Proximity sensor */ isl29028@44 { - compatible = "isil,isl29028"; + compatible = "isl,isl29028"; reg = <0x44>; interrupt-parent = <&gpio>; interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts index 7793abd5bef1..4d3ddc585641 100644 --- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts @@ -10,6 +10,9 @@ rtc0 = "/i2c@7000c000/rtc@68"; rtc1 = "/i2c@7000d000/tps65911@2d"; rtc2 = "/rtc@7000e000"; + serial0 = &uarta; + serial1 = &uartb; + serial2 = &uartd; }; host1x@50000000 { diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 6b35c29278d7..99475f6e76a3 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -1,5 +1,6 @@ #include <dt-bindings/clock/tegra30-car.h> #include <dt-bindings/gpio/tegra-gpio.h> +#include <dt-bindings/memory/tegra30-mc.h> #include <dt-bindings/pinctrl/pinctrl-tegra.h> #include <dt-bindings/interrupt-controller/arm-gic.h> @@ -9,14 +10,6 @@ compatible = "nvidia,tegra30"; interrupt-parent = <&intc>; - aliases { - serial0 = &uarta; - serial1 = &uartb; - serial2 = &uartc; - serial3 = &uartd; - serial4 = &uarte; - }; - pcie-controller@00003000 { compatible = "nvidia,tegra30-pcie"; device_type = "pci"; @@ -174,6 +167,8 @@ resets = <&tegra_car 27>; reset-names = "dc"; + iommus = <&mc TEGRA_SWGROUP_DC>; + nvidia,head = <0>; rgb { @@ -191,6 +186,8 @@ resets = <&tegra_car 26>; reset-names = "dc"; + iommus = <&mc TEGRA_SWGROUP_DCB>; + nvidia,head = <1>; rgb { @@ -272,6 +269,11 @@ #reset-cells = <1>; }; + flow-controller@60007000 { + compatible = "nvidia,tegra30-flowctrl"; + reg = <0x60007000 0x1000>; + }; + apbdma: dma@6000a000 { compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; reg = <0x6000a000 0x1400>; @@ -618,23 +620,15 @@ clock-names = "pclk", "clk32k_in"; }; - memory-controller@7000f000 { + mc: memory-controller@7000f000 { compatible = "nvidia,tegra30-mc"; - reg = <0x7000f000 0x010 - 0x7000f03c 0x1b4 - 0x7000f200 0x028 - 0x7000f284 0x17c>; + reg = <0x7000f000 0x400>; + clocks = <&tegra_car TEGRA30_CLK_MC>; + clock-names = "mc"; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; - }; - iommu@7000f010 { - compatible = "nvidia,tegra30-smmu"; - reg = <0x7000f010 0x02c - 0x7000f1f0 0x010 - 0x7000f228 0x05c>; - nvidia,#asids = <4>; /* # of ASIDs */ - dma-window = <0 0x40000000>; /* IOVA start & length */ - nvidia,ahb = <&ahb>; + #iommu-cells = <1>; }; fuse@7000f800 { diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi index 756c986995a3..2efb2058ba49 100644 --- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi @@ -41,7 +41,7 @@ bank-width = <4>; }; - vram@2,00000000 { + v2m_video_ram: vram@2,00000000 { compatible = "arm,vexpress-vram"; reg = <2 0x00000000 0x00800000>; }; @@ -246,9 +246,41 @@ clcd@1f0000 { compatible = "arm,pl111", "arm,primecell"; reg = <0x1f0000 0x1000>; + interrupt-names = "combined"; interrupts = <14>; clocks = <&v2m_oscclk1>, <&smbclk>; clock-names = "clcdclk", "apb_pclk"; + memory-region = <&v2m_video_ram>; + max-memory-bandwidth = <50350000>; /* 16bpp @ 25.175MHz */ + + port { + v2m_clcd_pads: endpoint { + remote-endpoint = <&v2m_clcd_panel>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + }; + + panel { + compatible = "panel-dpi"; + + port { + v2m_clcd_panel: endpoint { + remote-endpoint = <&v2m_clcd_pads>; + }; + }; + + panel-timing { + clock-frequency = <25175000>; + hactive = <640>; + hback-porch = <40>; + hfront-porch = <24>; + hsync-len = <96>; + vactive = <480>; + vback-porch = <32>; + vfront-porch = <11>; + vsync-len = <2>; + }; + }; }; }; @@ -350,7 +382,7 @@ /* CLCD clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 1>; - freq-range = <23750000 63500000>; + freq-range = <23750000 65000000>; #clock-cells = <0>; clock-output-names = "v2m:oscclk1"; }; diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi index ba856d604fb7..cb3090f919a7 100644 --- a/arch/arm/boot/dts/vexpress-v2m.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m.dtsi @@ -40,7 +40,7 @@ bank-width = <4>; }; - vram@3,00000000 { + v2m_video_ram: vram@3,00000000 { compatible = "arm,vexpress-vram"; reg = <3 0x00000000 0x00800000>; }; @@ -245,9 +245,41 @@ clcd@1f000 { compatible = "arm,pl111", "arm,primecell"; reg = <0x1f000 0x1000>; + interrupt-names = "combined"; interrupts = <14>; clocks = <&v2m_oscclk1>, <&smbclk>; clock-names = "clcdclk", "apb_pclk"; + memory-region = <&v2m_video_ram>; + max-memory-bandwidth = <50350000>; /* 16bpp @ 25.175MHz */ + + port { + v2m_clcd_pads: endpoint { + remote-endpoint = <&v2m_clcd_panel>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + }; + + panel { + compatible = "panel-dpi"; + + port { + v2m_clcd_panel: endpoint { + remote-endpoint = <&v2m_clcd_pads>; + }; + }; + + panel-timing { + clock-frequency = <25175000>; + hactive = <640>; + hback-porch = <40>; + hfront-porch = <24>; + hsync-len = <96>; + vactive = <480>; + vback-porch = <32>; + vfront-porch = <11>; + vsync-len = <2>; + }; + }; }; }; @@ -349,7 +381,7 @@ /* CLCD clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 1>; - freq-range = <23750000 63500000>; + freq-range = <23750000 65000000>; #clock-cells = <0>; clock-output-names = "v2m:oscclk1"; }; diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts index a25c262326dc..33920df03640 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts @@ -38,6 +38,7 @@ compatible = "arm,cortex-a15"; reg = <0>; cci-control-port = <&cci_control1>; + cpu-idle-states = <&CLUSTER_SLEEP_BIG>; }; cpu1: cpu@1 { @@ -45,6 +46,7 @@ compatible = "arm,cortex-a15"; reg = <1>; cci-control-port = <&cci_control1>; + cpu-idle-states = <&CLUSTER_SLEEP_BIG>; }; cpu2: cpu@2 { @@ -52,6 +54,7 @@ compatible = "arm,cortex-a7"; reg = <0x100>; cci-control-port = <&cci_control2>; + cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; }; cpu3: cpu@3 { @@ -59,6 +62,7 @@ compatible = "arm,cortex-a7"; reg = <0x101>; cci-control-port = <&cci_control2>; + cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; }; cpu4: cpu@4 { @@ -66,6 +70,25 @@ compatible = "arm,cortex-a7"; reg = <0x102>; cci-control-port = <&cci_control2>; + cpu-idle-states = <&CLUSTER_SLEEP_LITTLE>; + }; + + idle-states { + CLUSTER_SLEEP_BIG: cluster-sleep-big { + compatible = "arm,idle-state"; + local-timer-stop; + entry-latency-us = <1000>; + exit-latency-us = <700>; + min-residency-us = <2000>; + }; + + CLUSTER_SLEEP_LITTLE: cluster-sleep-little { + compatible = "arm,idle-state"; + local-timer-stop; + entry-latency-us = <1000>; + exit-latency-us = <500>; + min-residency-us = <2500>; + }; }; }; @@ -335,6 +358,205 @@ }; }; + etb@0,20010000 { + compatible = "arm,coresight-etb10", "arm,primecell"; + reg = <0 0x20010000 0 0x1000>; + + coresight-default-sink; + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + port { + etb_in_port: endpoint@0 { + slave-mode; + remote-endpoint = <&replicator_out_port0>; + }; + }; + }; + + tpiu@0,20030000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0 0x20030000 0 0x1000>; + + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + port { + tpiu_in_port: endpoint@0 { + slave-mode; + remote-endpoint = <&replicator_out_port1>; + }; + }; + }; + + replicator { + /* non-configurable replicators don't show up on the + * AMBA bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-replicator"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* replicator output ports */ + port@0 { + reg = <0>; + replicator_out_port0: endpoint { + remote-endpoint = <&etb_in_port>; + }; + }; + + port@1 { + reg = <1>; + replicator_out_port1: endpoint { + remote-endpoint = <&tpiu_in_port>; + }; + }; + + /* replicator input port */ + port@2 { + reg = <0>; + replicator_in_port0: endpoint { + slave-mode; + remote-endpoint = <&funnel_out_port0>; + }; + }; + }; + }; + + funnel@0,20040000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0x20040000 0 0x1000>; + + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* funnel output port */ + port@0 { + reg = <0>; + funnel_out_port0: endpoint { + remote-endpoint = + <&replicator_in_port0>; + }; + }; + + /* funnel input ports */ + port@1 { + reg = <0>; + funnel_in_port0: endpoint { + slave-mode; + remote-endpoint = <&ptm0_out_port>; + }; + }; + + port@2 { + reg = <1>; + funnel_in_port1: endpoint { + slave-mode; + remote-endpoint = <&ptm1_out_port>; + }; + }; + + port@3 { + reg = <2>; + funnel_in_port2: endpoint { + slave-mode; + remote-endpoint = <&etm0_out_port>; + }; + }; + + /* Input port #3 is for ITM, not supported here */ + + port@4 { + reg = <4>; + funnel_in_port4: endpoint { + slave-mode; + remote-endpoint = <&etm1_out_port>; + }; + }; + + port@5 { + reg = <5>; + funnel_in_port5: endpoint { + slave-mode; + remote-endpoint = <&etm2_out_port>; + }; + }; + }; + }; + + ptm@0,2201c000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0x2201c000 0 0x1000>; + + cpu = <&cpu0>; + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + port { + ptm0_out_port: endpoint { + remote-endpoint = <&funnel_in_port0>; + }; + }; + }; + + ptm@0,2201d000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0x2201d000 0 0x1000>; + + cpu = <&cpu1>; + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + port { + ptm1_out_port: endpoint { + remote-endpoint = <&funnel_in_port1>; + }; + }; + }; + + etm@0,2203c000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0x2203c000 0 0x1000>; + + cpu = <&cpu2>; + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + port { + etm0_out_port: endpoint { + remote-endpoint = <&funnel_in_port2>; + }; + }; + }; + + etm@0,2203d000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0x2203d000 0 0x1000>; + + cpu = <&cpu3>; + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + port { + etm1_out_port: endpoint { + remote-endpoint = <&funnel_in_port4>; + }; + }; + }; + + etm@0,2203e000 { + compatible = "arm,coresight-etm3x", "arm,primecell"; + reg = <0 0x2203e000 0 0x1000>; + + cpu = <&cpu4>; + clocks = <&oscclk6a>; + clock-names = "apb_pclk"; + port { + etm2_out_port: endpoint { + remote-endpoint = <&funnel_in_port5>; + }; + }; + }; + smb { compatible = "simple-bus"; diff --git a/arch/arm/boot/dts/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/vexpress-v2p-ca9.dts index 62d9b225dcce..23662b5a5e9d 100644 --- a/arch/arm/boot/dts/vexpress-v2p-ca9.dts +++ b/arch/arm/boot/dts/vexpress-v2p-ca9.dts @@ -70,9 +70,40 @@ clcd@10020000 { compatible = "arm,pl111", "arm,primecell"; reg = <0x10020000 0x1000>; + interrupt-names = "combined"; interrupts = <0 44 4>; clocks = <&oscclk1>, <&oscclk2>; clock-names = "clcdclk", "apb_pclk"; + max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */ + + port { + clcd_pads: endpoint { + remote-endpoint = <&clcd_panel>; + arm,pl11x,tft-r0g0b0-pads = <0 8 16>; + }; + }; + + panel { + compatible = "panel-dpi"; + + port { + clcd_panel: endpoint { + remote-endpoint = <&clcd_pads>; + }; + }; + + panel-timing { + clock-frequency = <63500127>; + hactive = <1024>; + hback-porch = <152>; + hfront-porch = <48>; + hsync-len = <104>; + vactive = <768>; + vback-porch = <23>; + vfront-porch = <3>; + vsync-len = <4>; + }; + }; }; memory-controller@100e0000 { diff --git a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi new file mode 100644 index 000000000000..56a452bc326c --- /dev/null +++ b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi @@ -0,0 +1,96 @@ +/* + * Copyright 2014 Toradex AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/ { + chosen { + bootargs = "console=ttyLP0,115200"; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + sys_5v0_reg: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + /* USBH_PEN */ + usbh_vbus_reg: regulator@1 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_reg>; + reg = <1>; + regulator-name = "usbh_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; + vin-supply = <&sys_5v0_reg>; + }; + }; +}; + +&bl { + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + status = "okay"; +}; + +&fec1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; + + /* M41T0M6 real time clock on carrier board */ + rtc: m41t0m6@68 { + compatible = "st,m41t00"; + reg = <0x68>; + }; +}; + +&pwm0 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&usbh1 { + vbus-supply = <&usbh_vbus_reg>; +}; diff --git a/arch/arm/boot/dts/vf610-colibri.dts b/arch/arm/boot/dts/vf-colibri.dtsi index aecc7dbc65e8..82f5728be5c9 100644 --- a/arch/arm/boot/dts/vf610-colibri.dts +++ b/arch/arm/boot/dts/vf-colibri.dtsi @@ -7,72 +7,108 @@ * (at your option) any later version. */ -/dts-v1/; -#include "vf610.dtsi" - / { - model = "Toradex Colibri VF61 COM"; - compatible = "toradex,vf610-colibri", "fsl,vf610"; - - chosen { - bootargs = "console=ttyLP0,115200"; + bl: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm0 0 5000000 0>; + status = "disabled"; }; +}; - memory { - reg = <0x80000000 0x10000000>; - }; +&adc0 { + status = "okay"; +}; - clocks { - enet_ext { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - }; - }; +&adc1 { + status = "okay"; +}; +&edma0 { + status = "okay"; }; &esdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_esdhc1>; bus-width = <4>; - status = "okay"; + cd-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; }; &fec1 { phy-mode = "rmii"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; - status = "okay"; }; -&L2 { - arm,data-latency = <2 1 2>; - arm,tag-latency = <3 2 3>; +&i2c0 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; +}; + +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0>; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; - status = "okay"; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; }; &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2>; +}; + +&usbdev0 { + disable-over-current; + status = "okay"; +}; + +&usbh1 { + disable-over-current; + status = "okay"; +}; + +&usbmisc0 { + status = "okay"; +}; + +&usbmisc1 { + status = "okay"; +}; + +&usbphy0 { + status = "okay"; +}; + +&usbphy1 { status = "okay"; }; &iomuxc { vf610-colibri { + pinctrl_gpio_ext: gpio_ext { + fsl,pins = < + VF610_PAD_PTD10__GPIO_89 0x22ed /* EXT_IO_0 */ + VF610_PAD_PTD9__GPIO_88 0x22ed /* EXT_IO_1 */ + VF610_PAD_PTD26__GPIO_68 0x22ed /* EXT_IO_2 */ + >; + }; + pinctrl_esdhc1: esdhc1grp { - fsl,fsl,pins = < + fsl,pins = < VF610_PAD_PTA24__ESDHC1_CLK 0x31ef VF610_PAD_PTA25__ESDHC1_CMD 0x31ef VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef @@ -97,6 +133,27 @@ >; }; + pinctrl_i2c0: i2c0grp { + fsl,pins = < + VF610_PAD_PTB14__I2C0_SCL 0x37ff + VF610_PAD_PTB15__I2C0_SDA 0x37ff + >; + }; + + pinctrl_pwm0: pwm0grp { + fsl,pins = < + VF610_PAD_PTB0__FTM0_CH0 0x1182 + VF610_PAD_PTB1__FTM0_CH1 0x1182 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + VF610_PAD_PTB8__FTM1_CH0 0x1182 + VF610_PAD_PTB9__FTM1_CH1 0x1182 + >; + }; + pinctrl_uart0: uart0grp { fsl,pins = < VF610_PAD_PTB10__UART0_TX 0x21a2 @@ -119,5 +176,11 @@ VF610_PAD_PTD3__UART2_CTS 0x21a1 >; }; + + pinctrl_usbh1_reg: gpio_usb_vbus { + fsl,pins = < + VF610_PAD_PTD4__GPIO_83 0x22ed + >; + }; }; }; diff --git a/arch/arm/boot/dts/vf500-colibri-eval-v3.dts b/arch/arm/boot/dts/vf500-colibri-eval-v3.dts new file mode 100644 index 000000000000..7fc782c4fc52 --- /dev/null +++ b/arch/arm/boot/dts/vf500-colibri-eval-v3.dts @@ -0,0 +1,17 @@ +/* + * Copyright 2014 Toradex AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/dts-v1/; +#include "vf500-colibri.dtsi" +#include "vf-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri VF50 on Colibri Evaluation Board"; + compatible = "toradex,vf500-colibri_vf50-on-eval", "toradex,vf500-colibri_vf50", "fsl,vf500"; +}; diff --git a/arch/arm/boot/dts/vf500-colibri.dtsi b/arch/arm/boot/dts/vf500-colibri.dtsi new file mode 100644 index 000000000000..cee34a32f25b --- /dev/null +++ b/arch/arm/boot/dts/vf500-colibri.dtsi @@ -0,0 +1,20 @@ +/* + * Copyright 2014 Toradex AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include "vf500.dtsi" +#include "vf-colibri.dtsi" + +/ { + model = "Toradex Colibri VF50 COM"; + compatible = "toradex,vf610-colibri_vf50", "fsl,vf500"; + + memory { + reg = <0x80000000 0x8000000>; + }; +}; diff --git a/arch/arm/boot/dts/vf500.dtsi b/arch/arm/boot/dts/vf500.dtsi new file mode 100644 index 000000000000..de6700542714 --- /dev/null +++ b/arch/arm/boot/dts/vf500.dtsi @@ -0,0 +1,171 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include "skeleton.dtsi" +#include "vfxxx.dtsi" +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + a5_cpu: cpu@0 { + compatible = "arm,cortex-a5"; + device_type = "cpu"; + reg = <0x0>; + }; + }; + + soc { + interrupt-parent = <&intc>; + + aips-bus@40000000 { + + intc: interrupt-controller@40002000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x40003000 0x1000>, + <0x40002100 0x100>; + }; + + global_timer: timer@40002200 { + compatible = "arm,cortex-a9-global-timer"; + reg = <0x40002200 0x20>; + interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks VF610_CLK_PLATFORM_BUS>; + }; + }; + }; +}; + +&adc0 { + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; +}; + +&adc1 { + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; +}; + +&can0 { + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; +}; + +&can1 { + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; +}; + +&dspi0 { + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; +}; + +&edma0 { + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma-tx", "edma-err"; +}; + +&edma1 { + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma-tx", "edma-err"; +}; + +&esdhc1 { + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; +}; + +&fec0 { + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; +}; + +&fec1 { + interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; +}; + +&ftm { + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; +}; + +&gpio1 { + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; +}; + +&gpio2 { + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; +}; + +&gpio3 { + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; +}; + +&gpio4 { + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; +}; + +&gpio5 { + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; +}; + +&i2c0 { + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; +}; + +&pit { + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; +}; + +&qspi0 { + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; +}; + +&sai2 { + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; +}; + +&uart0 { + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; +}; + +&uart1 { + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; +}; + +&uart2 { + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; +}; + +&uart3 { + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; +}; + +&uart4 { + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; +}; + +&uart5 { + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; +}; + +&usbdev0 { + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; +}; + +&usbh1 { + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; +}; + +&usbphy0 { + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; +}; + +&usbphy1 { + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; +}; diff --git a/arch/arm/boot/dts/vf610-colibri-eval-v3.dts b/arch/arm/boot/dts/vf610-colibri-eval-v3.dts new file mode 100644 index 000000000000..10ebe99e2751 --- /dev/null +++ b/arch/arm/boot/dts/vf610-colibri-eval-v3.dts @@ -0,0 +1,17 @@ +/* + * Copyright 2014 Toradex AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/dts-v1/; +#include "vf610-colibri.dtsi" +#include "vf-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri VF61 on Colibri Evaluation Board"; + compatible = "toradex,vf610-colibri_vf61-on-eval", "toradex,vf610-colibri_vf61", "fsl,vf610"; +};
\ No newline at end of file diff --git a/arch/arm/boot/dts/vf610-colibri.dtsi b/arch/arm/boot/dts/vf610-colibri.dtsi new file mode 100644 index 000000000000..19fe045b8334 --- /dev/null +++ b/arch/arm/boot/dts/vf610-colibri.dtsi @@ -0,0 +1,25 @@ +/* + * Copyright 2014 Toradex AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include "vf610.dtsi" +#include "vf-colibri.dtsi" + +/ { + model = "Toradex Colibri VF61 COM"; + compatible = "toradex,vf610-colibri_vf61", "fsl,vf610"; + + memory { + reg = <0x80000000 0x10000000>; + }; +}; + +&L2 { + arm,data-latency = <2 1 2>; + arm,tag-latency = <3 2 3>; +}; diff --git a/arch/arm/boot/dts/vf610-cosmic.dts b/arch/arm/boot/dts/vf610-cosmic.dts index 3fd1b74e1216..fd8758b639f5 100644 --- a/arch/arm/boot/dts/vf610-cosmic.dts +++ b/arch/arm/boot/dts/vf610-cosmic.dts @@ -23,14 +23,23 @@ reg = <0x80000000 0x10000000>; }; - clocks { - enet_ext { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - }; + enet_ext: enet_ext { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; }; +}; +&clks { + clocks = <&sxosc>, <&fxosc>, <&enet_ext>; + clock-names = "sxosc", "fxosc", "enet_ext"; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + status = "okay"; }; &fec1 { @@ -42,6 +51,18 @@ &iomuxc { vf610-cosmic { + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + VF610_PAD_PTA24__ESDHC1_CLK 0x31ef + VF610_PAD_PTA25__ESDHC1_CMD 0x31ef + VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef + VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef + VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef + VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef + VF610_PAD_PTB28__GPIO_98 0x219d + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts index b8a5e8c68f06..a0f762159cb2 100644 --- a/arch/arm/boot/dts/vf610-twr.dts +++ b/arch/arm/boot/dts/vf610-twr.dts @@ -22,18 +22,16 @@ reg = <0x80000000 0x8000000>; }; - clocks { - audio_ext { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24576000>; - }; + audio_ext: mclk_osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; - enet_ext { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <50000000>; - }; + enet_ext: eth_osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; }; regulators { @@ -76,7 +74,6 @@ simple-audio-card,cpu { sound-dai = <&sai2>; - master-clkdir-out; frame-master; bitclock-master; }; @@ -96,6 +93,11 @@ status = "okay"; }; +&clks { + clocks = <&sxosc>, <&fxosc>, <&enet_ext>, <&audio_ext>; + clock-names = "sxosc", "fxosc", "enet_ext", "audio_ext"; +}; + &dspi0 { bus-num = <0>; pinctrl-names = "default"; @@ -113,10 +115,15 @@ }; }; +&edma0 { + status = "okay"; +}; + &esdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_esdhc1>; bus-width = <4>; + cd-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; status = "okay"; }; @@ -221,8 +228,6 @@ VF610_PAD_PTB1__FTM0_CH1 0x1582 VF610_PAD_PTB2__FTM0_CH2 0x1582 VF610_PAD_PTB3__FTM0_CH3 0x1582 - VF610_PAD_PTB6__FTM0_CH6 0x1582 - VF610_PAD_PTB7__FTM0_CH7 0x1582 >; }; @@ -244,6 +249,13 @@ VF610_PAD_PTB5__UART1_RX 0x21a1 >; }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + VF610_PAD_PTB6__UART2_TX 0x21a2 + VF610_PAD_PTB7__UART2_RX 0x21a1 + >; + }; }; }; @@ -265,3 +277,35 @@ pinctrl-0 = <&pinctrl_uart1>; status = "okay"; }; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbdev0 { + disable-over-current; + status = "okay"; +}; + +&usbh1 { + disable-over-current; + status = "okay"; +}; + +&usbmisc0 { + status = "okay"; +}; + +&usbmisc1 { + status = "okay"; +}; + +&usbphy0 { + status = "okay"; +}; + +&usbphy1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi index 583dd363c9dc..5f8eb1bd782b 100644 --- a/arch/arm/boot/dts/vf610.dtsi +++ b/arch/arm/boot/dts/vf610.dtsi @@ -7,427 +7,19 @@ * (at your option) any later version. */ -#include "skeleton.dtsi" -#include "vf610-pinfunc.h" -#include <dt-bindings/clock/vf610-clock.h> -#include <dt-bindings/interrupt-controller/irq.h> +#include "vf500.dtsi" -/ { - aliases { - can0 = &can0; - can1 = &can1; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - serial3 = &uart3; - serial4 = &uart4; - serial5 = &uart5; - gpio0 = &gpio1; - gpio1 = &gpio2; - gpio2 = &gpio3; - gpio3 = &gpio4; - gpio4 = &gpio5; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a5"; - device_type = "cpu"; - reg = <0x0>; - next-level-cache = <&L2>; - }; - }; - - clocks { - #address-cells = <1>; - #size-cells = <0>; - - sxosc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - - fxosc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <24000000>; - }; - }; - - soc { - #address-cells = <1>; - #size-cells = <1>; - compatible = "simple-bus"; - interrupt-parent = <&intc>; - ranges; - - aips0: aips-bus@40000000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - interrupt-parent = <&intc>; - reg = <0x40000000 0x70000>; - ranges; - - intc: interrupt-controller@40002000 { - compatible = "arm,cortex-a9-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x40003000 0x1000>, - <0x40002100 0x100>; - }; - - L2: l2-cache@40006000 { - compatible = "arm,pl310-cache"; - reg = <0x40006000 0x1000>; - cache-unified; - cache-level = <2>; - arm,data-latency = <1 1 1>; - arm,tag-latency = <2 2 2>; - }; - - edma0: dma-controller@40018000 { - #dma-cells = <2>; - compatible = "fsl,vf610-edma"; - reg = <0x40018000 0x2000>, - <0x40024000 0x1000>, - <0x40025000 0x1000>; - interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, - <0 9 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "edma-tx", "edma-err"; - dma-channels = <32>; - clock-names = "dmamux0", "dmamux1"; - clocks = <&clks VF610_CLK_DMAMUX0>, - <&clks VF610_CLK_DMAMUX1>; - }; - - can0: flexcan@40020000 { - compatible = "fsl,vf610-flexcan"; - reg = <0x40020000 0x4000>; - interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_FLEXCAN0>, - <&clks VF610_CLK_FLEXCAN0>; - clock-names = "ipg", "per"; - status = "disabled"; - }; - - uart0: serial@40027000 { - compatible = "fsl,vf610-lpuart"; - reg = <0x40027000 0x1000>; - interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_UART0>; - clock-names = "ipg"; - dmas = <&edma0 0 2>, - <&edma0 0 3>; - dma-names = "rx","tx"; - status = "disabled"; - }; - - uart1: serial@40028000 { - compatible = "fsl,vf610-lpuart"; - reg = <0x40028000 0x1000>; - interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_UART1>; - clock-names = "ipg"; - dmas = <&edma0 0 4>, - <&edma0 0 5>; - dma-names = "rx","tx"; - status = "disabled"; - }; - - uart2: serial@40029000 { - compatible = "fsl,vf610-lpuart"; - reg = <0x40029000 0x1000>; - interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_UART2>; - clock-names = "ipg"; - dmas = <&edma0 0 6>, - <&edma0 0 7>; - dma-names = "rx","tx"; - status = "disabled"; - }; - - uart3: serial@4002a000 { - compatible = "fsl,vf610-lpuart"; - reg = <0x4002a000 0x1000>; - interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_UART3>; - clock-names = "ipg"; - dmas = <&edma0 0 8>, - <&edma0 0 9>; - dma-names = "rx","tx"; - status = "disabled"; - }; - - dspi0: dspi0@4002c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-dspi"; - reg = <0x4002c000 0x1000>; - interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_DSPI0>; - clock-names = "dspi"; - spi-num-chipselects = <5>; - status = "disabled"; - }; - - sai2: sai@40031000 { - compatible = "fsl,vf610-sai"; - reg = <0x40031000 0x1000>; - interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_SAI2>; - clock-names = "sai"; - dma-names = "tx", "rx"; - dmas = <&edma0 0 21>, - <&edma0 0 20>; - status = "disabled"; - }; - - pit: pit@40037000 { - compatible = "fsl,vf610-pit"; - reg = <0x40037000 0x1000>; - interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_PIT>; - clock-names = "pit"; - }; - - pwm0: pwm@40038000 { - compatible = "fsl,vf610-ftm-pwm"; - #pwm-cells = <3>; - reg = <0x40038000 0x1000>; - clock-names = "ftm_sys", "ftm_ext", - "ftm_fix", "ftm_cnt_clk_en"; - clocks = <&clks VF610_CLK_FTM0>, - <&clks VF610_CLK_FTM0_EXT_SEL>, - <&clks VF610_CLK_FTM0_FIX_SEL>, - <&clks VF610_CLK_FTM0_EXT_FIX_EN>; - status = "disabled"; - }; - - adc0: adc@4003b000 { - compatible = "fsl,vf610-adc"; - reg = <0x4003b000 0x1000>; - interrupts = <0 53 0x04>; - clocks = <&clks VF610_CLK_ADC0>; - clock-names = "adc"; - status = "disabled"; - }; - - wdog@4003e000 { - compatible = "fsl,vf610-wdt", "fsl,imx21-wdt"; - reg = <0x4003e000 0x1000>; - clocks = <&clks VF610_CLK_WDT>; - clock-names = "wdog"; - }; - - qspi0: quadspi@40044000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-qspi"; - reg = <0x40044000 0x1000>; - interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_QSPI0_EN>, - <&clks VF610_CLK_QSPI0>; - clock-names = "qspi_en", "qspi"; - status = "disabled"; - }; - - iomuxc: iomuxc@40048000 { - compatible = "fsl,vf610-iomuxc"; - reg = <0x40048000 0x1000>; - #gpio-range-cells = <3>; - }; - - gpio1: gpio@40049000 { - compatible = "fsl,vf610-gpio"; - reg = <0x40049000 0x1000 0x400ff000 0x40>; - interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 0 32>; - }; - - gpio2: gpio@4004a000 { - compatible = "fsl,vf610-gpio"; - reg = <0x4004a000 0x1000 0x400ff040 0x40>; - interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 32 32>; - }; - - gpio3: gpio@4004b000 { - compatible = "fsl,vf610-gpio"; - reg = <0x4004b000 0x1000 0x400ff080 0x40>; - interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 64 32>; - }; - - gpio4: gpio@4004c000 { - compatible = "fsl,vf610-gpio"; - reg = <0x4004c000 0x1000 0x400ff0c0 0x40>; - interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 96 32>; - }; - - gpio5: gpio@4004d000 { - compatible = "fsl,vf610-gpio"; - reg = <0x4004d000 0x1000 0x400ff100 0x40>; - interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-ranges = <&iomuxc 0 128 7>; - }; - - anatop@40050000 { - compatible = "fsl,vf610-anatop"; - reg = <0x40050000 0x1000>; - }; - - i2c0: i2c@40066000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,vf610-i2c"; - reg = <0x40066000 0x1000>; - interrupts =<0 71 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_I2C0>; - clock-names = "ipg"; - dmas = <&edma0 0 50>, - <&edma0 0 51>; - dma-names = "rx","tx"; - status = "disabled"; - }; - - clks: ccm@4006b000 { - compatible = "fsl,vf610-ccm"; - reg = <0x4006b000 0x1000>; - #clock-cells = <1>; - }; - }; - - aips1: aips-bus@40080000 { - compatible = "fsl,aips-bus", "simple-bus"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x40080000 0x80000>; - ranges; - - edma1: dma-controller@40098000 { - #dma-cells = <2>; - compatible = "fsl,vf610-edma"; - reg = <0x40098000 0x2000>, - <0x400a1000 0x1000>, - <0x400a2000 0x1000>; - interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>, - <0 11 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "edma-tx", "edma-err"; - dma-channels = <32>; - clock-names = "dmamux0", "dmamux1"; - clocks = <&clks VF610_CLK_DMAMUX2>, - <&clks VF610_CLK_DMAMUX3>; - }; - - uart4: serial@400a9000 { - compatible = "fsl,vf610-lpuart"; - reg = <0x400a9000 0x1000>; - interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_UART4>; - clock-names = "ipg"; - status = "disabled"; - }; - - uart5: serial@400aa000 { - compatible = "fsl,vf610-lpuart"; - reg = <0x400aa000 0x1000>; - interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_UART5>; - clock-names = "ipg"; - status = "disabled"; - }; - - adc1: adc@400bb000 { - compatible = "fsl,vf610-adc"; - reg = <0x400bb000 0x1000>; - interrupts = <0 54 0x04>; - clocks = <&clks VF610_CLK_ADC1>; - clock-names = "adc"; - status = "disabled"; - }; - - esdhc1: esdhc@400b2000 { - compatible = "fsl,imx53-esdhc"; - reg = <0x400b2000 0x1000>; - interrupts = <0 28 0x04>; - clocks = <&clks VF610_CLK_IPG_BUS>, - <&clks VF610_CLK_PLATFORM_BUS>, - <&clks VF610_CLK_ESDHC1>; - clock-names = "ipg", "ahb", "per"; - status = "disabled"; - }; - - ftm: ftm@400b8000 { - compatible = "fsl,ftm-timer"; - reg = <0x400b8000 0x1000 0x400b9000 0x1000>; - interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "ftm-evt", "ftm-src", - "ftm-evt-counter-en", "ftm-src-counter-en"; - clocks = <&clks VF610_CLK_FTM2>, - <&clks VF610_CLK_FTM3>, - <&clks VF610_CLK_FTM2_EXT_FIX_EN>, - <&clks VF610_CLK_FTM3_EXT_FIX_EN>; - status = "disabled"; - }; - - fec0: ethernet@400d0000 { - compatible = "fsl,mvf600-fec"; - reg = <0x400d0000 0x1000>; - interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_ENET0>, - <&clks VF610_CLK_ENET0>, - <&clks VF610_CLK_ENET>; - clock-names = "ipg", "ahb", "ptp"; - status = "disabled"; - }; - - fec1: ethernet@400d1000 { - compatible = "fsl,mvf600-fec"; - reg = <0x400d1000 0x1000>; - interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_ENET1>, - <&clks VF610_CLK_ENET1>, - <&clks VF610_CLK_ENET>; - clock-names = "ipg", "ahb", "ptp"; - status = "disabled"; - }; - - can1: flexcan@400d4000 { - compatible = "fsl,vf610-flexcan"; - reg = <0x400d4000 0x4000>; - interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks VF610_CLK_FLEXCAN1>, - <&clks VF610_CLK_FLEXCAN1>; - clock-names = "ipg", "per"; - status = "disabled"; - }; +&a5_cpu { + next-level-cache = <&L2>; +}; - }; +&aips0 { + L2: l2-cache@40006000 { + compatible = "arm,pl310-cache"; + reg = <0x40006000 0x1000>; + cache-unified; + cache-level = <2>; + arm,data-latency = <1 1 1>; + arm,tag-latency = <2 2 2>; }; }; diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi new file mode 100644 index 000000000000..505969ae8093 --- /dev/null +++ b/arch/arm/boot/dts/vfxxx.dtsi @@ -0,0 +1,437 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include "vf610-pinfunc.h" +#include <dt-bindings/clock/vf610-clock.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> + +/ { + aliases { + can0 = &can0; + can1 = &can1; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + usbphy0 = &usbphy0; + usbphy1 = &usbphy1; + }; + + fxosc: fxosc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + sxosc: sxosc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + aips0: aips-bus@40000000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + edma0: dma-controller@40018000 { + #dma-cells = <2>; + compatible = "fsl,vf610-edma"; + reg = <0x40018000 0x2000>, + <0x40024000 0x1000>, + <0x40025000 0x1000>; + dma-channels = <32>; + clock-names = "dmamux0", "dmamux1"; + clocks = <&clks VF610_CLK_DMAMUX0>, + <&clks VF610_CLK_DMAMUX1>; + status = "disabled"; + }; + + can0: flexcan@40020000 { + compatible = "fsl,vf610-flexcan"; + reg = <0x40020000 0x4000>; + clocks = <&clks VF610_CLK_FLEXCAN0>, + <&clks VF610_CLK_FLEXCAN0>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart0: serial@40027000 { + compatible = "fsl,vf610-lpuart"; + reg = <0x40027000 0x1000>; + clocks = <&clks VF610_CLK_UART0>; + clock-names = "ipg"; + dmas = <&edma0 0 2>, + <&edma0 0 3>; + dma-names = "rx","tx"; + status = "disabled"; + }; + + uart1: serial@40028000 { + compatible = "fsl,vf610-lpuart"; + reg = <0x40028000 0x1000>; + clocks = <&clks VF610_CLK_UART1>; + clock-names = "ipg"; + dmas = <&edma0 0 4>, + <&edma0 0 5>; + dma-names = "rx","tx"; + status = "disabled"; + }; + + uart2: serial@40029000 { + compatible = "fsl,vf610-lpuart"; + reg = <0x40029000 0x1000>; + clocks = <&clks VF610_CLK_UART2>; + clock-names = "ipg"; + dmas = <&edma0 0 6>, + <&edma0 0 7>; + dma-names = "rx","tx"; + status = "disabled"; + }; + + uart3: serial@4002a000 { + compatible = "fsl,vf610-lpuart"; + reg = <0x4002a000 0x1000>; + clocks = <&clks VF610_CLK_UART3>; + clock-names = "ipg"; + dmas = <&edma0 0 8>, + <&edma0 0 9>; + dma-names = "rx","tx"; + status = "disabled"; + }; + + dspi0: dspi0@4002c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-dspi"; + reg = <0x4002c000 0x1000>; + clocks = <&clks VF610_CLK_DSPI0>; + clock-names = "dspi"; + spi-num-chipselects = <5>; + status = "disabled"; + }; + + sai2: sai@40031000 { + compatible = "fsl,vf610-sai"; + reg = <0x40031000 0x1000>; + clocks = <&clks VF610_CLK_SAI2>; + clock-names = "sai"; + dma-names = "tx", "rx"; + dmas = <&edma0 0 21>, + <&edma0 0 20>; + status = "disabled"; + }; + + pit: pit@40037000 { + compatible = "fsl,vf610-pit"; + reg = <0x40037000 0x1000>; + clocks = <&clks VF610_CLK_PIT>; + clock-names = "pit"; + }; + + pwm0: pwm@40038000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x40038000 0x1000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clks VF610_CLK_FTM0>, + <&clks VF610_CLK_FTM0_EXT_SEL>, + <&clks VF610_CLK_FTM0_FIX_SEL>, + <&clks VF610_CLK_FTM0_EXT_FIX_EN>; + status = "disabled"; + }; + + pwm1: pwm@40039000 { + compatible = "fsl,vf610-ftm-pwm"; + #pwm-cells = <3>; + reg = <0x40039000 0x1000>; + clock-names = "ftm_sys", "ftm_ext", + "ftm_fix", "ftm_cnt_clk_en"; + clocks = <&clks VF610_CLK_FTM1>, + <&clks VF610_CLK_FTM1_EXT_SEL>, + <&clks VF610_CLK_FTM1_FIX_SEL>, + <&clks VF610_CLK_FTM1_EXT_FIX_EN>; + status = "disabled"; + }; + + adc0: adc@4003b000 { + compatible = "fsl,vf610-adc"; + reg = <0x4003b000 0x1000>; + clocks = <&clks VF610_CLK_ADC0>; + clock-names = "adc"; + status = "disabled"; + }; + + wdog@4003e000 { + compatible = "fsl,vf610-wdt", "fsl,imx21-wdt"; + reg = <0x4003e000 0x1000>; + clocks = <&clks VF610_CLK_WDT>; + clock-names = "wdog"; + status = "disabled"; + }; + + qspi0: quadspi@40044000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-qspi"; + reg = <0x40044000 0x1000>; + clocks = <&clks VF610_CLK_QSPI0_EN>, + <&clks VF610_CLK_QSPI0>; + clock-names = "qspi_en", "qspi"; + status = "disabled"; + }; + + iomuxc: iomuxc@40048000 { + compatible = "fsl,vf610-iomuxc"; + reg = <0x40048000 0x1000>; + #gpio-range-cells = <3>; + }; + + gpio1: gpio@40049000 { + compatible = "fsl,vf610-gpio"; + reg = <0x40049000 0x1000 0x400ff000 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 0 32>; + }; + + gpio2: gpio@4004a000 { + compatible = "fsl,vf610-gpio"; + reg = <0x4004a000 0x1000 0x400ff040 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 32 32>; + }; + + gpio3: gpio@4004b000 { + compatible = "fsl,vf610-gpio"; + reg = <0x4004b000 0x1000 0x400ff080 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 64 32>; + }; + + gpio4: gpio@4004c000 { + compatible = "fsl,vf610-gpio"; + reg = <0x4004c000 0x1000 0x400ff0c0 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 96 32>; + }; + + gpio5: gpio@4004d000 { + compatible = "fsl,vf610-gpio"; + reg = <0x4004d000 0x1000 0x400ff100 0x40>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&iomuxc 0 128 7>; + }; + + anatop: anatop@40050000 { + compatible = "fsl,vf610-anatop", "syscon"; + reg = <0x40050000 0x400>; + }; + + usbphy0: usbphy@40050800 { + compatible = "fsl,vf610-usbphy"; + reg = <0x40050800 0x400>; + clocks = <&clks VF610_CLK_USBPHY0>; + fsl,anatop = <&anatop>; + status = "disabled"; + }; + + usbphy1: usbphy@40050c00 { + compatible = "fsl,vf610-usbphy"; + reg = <0x40050c00 0x400>; + clocks = <&clks VF610_CLK_USBPHY1>; + fsl,anatop = <&anatop>; + status = "disabled"; + }; + + i2c0: i2c@40066000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,vf610-i2c"; + reg = <0x40066000 0x1000>; + clocks = <&clks VF610_CLK_I2C0>; + clock-names = "ipg"; + dmas = <&edma0 0 50>, + <&edma0 0 51>; + dma-names = "rx","tx"; + status = "disabled"; + }; + + clks: ccm@4006b000 { + compatible = "fsl,vf610-ccm"; + reg = <0x4006b000 0x1000>; + clocks = <&sxosc>, <&fxosc>; + clock-names = "sxosc", "fxosc"; + #clock-cells = <1>; + }; + + usbdev0: usb@40034000 { + compatible = "fsl,vf610-usb", "fsl,imx27-usb"; + reg = <0x40034000 0x800>; + clocks = <&clks VF610_CLK_USBC0>; + fsl,usbphy = <&usbphy0>; + fsl,usbmisc = <&usbmisc0 0>; + dr_mode = "peripheral"; + status = "disabled"; + }; + + usbmisc0: usb@40034800 { + #index-cells = <1>; + compatible = "fsl,vf610-usbmisc"; + reg = <0x40034800 0x200>; + clocks = <&clks VF610_CLK_USBC0>; + status = "disabled"; + }; + }; + + aips1: aips-bus@40080000 { + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + edma1: dma-controller@40098000 { + #dma-cells = <2>; + compatible = "fsl,vf610-edma"; + reg = <0x40098000 0x2000>, + <0x400a1000 0x1000>, + <0x400a2000 0x1000>; + dma-channels = <32>; + clock-names = "dmamux0", "dmamux1"; + clocks = <&clks VF610_CLK_DMAMUX2>, + <&clks VF610_CLK_DMAMUX3>; + status = "disabled"; + }; + + uart4: serial@400a9000 { + compatible = "fsl,vf610-lpuart"; + reg = <0x400a9000 0x1000>; + clocks = <&clks VF610_CLK_UART4>; + clock-names = "ipg"; + status = "disabled"; + }; + + uart5: serial@400aa000 { + compatible = "fsl,vf610-lpuart"; + reg = <0x400aa000 0x1000>; + clocks = <&clks VF610_CLK_UART5>; + clock-names = "ipg"; + status = "disabled"; + }; + + adc1: adc@400bb000 { + compatible = "fsl,vf610-adc"; + reg = <0x400bb000 0x1000>; + clocks = <&clks VF610_CLK_ADC1>; + clock-names = "adc"; + status = "disabled"; + }; + + esdhc1: esdhc@400b2000 { + compatible = "fsl,imx53-esdhc"; + reg = <0x400b2000 0x1000>; + clocks = <&clks VF610_CLK_IPG_BUS>, + <&clks VF610_CLK_PLATFORM_BUS>, + <&clks VF610_CLK_ESDHC1>; + clock-names = "ipg", "ahb", "per"; + status = "disabled"; + }; + + usbh1: usb@400b4000 { + compatible = "fsl,vf610-usb", "fsl,imx27-usb"; + reg = <0x400b4000 0x800>; + clocks = <&clks VF610_CLK_USBC1>; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc1 0>; + dr_mode = "host"; + status = "disabled"; + }; + + usbmisc1: usb@400b4800 { + #index-cells = <1>; + compatible = "fsl,vf610-usbmisc"; + reg = <0x400b4800 0x200>; + clocks = <&clks VF610_CLK_USBC1>; + status = "disabled"; + }; + + ftm: ftm@400b8000 { + compatible = "fsl,ftm-timer"; + reg = <0x400b8000 0x1000 0x400b9000 0x1000>; + clock-names = "ftm-evt", "ftm-src", + "ftm-evt-counter-en", "ftm-src-counter-en"; + clocks = <&clks VF610_CLK_FTM2>, + <&clks VF610_CLK_FTM3>, + <&clks VF610_CLK_FTM2_EXT_FIX_EN>, + <&clks VF610_CLK_FTM3_EXT_FIX_EN>; + status = "disabled"; + }; + + fec0: ethernet@400d0000 { + compatible = "fsl,mvf600-fec"; + reg = <0x400d0000 0x1000>; + clocks = <&clks VF610_CLK_ENET0>, + <&clks VF610_CLK_ENET0>, + <&clks VF610_CLK_ENET>; + clock-names = "ipg", "ahb", "ptp"; + status = "disabled"; + }; + + fec1: ethernet@400d1000 { + compatible = "fsl,mvf600-fec"; + reg = <0x400d1000 0x1000>; + clocks = <&clks VF610_CLK_ENET1>, + <&clks VF610_CLK_ENET1>, + <&clks VF610_CLK_ENET>; + clock-names = "ipg", "ahb", "ptp"; + status = "disabled"; + }; + + can1: flexcan@400d4000 { + compatible = "fsl,vf610-flexcan"; + reg = <0x400d4000 0x4000>; + clocks = <&clks VF610_CLK_FLEXCAN1>, + <&clks VF610_CLK_FLEXCAN1>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + }; + }; +}; diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index 6cc83d4c6c76..ee3e5d675b05 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -30,7 +30,6 @@ /* kHz uV */ 666667 1000000 333334 1000000 - 222223 1000000 >; }; @@ -65,7 +64,7 @@ interrupt-parent = <&intc>; ranges; - adc@f8007100 { + adc: adc@f8007100 { compatible = "xlnx,zynq-xadc-1.00.a"; reg = <0xf8007100 0x20>; interrupts = <0 7 4>; @@ -137,7 +136,7 @@ <0xF8F00100 0x100>; }; - L2: cache-controller { + L2: cache-controller@f8f02000 { compatible = "arm,pl310-cache"; reg = <0xF8F02000 0x1000>; arm,data-latency = <3 2 2>; @@ -146,6 +145,11 @@ cache-level = <2>; }; + mc: memory-controller@f8006000 { + compatible = "xlnx,zynq-ddrc-a05"; + reg = <0xf8006000 0x1000>; + }; + uart0: serial@e0000000 { compatible = "xlnx,xuartps", "cdns,uart-r1p8"; status = "disabled"; @@ -190,20 +194,24 @@ gem0: ethernet@e000b000 { compatible = "cdns,gem"; - reg = <0xe000b000 0x4000>; + reg = <0xe000b000 0x1000>; status = "disabled"; interrupts = <0 22 4>; clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; clock-names = "pclk", "hclk", "tx_clk"; + #address-cells = <1>; + #size-cells = <0>; }; gem1: ethernet@e000c000 { compatible = "cdns,gem"; - reg = <0xe000c000 0x4000>; + reg = <0xe000c000 0x1000>; status = "disabled"; interrupts = <0 45 4>; clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; clock-names = "pclk", "hclk", "tx_clk"; + #address-cells = <1>; + #size-cells = <0>; }; sdhci0: sdhci@e0100000 { @@ -214,7 +222,7 @@ interrupt-parent = <&intc>; interrupts = <0 24 4>; reg = <0xe0100000 0x1000>; - } ; + }; sdhci1: sdhci@e0101000 { compatible = "arasan,sdhci-8.9a"; @@ -224,7 +232,7 @@ interrupt-parent = <&intc>; interrupts = <0 47 4>; reg = <0xe0101000 0x1000>; - } ; + }; slcr: slcr@f8000000 { #address-cells = <1>; @@ -235,7 +243,6 @@ clkc: clkc@100 { #clock-cells = <1>; compatible = "xlnx,ps7-clkc"; - ps-clk-frequency = <33333333>; fclk-enable = <0>; clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", @@ -256,6 +263,8 @@ compatible = "arm,pl330", "arm,primecell"; reg = <0xf8003000 0x1000>; interrupt-parent = <&intc>; + interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", + "dma4", "dma5", "dma6", "dma7"; interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, @@ -271,7 +280,7 @@ devcfg: devcfg@f8007000 { compatible = "xlnx,zynq-devcfg-1.0"; reg = <0xf8007000 0x100>; - } ; + }; global_timer: timer@f8f00200 { compatible = "arm,cortex-a9-global-timer"; @@ -303,6 +312,17 @@ compatible = "arm,cortex-a9-twd-timer"; reg = <0xf8f00600 0x20>; clocks = <&clkc 4>; - } ; + }; + + watchdog0: watchdog@f8005000 { + clocks = <&clkc 45>; + compatible = "xlnx,zynq-wdt-r1p2"; + device_type = "watchdog"; + interrupt-parent = <&intc>; + interrupts = <0 9 1>; + reg = <0xf8005000 0x1000>; + reset = <0>; + timeout-sec = <10>; + }; }; }; diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts index 41afd9da6876..ab1dc0a56cdd 100644 --- a/arch/arm/boot/dts/zynq-parallella.dts +++ b/arch/arm/boot/dts/zynq-parallella.dts @@ -25,7 +25,7 @@ memory { device_type = "memory"; - reg = <0 0x40000000>; + reg = <0x0 0x40000000>; }; chosen { @@ -34,12 +34,15 @@ }; }; +&clkc { + fclk-enable = <0xf>; + ps-clk-frequency = <33333333>; +}; + &gem0 { status = "okay"; phy-mode = "rgmii-id"; phy-handle = <ðernet_phy>; - #address-cells = <1>; - #size-cells = <0>; ethernet_phy: ethernet-phy@0 { /* Marvell 88E1318 */ @@ -53,6 +56,29 @@ &i2c0 { status = "okay"; + + isl9305: isl9305@68 { + compatible = "isl,isl9305"; + reg = <0x68>; + + regulators { + dcd1 { + regulator-name = "VDD_DSP"; + regulator-always-on; + }; + dcd2 { + regulator-name = "1P35V"; + regulator-always-on; + }; + ldo1 { + regulator-name = "VDD_ADJ"; + }; + ldo2 { + regulator-name = "VDD_GPIO"; + regulator-always-on; + }; + }; + }; }; &sdhci1 { diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts index 835c3089c61c..280f02dd4ddc 100644 --- a/arch/arm/boot/dts/zynq-zc702.dts +++ b/arch/arm/boot/dts/zynq-zc702.dts @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 Xilinx + * Copyright (C) 2011 - 2014 Xilinx * Copyright (C) 2012 National Instruments Corp. * * This software is licensed under the terms of the GNU General Public @@ -27,15 +27,33 @@ bootargs = "console=ttyPS0,115200 earlyprintk"; }; + leds { + compatible = "gpio-leds"; + + ds23 { + label = "ds23"; + gpios = <&gpio0 10 0>; + linux,default-trigger = "heartbeat"; + }; + }; }; &can0 { status = "okay"; }; +&clkc { + ps-clk-frequency = <33333333>; +}; + &gem0 { status = "okay"; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@7 { + reg = <7>; + }; }; &i2c0 { diff --git a/arch/arm/boot/dts/zynq-zc706.dts b/arch/arm/boot/dts/zynq-zc706.dts index 4cc9913078cd..34f7812d2ee8 100644 --- a/arch/arm/boot/dts/zynq-zc706.dts +++ b/arch/arm/boot/dts/zynq-zc706.dts @@ -1,7 +1,6 @@ /* - * Copyright (C) 2011 Xilinx + * Copyright (C) 2011 - 2014 Xilinx * Copyright (C) 2012 National Instruments Corp. - * Copyright (C) 2013 Xilinx * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -21,7 +20,7 @@ memory { device_type = "memory"; - reg = <0 0x40000000>; + reg = <0x0 0x40000000>; }; chosen { @@ -30,9 +29,18 @@ }; +&clkc { + ps-clk-frequency = <33333333>; +}; + &gem0 { status = "okay"; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@7 { + reg = <7>; + }; }; &i2c0 { diff --git a/arch/arm/boot/dts/zynq-zed.dts b/arch/arm/boot/dts/zynq-zed.dts index 82d7ef1a9a9c..1c7cc990b47a 100644 --- a/arch/arm/boot/dts/zynq-zed.dts +++ b/arch/arm/boot/dts/zynq-zed.dts @@ -1,7 +1,6 @@ /* - * Copyright (C) 2011 Xilinx + * Copyright (C) 2011 - 2014 Xilinx * Copyright (C) 2012 National Instruments Corp. - * Copyright (C) 2013 Xilinx * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -17,11 +16,11 @@ / { model = "Zynq Zed Development Board"; - compatible = "xlnx,zynq-7000"; + compatible = "xlnx,zynq-zed", "xlnx,zynq-7000"; memory { device_type = "memory"; - reg = <0 0x20000000>; + reg = <0x0 0x20000000>; }; chosen { @@ -30,9 +29,18 @@ }; +&clkc { + ps-clk-frequency = <33333333>; +}; + &gem0 { status = "okay"; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@0 { + reg = <0>; + }; }; &sdhci0 { diff --git a/arch/arm/boot/dts/zynq-zybo.dts b/arch/arm/boot/dts/zynq-zybo.dts new file mode 100644 index 000000000000..a9a12ce5023b --- /dev/null +++ b/arch/arm/boot/dts/zynq-zybo.dts @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2011 - 2014 Xilinx + * Copyright (C) 2012 National Instruments Corp. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +/dts-v1/; +/include/ "zynq-7000.dtsi" + +/ { + model = "Zynq ZYBO Development Board"; + compatible = "digilent,zynq-zybo", "xlnx,zynq-7000"; + + memory { + device_type = "memory"; + reg = <0x0 0x20000000>; + }; + + chosen { + bootargs = "console=ttyPS0,115200 earlyprintk"; + }; + +}; + +&clkc { + ps-clk-frequency = <50000000>; +}; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy>; + + ethernet_phy: ethernet-phy@0 { + reg = <0>; + }; +}; + +&sdhci0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; |