summaryrefslogtreecommitdiff
path: root/arch/arm/boot
diff options
context:
space:
mode:
authorIcenowy Zheng <icenowy@aosc.io>2020-09-23 08:58:54 +0800
committerMaxime Ripard <maxime@cerno.tech>2020-09-28 12:09:22 +0200
commit90e048101fa192e6e1ea48192fa22d8c684a0bf1 (patch)
tree203dad0ace1b71c45b2481a47297a9cef4b0eb65 /arch/arm/boot
parentc0dcfbe29edcc90d90da6b84e7d45ef39e67a726 (diff)
ARM: dts: sun8i: V3/V3s/S3/S3L: add CSI1 device node
The CSI1 controller of V3/V3s/S3/S3L chips is used for parallel CSI. Add the device tree node of it. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20200923005858.148261-2-icenowy@aosc.io
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/sun8i-v3s.dtsi12
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index 4cfdf193cf88..3e079973672d 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -488,6 +488,18 @@
#size-cells = <0>;
};
+ csi1: camera@1cb4000 {
+ compatible = "allwinner,sun8i-v3s-csi";
+ reg = <0x01cb4000 0x3000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CSI>,
+ <&ccu CLK_CSI1_SCLK>,
+ <&ccu CLK_DRAM_CSI>;
+ clock-names = "bus", "mod", "ram";
+ resets = <&ccu RST_BUS_CSI>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@1c81000 {
compatible = "arm,gic-400";
reg = <0x01c81000 0x1000>,