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authorLinus Walleij <linus.walleij@stericsson.com>2009-09-15 17:30:37 +0100
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-09-15 22:11:05 +0100
commitbc581770cfdd8c17ea17d324dc05e2f9c599e7ca (patch)
treec6d2c2eb82d8a6c6851de0ecc7d8c0e63e026266 /arch/arm/include/asm/cputype.h
parent18240904960a39e582ced8ba8ececb10b8c22dd3 (diff)
ARM: 5580/2: ARM TCM (Tightly-Coupled Memory) support v3
This adds the TCM interface to Linux, when active, it will detect and report TCM memories and sizes early in boot if present, introduce generic TCM memory handling, provide a generic TCM memory pool and select TCM memory for the U300 platform. See the Documentation/arm/tcm.txt for documentation. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/include/asm/cputype.h')
-rw-r--r--arch/arm/include/asm/cputype.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index b3e656c6fb78..54a1f1d76b14 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -63,6 +63,11 @@ static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
return read_cpuid(CPUID_CACHETYPE);
}
+static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void)
+{
+ return read_cpuid(CPUID_TCM);
+}
+
/*
* Intel's XScale3 core supports some v6 features (supersections, L2)
* but advertises itself as v5 as it does not support the v6 ISA. For