diff options
author | Kevin Hilman <khilman@linaro.org> | 2013-08-14 08:14:50 -0700 |
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committer | Kevin Hilman <khilman@linaro.org> | 2013-08-14 08:14:50 -0700 |
commit | 080e3da4f4bf693ec59bd98eae3ee5bd5b1dd047 (patch) | |
tree | 2a367e97dcffe9ced54ff71b03ab893a3248fdb4 /arch/arm/include/asm/tlbflush.h | |
parent | e91f24ae027a583f2faff84456fa2630144bfed8 (diff) | |
parent | 39c41df9c1950fba0ee6a4e7a63be281e89fe437 (diff) |
Merge branch 'zynq/dt' into next/dt
* zynq/dt: (1054 commits)
arm: zynq: dt: Set correct L2 ram latencies
+ v3.11-rc5
Conflicts:
arch/arm/Makefile
Diffstat (limited to 'arch/arm/include/asm/tlbflush.h')
-rw-r--r-- | arch/arm/include/asm/tlbflush.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h index fdbb9e369745..f467e9b3f8d5 100644 --- a/arch/arm/include/asm/tlbflush.h +++ b/arch/arm/include/asm/tlbflush.h @@ -443,7 +443,18 @@ static inline void local_flush_bp_all(void) isb(); } +#include <asm/cputype.h> #ifdef CONFIG_ARM_ERRATA_798181 +static inline int erratum_a15_798181(void) +{ + unsigned int midr = read_cpuid_id(); + + /* Cortex-A15 r0p0..r3p2 affected */ + if ((midr & 0xff0ffff0) != 0x410fc0f0 || midr > 0x413fc0f2) + return 0; + return 1; +} + static inline void dummy_flush_tlb_a15_erratum(void) { /* @@ -453,6 +464,11 @@ static inline void dummy_flush_tlb_a15_erratum(void) dsb(); } #else +static inline int erratum_a15_798181(void) +{ + return 0; +} + static inline void dummy_flush_tlb_a15_erratum(void) { } |