diff options
| author | Amit Daniel Kachhap <amit.kachhap@arm.com> | 2022-11-17 06:28:22 +0100 |
|---|---|---|
| committer | Russell King (Oracle) <rmk+kernel@armlinux.org.uk> | 2022-11-28 11:57:32 +0000 |
| commit | c00a19c8b143db31d660ee965e6a6f782ef090ff (patch) | |
| tree | a86521291809833382af989671c895bd85b6c3a6 /arch/arm/include/asm/vfp.h | |
| parent | 74c344e6f153dd9ae97c99ad751723e4030d4af9 (diff) | |
ARM: 9268/1: vfp: Add hwcap FPHP and ASIMDHP for FEAT_FP16
Floating point half-precision (FPHP) and Advanced SIMD half-precision
(ASIMDHP) are VFP features (FEAT_FP16) represented by MVFR1 identification register. These capabilities can optionally exist with VFPv3 and mandatory with VFPv4. Both these new features exist for Armv8 architecture in AArch32 state.
These hwcaps may be useful for the userspace to add conditional check
before trying to use FEAT_FP16 feature specific instructions.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'arch/arm/include/asm/vfp.h')
| -rw-r--r-- | arch/arm/include/asm/vfp.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/include/asm/vfp.h b/arch/arm/include/asm/vfp.h index 19928bfb4f9c..157ea3426158 100644 --- a/arch/arm/include/asm/vfp.h +++ b/arch/arm/include/asm/vfp.h @@ -87,6 +87,12 @@ #define MVFR0_DP_BIT (8) #define MVFR0_DP_MASK (0xf << MVFR0_DP_BIT) +/* MVFR1 bits */ +#define MVFR1_ASIMDHP_BIT (20) +#define MVFR1_ASIMDHP_MASK (0xf << MVFR1_ASIMDHP_BIT) +#define MVFR1_FPHP_BIT (24) +#define MVFR1_FPHP_MASK (0xf << MVFR1_FPHP_BIT) + /* Bit patterns for decoding the packaged operation descriptors */ #define VFPOPDESC_LENGTH_BIT (9) #define VFPOPDESC_LENGTH_MASK (0x07 << VFPOPDESC_LENGTH_BIT) |