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authorRafael J. Wysocki <rafael.j.wysocki@intel.com>2020-10-06 21:43:43 +0200
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2020-10-07 17:13:15 +0200
commitefad4240da949fc3249015065b95d708b72ae670 (patch)
treef9879c25cda6bd6fddae7cfe644b0a55c619568c /arch/arm/include
parent86836bac55f971995499978df4e62115d7baf5ef (diff)
cpufreq: stats: Add memory barrier to store_reset()
There is nothing to prevent the CPU or the compiler from reordering the writes to stats->reset_time and stats->reset_pending in store_reset(), in which case the readers of stats->reset_time may see a stale value. Moreover, on 32-bit arches the write to reset_time cannot be completed in one go, so the readers of it may see a partially updated value in that case. To prevent that from happening, add a write memory barrier between the writes to stats->reset_time and stats->reset_pending in store_reset() and corresponding read memory barrier in the readers of stats->reset_time. Fixes: 40c3bd4cfa6f ("cpufreq: stats: Defer stats update to cpufreq_stats_record_transition()") Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Diffstat (limited to 'arch/arm/include')
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