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| author | Arnd Bergmann <arnd@arndb.de> | 2017-10-19 17:59:50 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2017-10-19 17:59:50 +0200 |
| commit | 84dbf97808955ea12286c9f442902360e0e1cc96 (patch) | |
| tree | da9683aea007fc795de0f0d69aaad46d97b5fbcd /arch/arm/include | |
| parent | e7b14ccd55fad40855f1a1ccea8cde82ee4a0786 (diff) | |
| parent | 3fd45a136ff61bb54deab70fb2d534a85e40481f (diff) | |
Merge tag 'renesas-soc-for-v4.15' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
Pull "Renesas ARM Based SoC Updates for v4.15" from Simon Horman:
* Prepare to enable SMP on R-Car E2 (r8a7794).
Geert Uytterhoeven says:
"The main hurdle here is that R-Car Gen2 boot loaders do not initialize
the arch_timer CNTVOFF register, which thus needs workarounds on Linux.
- The first patch adds a definition for MON_MODE, as suggested by Marc
Zyngier,
- The second patch makes sure CNTVOFF is initialized for boot and
secondary Cortex-A15 and Cortex-A7 CPU cores, like is already done for
the boot Cortex-A7 CPU core. Without this, the ARM arch timer does
not work on secondary CPU cores."
A follow-up patch to enable SMP in DT on R-Car E2 (r8a7794) is currently
deferred unto v4.16 as it depends on the above.
* Enable low-level debugging support for RZ/G1E (r8a7745).
Fabrizio Castro says, "RZ/G1E uses SCIF4 for the debug console."
* tag 'renesas-soc-for-v4.15' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: rcar-gen2: Make sure CNTVOFF is initialized on CA7/15
ARM: Add definition for monitor mode
ARM: debug-ll: Add support for r8a7745
Diffstat (limited to 'arch/arm/include')
| -rw-r--r-- | arch/arm/include/uapi/asm/ptrace.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/include/uapi/asm/ptrace.h b/arch/arm/include/uapi/asm/ptrace.h index 5af0ed1b825a..70ff6bf489f3 100644 --- a/arch/arm/include/uapi/asm/ptrace.h +++ b/arch/arm/include/uapi/asm/ptrace.h @@ -53,6 +53,7 @@ #endif #define FIQ_MODE 0x00000011 #define IRQ_MODE 0x00000012 +#define MON_MODE 0x00000016 #define ABT_MODE 0x00000017 #define HYP_MODE 0x0000001a #define UND_MODE 0x0000001b |