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authorArnd Bergmann <arnd@arndb.de>2017-10-19 18:07:09 +0200
committerArnd Bergmann <arnd@arndb.de>2017-10-19 18:07:09 +0200
commite7ffa44d37cdb8b43bcb6f49eb227bb340dda22d (patch)
treea3e50d8f2e305d64e058075c50d10bf3cbe8116a /arch/arm/include
parent84dbf97808955ea12286c9f442902360e0e1cc96 (diff)
parentc14963521502b237a6817aceda6f3379296db75c (diff)
Merge tag 'arm-soc/for-4.15/soc' of http://github.com/Broadcom/stblinux into next/soc
Pull "Broadcom soc changes for 4.15 (part 1)" from Florian Fainelli: This pull request contains Broadcom ARM-based SoC/Kconfig changes for 4.15 please pull the following: - Danilo removes the clock provider driver stubs which are no longer needed now that we have a proper CPRMAN clock provider driver - Stefan moves the SMP startup code for BCM2836 from the interrupt controller driver down to where it belongs in the architecture code, this was requested by Marc Zyngier before comitting any fixes to that code - Phil provides a fix for a future Raspberry Pi firmware which will make the secondary cores wait for an event and therefore requires the CPU onlining other cores to send such event (along with the appropriate barrier) - Florian fixes the BRCMSTB UART debug stub to work correctly when using an ARM BE8 kernel since there were some missing register read swapping needed * tag 'arm-soc/for-4.15/soc' of http://github.com/Broadcom/stblinux: ARM: brcmstb: Add appropriate ARM_BE8() macros for swapping ARM: bcm2836: Send event when onlining other cores irqchip: bcm2836: Move SMP startup code to arch/arm (v2) clk: bcm2835: remove remains from stub clk driver
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/debug/brcmstb.S3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/include/debug/brcmstb.S b/arch/arm/include/debug/brcmstb.S
index 52aaed2b936f..c826f15d2f80 100644
--- a/arch/arm/include/debug/brcmstb.S
+++ b/arch/arm/include/debug/brcmstb.S
@@ -58,6 +58,7 @@
/* Check SUN_TOP_CTRL base */
ldr \rp, =SUN_TOP_CTRL_BASE @ load SUN_TOP_CTRL PA
ldr \rv, [\rp, #0] @ get register contents
+ARM_BE8( rev \rv, \rv )
and \rv, \rv, #0xffffff00 @ strip revision bits [7:0]
/* Chip specific detection starts here */
@@ -98,11 +99,13 @@
.endm
.macro store, rd, rx:vararg
+ARM_BE8( rev \rd, \rd )
str \rd, \rx
.endm
.macro load, rd, rx:vararg
ldr \rd, \rx
+ARM_BE8( rev \rd, \rd )
.endm
.macro senduart,rd,rx