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authorDmitry Osipenko <digetx@gmail.com>2019-03-18 01:52:04 +0300
committerThierry Reding <treding@nvidia.com>2019-04-09 16:36:16 +0200
commitebca2a6ee161502828de017b28a8f1d7422073f0 (patch)
treec3f9e1206650ce44e203f71c6c3d3de529a49a69 /arch/arm/include
parent9e98c678c2d6ae3a17cb2de55d17f69dddaa231b (diff)
ARM: trusted_foundations: Support L2 cache maintenance
Implement L2 cache initialization firmware callback that should be invoked early during boot in order to set up the required outer cache driver's callbacks and add the callback required for L2X0 maintenance. Partially based on work done by Michał Mirosław [1]. [1] https://www.spinics.net/lists/arm-kernel/msg594765.html Tested-by: Robert Yang <decatf@gmail.com> Tested-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Signed-off-by: Michał Mirosław <mirq-linux@rere.qmqm.pl> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm/include')
-rw-r--r--arch/arm/include/asm/trusted_foundations.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/include/asm/trusted_foundations.h b/arch/arm/include/asm/trusted_foundations.h
index 00748350cf72..9e6a41e9215e 100644
--- a/arch/arm/include/asm/trusted_foundations.h
+++ b/arch/arm/include/asm/trusted_foundations.h
@@ -32,6 +32,9 @@
#include <linux/cpu.h>
#include <linux/smp.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/outercache.h>
+
struct trusted_foundations_platform_data {
unsigned int version_major;
unsigned int version_minor;
@@ -43,6 +46,9 @@ void register_trusted_foundations(struct trusted_foundations_platform_data *pd);
void of_register_trusted_foundations(void);
#else /* CONFIG_TRUSTED_FOUNDATIONS */
+static inline void tf_dummy_write_sec(unsigned long val, unsigned int reg)
+{
+}
static inline void register_trusted_foundations(
struct trusted_foundations_platform_data *pd)
@@ -53,6 +59,10 @@ static inline void register_trusted_foundations(
*/
pr_err("No support for Trusted Foundations, continuing in degraded mode.\n");
pr_err("Secondary processors as well as CPU PM will be disabled.\n");
+#if IS_ENABLED(CONFIG_CACHE_L2X0)
+ pr_err("L2X0 cache will be kept disabled.\n");
+ outer_cache.write_sec = tf_dummy_write_sec;
+#endif
#if IS_ENABLED(CONFIG_SMP)
setup_max_cpus = 0;
#endif