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authorMarek Szyprowski <m.szyprowski@samsung.com>2019-05-28 09:38:14 +0100
committerRussell King <rmk+kernel@armlinux.org.uk>2019-06-20 22:29:58 +0100
commit5f41f9198f296091c6a58bc2e86af1e9f019b2a3 (patch)
treef309f6b56520b0b974c46cff4de32b3d8decc1c1 /arch/arm/kernel/smp.c
parent304009a182b9fc6eff74060b415c8240380501cb (diff)
ARM: 8864/1: Add workaround for I-Cache line size mismatch between CPU cores
Some big.LITTLE systems have I-Cache line size mismatch between LITTLE and big cores. This patch adds a workaround for proper I-Cache support on such systems. Without it, some class of the userspace code (typically self-modifying) might suffer from random SIGILL failures. Similar workaround already exists for ARM64 architecture. I has been added by commit 116c81f427ff ("arm64: Work around systems with mismatched cache line sizes"). Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'arch/arm/kernel/smp.c')
-rw-r--r--arch/arm/kernel/smp.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index ebc53804d57b..12cf7c4324a9 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -375,6 +375,7 @@ static void smp_store_cpu_info(unsigned int cpuid)
cpu_info->cpuid = read_cpuid_id();
store_cpu_topology(cpuid);
+ check_cpu_icache_size(cpuid);
}
/*