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authorRussell King <rmk+kernel@arm.linux.org.uk>2014-03-19 12:06:27 +0000
committerRussell King <rmk+kernel@arm.linux.org.uk>2014-05-30 00:49:07 +0100
commit24cb65feab42ac0cc26464ac4b7a38c0ab7ce173 (patch)
tree9488e0a57b27c54878a698c70d59b041bb52ab3a /arch/arm/mach-cns3xxx
parenta048711c0b3701ee22efd74022cb1f548a52842c (diff)
ARM: l2c: cns3xxx: remove cache size override
The cache size should already be present in the L2 cache auxiliary control register: it is part of the integration process to configure the hardware IP. Most platforms get this right, yet still many cargo-cult program, and assume that they always need specifying to the L2 cache code. Remove them so we can find out which really need this. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mach-cns3xxx')
-rw-r--r--arch/arm/mach-cns3xxx/core.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c
index 5c31b2638c01..f85449a6accd 100644
--- a/arch/arm/mach-cns3xxx/core.c
+++ b/arch/arm/mach-cns3xxx/core.c
@@ -290,7 +290,7 @@ void __init cns3xxx_l2x0_init(void)
writel(val, base + L310_DATA_LATENCY_CTRL);
/* 32 KiB, 8-way, parity disable */
- l2x0_init(base, 0x00540000, 0xfe000fff);
+ l2x0_init(base, 0x00500000, 0xfe0f0fff);
}
#endif /* CONFIG_CACHE_L2X0 */