diff options
| author | Arnd Bergmann <arnd@arndb.de> | 2012-01-09 16:16:29 +0000 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2012-01-09 16:16:29 +0000 |
| commit | dcf7ec5ee62a78123057a1e286c88ca739717409 (patch) | |
| tree | fa3f19434638a942ba66d236dde4d9aaadf8b370 /arch/arm/mach-exynos/mach-origen.c | |
| parent | 15db3e823c3246e3bd31fe454f5c8927eb85caf2 (diff) | |
| parent | 142f2101a86ade2d6c9dfbedf82e1b5b31c8fce6 (diff) | |
Merge branch 'samsung/driver' into next/drivers
Conflicts:
arch/arm/mach-mxs/include/mach/common.h
Pull in previous samsung conflict merges and do a trivial
merge of an mxs double-add conflict.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-exynos/mach-origen.c')
| -rw-r--r-- | arch/arm/mach-exynos/mach-origen.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c index b805e595cc35..2b11e046d391 100644 --- a/arch/arm/mach-exynos/mach-origen.c +++ b/arch/arm/mach-exynos/mach-origen.c @@ -22,13 +22,13 @@ #include <linux/lcd.h> #include <asm/mach/arch.h> +#include <asm/hardware/gic.h> #include <asm/mach-types.h> #include <video/platform_lcd.h> #include <plat/regs-serial.h> #include <plat/regs-fb-v4.h> -#include <plat/exynos4.h> #include <plat/cpu.h> #include <plat/devs.h> #include <plat/sdhci.h> @@ -44,6 +44,8 @@ #include <mach/ohci.h> #include <mach/map.h> +#include "common.h" + /* Following are default values for UCON, ULCON and UFCON UART registers */ #define ORIGEN_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ S3C2410_UCON_RXILEVEL | \ @@ -650,7 +652,7 @@ static void s5p_tv_setup(void) static void __init origen_map_io(void) { - s5p_init_io(NULL, 0, S5P_VA_CHIPID); + exynos_init_io(NULL, 0); s3c24xx_init_clocks(24000000); s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs)); } @@ -707,7 +709,9 @@ MACHINE_START(ORIGEN, "ORIGEN") .atag_offset = 0x100, .init_irq = exynos4_init_irq, .map_io = origen_map_io, + .handle_irq = gic_handle_irq, .init_machine = origen_machine_init, .timer = &exynos4_timer, .reserve = &origen_reserve, + .restart = exynos4_restart, MACHINE_END |