diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2016-03-20 14:57:08 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2016-03-20 14:57:08 -0700 |
| commit | 33b3d2e88c9efd701b6153ca4714d4aa6e9f5af0 (patch) | |
| tree | 7a3bf34e08e6c7b32e0d5c9333b02a02e3af6330 /arch/arm/mach-exynos | |
| parent | e88fa1b8b00a947299e2415e819301fa52037cf4 (diff) | |
| parent | 307d40c56b0c86315859ee724b51748260f50e65 (diff) | |
Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform updates from Arnd Bergmann:
"Newly added support for additional SoCs:
- Axis Artpec-6 SoC family
- Allwinner A83T SoC
- Mediatek MT7623
- NXP i.MX6QP SoC
- ST Microelectronics stm32f469 microcontroller
New features:
- SMP support for Mediatek mt2701
- Big-endian support for NXP i.MX
- DaVinci now uses the new DMA engine dma_slave_map
- OMAP now uses the new DMA engine dma_slave_map
- earlyprintk support for palmchip uart on mach-tango
- delay timer support for orion
Other:
- Exynos PMU driver moved out to drivers/soc/
- Various smaller updates for Renesas, Xilinx, PXA, AT91, OMAP,
uniphier"
* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (83 commits)
ARM: uniphier: rework SMP code to support new System Bus binding
ARM: uniphier: add missing of_node_put()
ARM: at91: avoid defining CONFIG_* symbols in source code
ARM: DRA7: hwmod: Add data for eDMA tpcc, tptc0, tptc1
ARM: imx: Make reset_control_ops const
ARM: imx: Do L2 errata only if the L2 cache isn't enabled
ARM: imx: select ARM_CPU_SUSPEND only for imx6
dmaengine: pxa_dma: fix the maximum requestor line
ARM: alpine: select the Alpine MSI controller driver
ARM: pxa: add the number of DMA requestor lines
dmaengine: mmp-pdma: add number of requestors
dma: mmp_pdma: Add the #dma-requests DT property documentation
ARM: OMAP2+: Add rtc hwmod configuration for ti81xx
ARM: s3c24xx: Avoid warning for inb/outb
ARM: zynq: Move early printk virtual address to vmalloc area
ARM: DRA7: hwmod: Add custom reset handler for PCIeSS
ARM: SAMSUNG: Remove unused register offset definition
ARM: EXYNOS: Cleanup header files inclusion
drivers: soc: samsung: Enable COMPILE_TEST
MAINTAINERS: Add maintainers entry for drivers/soc/samsung
...
Diffstat (limited to 'arch/arm/mach-exynos')
| -rw-r--r-- | arch/arm/mach-exynos/Kconfig | 4 | ||||
| -rw-r--r-- | arch/arm/mach-exynos/Makefile | 2 | ||||
| -rw-r--r-- | arch/arm/mach-exynos/common.h | 1 | ||||
| -rw-r--r-- | arch/arm/mach-exynos/exynos-pmu.h | 24 | ||||
| -rw-r--r-- | arch/arm/mach-exynos/exynos.c | 17 | ||||
| -rw-r--r-- | arch/arm/mach-exynos/firmware.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-exynos/include/mach/map.h | 14 | ||||
| -rw-r--r-- | arch/arm/mach-exynos/mcpm-exynos.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-exynos/platsmp.c | 3 | ||||
| -rw-r--r-- | arch/arm/mach-exynos/pm.c | 8 | ||||
| -rw-r--r-- | arch/arm/mach-exynos/pmu.c | 967 | ||||
| -rw-r--r-- | arch/arm/mach-exynos/regs-pmu.h | 693 | ||||
| -rw-r--r-- | arch/arm/mach-exynos/s5p-dev-mfc.c | 1 | ||||
| -rw-r--r-- | arch/arm/mach-exynos/suspend.c | 4 |
14 files changed, 17 insertions, 1725 deletions
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 5189bcecad12..207fa2c737a6 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -5,7 +5,7 @@ # # Licensed under GPLv2 -# Configuration options for the EXYNOS4 +# Configuration options for the EXYNOS menuconfig ARCH_EXYNOS bool "Samsung EXYNOS" @@ -17,6 +17,7 @@ menuconfig ARCH_EXYNOS select ARM_GIC select COMMON_CLK_SAMSUNG select EXYNOS_THERMAL + select EXYNOS_PMU select HAVE_ARM_SCU if SMP select HAVE_S3C2410_I2C if I2C select HAVE_S3C2410_WATCHDOG if WATCHDOG @@ -25,6 +26,7 @@ menuconfig ARCH_EXYNOS select PINCTRL_EXYNOS select PM_GENERIC_DOMAINS if PM select S5P_DEV_MFC + select SOC_SAMSUNG select SRAM select THERMAL select THERMAL_OF diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile index 2f306767cdfe..34d29df3e006 100644 --- a/arch/arm/mach-exynos/Makefile +++ b/arch/arm/mach-exynos/Makefile @@ -9,7 +9,7 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) += -I$(srctree)/$(src)/include -I$(srctree) # Core -obj-$(CONFIG_ARCH_EXYNOS) += exynos.o pmu.o exynos-smc.o firmware.o +obj-$(CONFIG_ARCH_EXYNOS) += exynos.o exynos-smc.o firmware.o obj-$(CONFIG_EXYNOS_CPU_SUSPEND) += pm.o sleep.o obj-$(CONFIG_PM_SLEEP) += suspend.o diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index e349a038976d..5365bf1f586a 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -12,7 +12,6 @@ #ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H #define __ARCH_ARM_MACH_EXYNOS_COMMON_H -#include <linux/of.h> #include <linux/platform_data/cpuidle-exynos.h> #define EXYNOS3250_SOC_ID 0xE3472000 diff --git a/arch/arm/mach-exynos/exynos-pmu.h b/arch/arm/mach-exynos/exynos-pmu.h deleted file mode 100644 index a2ab0d52b230..000000000000 --- a/arch/arm/mach-exynos/exynos-pmu.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (c) 2014 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * Header for EXYNOS PMU Driver support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef __EXYNOS_PMU_H -#define __EXYNOS_PMU_H - -enum sys_powerdown { - SYS_AFTR, - SYS_LPA, - SYS_SLEEP, - NUM_SYS_POWERDOWN, -}; - -extern void exynos_sys_powerdown_conf(enum sys_powerdown mode); - -#endif /* __EXYNOS_PMU_H */ diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index 1c47aee31e9c..bbf51a46f772 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -11,29 +11,23 @@ #include <linux/init.h> #include <linux/io.h> -#include <linux/kernel.h> -#include <linux/serial_s3c.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_fdt.h> #include <linux/of_platform.h> #include <linux/platform_device.h> -#include <linux/pm_domain.h> #include <linux/irqchip.h> +#include <linux/soc/samsung/exynos-regs-pmu.h> #include <asm/cacheflush.h> #include <asm/hardware/cache-l2x0.h> #include <asm/mach/arch.h> #include <asm/mach/map.h> -#include <asm/memory.h> #include <mach/map.h> #include "common.h" #include "mfc.h" -#include "regs-pmu.h" - -void __iomem *pmu_base_addr; static struct map_desc exynos4_iodesc[] __initdata = { { @@ -70,11 +64,6 @@ static struct map_desc exynos5_iodesc[] __initdata = { .pfn = __phys_to_pfn(EXYNOS5_PA_SROMC), .length = SZ_4K, .type = MT_DEVICE, - }, { - .virtual = (unsigned long)S5P_VA_CMU, - .pfn = __phys_to_pfn(EXYNOS5_PA_CMU), - .length = 144 * SZ_1K, - .type = MT_DEVICE, }, }; @@ -230,6 +219,10 @@ static const struct of_device_id exynos_cpufreq_matches[] = { { .compatible = "samsung,exynos4212", .data = "cpufreq-dt" }, { .compatible = "samsung,exynos4412", .data = "cpufreq-dt" }, { .compatible = "samsung,exynos5250", .data = "cpufreq-dt" }, +#ifndef CONFIG_BL_SWITCHER + { .compatible = "samsung,exynos5420", .data = "cpufreq-dt" }, + { .compatible = "samsung,exynos5800", .data = "cpufreq-dt" }, +#endif { /* sentinel */ } }; diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c index 111cfbf66fdb..1bfd1b0bd9dc 100644 --- a/arch/arm/mach-exynos/firmware.c +++ b/arch/arm/mach-exynos/firmware.c @@ -20,8 +20,6 @@ #include <asm/hardware/cache-l2x0.h> #include <asm/suspend.h> -#include <mach/map.h> - #include "common.h" #include "smc.h" diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h index de3ae59e1cfb..c88325d56743 100644 --- a/arch/arm/mach-exynos/include/mach/map.h +++ b/arch/arm/mach-exynos/include/mach/map.h @@ -2,7 +2,7 @@ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. * http://www.samsung.com/ * - * EXYNOS4 - Memory map definitions + * EXYNOS - Memory map definitions * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -14,30 +14,18 @@ #include <plat/map-base.h> -/* - * EXYNOS4 UART offset is 0x10000 but the older S5P SoCs are 0x400. - * So need to define it, and here is to avoid redefinition warning. - */ -#define S3C_UART_OFFSET (0x10000) - #include <plat/map-s5p.h> #define EXYNOS_PA_CHIPID 0x10000000 #define EXYNOS4_PA_CMU 0x10030000 -#define EXYNOS5_PA_CMU 0x10010000 #define EXYNOS4_PA_DMC0 0x10400000 #define EXYNOS4_PA_DMC1 0x10410000 #define EXYNOS4_PA_COREPERI 0x10500000 -#define EXYNOS4_PA_L2CC 0x10502000 #define EXYNOS4_PA_SROMC 0x12570000 #define EXYNOS5_PA_SROMC 0x12250000 -/* Compatibility UART */ - -#define EXYNOS5440_PA_UART0 0x000B0000 - #endif /* __ASM_ARCH_MAP_H */ diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c index 56978199c479..f086bf615b29 100644 --- a/arch/arm/mach-exynos/mcpm-exynos.c +++ b/arch/arm/mach-exynos/mcpm-exynos.c @@ -16,13 +16,13 @@ #include <linux/io.h> #include <linux/of_address.h> #include <linux/syscore_ops.h> +#include <linux/soc/samsung/exynos-regs-pmu.h> #include <asm/cputype.h> #include <asm/cp15.h> #include <asm/mcpm.h> #include <asm/smp_plat.h> -#include "regs-pmu.h" #include "common.h" #define EXYNOS5420_CPUS_PER_CLUSTER 4 diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index 5bd9559786ba..85c3be63d644 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -15,11 +15,11 @@ #include <linux/init.h> #include <linux/errno.h> #include <linux/delay.h> -#include <linux/device.h> #include <linux/jiffies.h> #include <linux/smp.h> #include <linux/io.h> #include <linux/of_address.h> +#include <linux/soc/samsung/exynos-regs-pmu.h> #include <asm/cacheflush.h> #include <asm/cp15.h> @@ -30,7 +30,6 @@ #include <mach/map.h> #include "common.h" -#include "regs-pmu.h" extern void exynos4_secondary_startup(void); diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index 9c1506b499bc..c43b776a51a3 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -17,7 +17,9 @@ #include <linux/suspend.h> #include <linux/cpu_pm.h> #include <linux/io.h> -#include <linux/err.h> +#include <linux/of.h> +#include <linux/soc/samsung/exynos-regs-pmu.h> +#include <linux/soc/samsung/exynos-pmu.h> #include <asm/firmware.h> #include <asm/smp_scu.h> @@ -26,11 +28,7 @@ #include <mach/map.h> -#include <plat/pm-common.h> - #include "common.h" -#include "exynos-pmu.h" -#include "regs-pmu.h" static inline void __iomem *exynos_boot_vector_addr(void) { diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c deleted file mode 100644 index dbf9fe98d479..000000000000 --- a/arch/arm/mach-exynos/pmu.c +++ /dev/null @@ -1,967 +0,0 @@ -/* - * Copyright (c) 2011-2014 Samsung Electronics Co., Ltd. - * http://www.samsung.com/ - * - * EXYNOS - CPU PMU(Power Management Unit) support - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <linux/io.h> -#include <linux/of.h> -#include <linux/of_address.h> -#include <linux/platform_device.h> -#include <linux/delay.h> - -#include <asm/cputype.h> - -#include "exynos-pmu.h" -#include "regs-pmu.h" - -#define PMU_TABLE_END (-1U) - -struct exynos_pmu_conf { - unsigned int offset; - u8 val[NUM_SYS_POWERDOWN]; -}; - -struct exynos_pmu_data { - const struct exynos_pmu_conf *pmu_config; - const struct exynos_pmu_conf *pmu_config_extra; - - void (*pmu_init)(void); - void (*powerdown_conf)(enum sys_powerdown); - void (*powerdown_conf_extra)(enum sys_powerdown); -}; - -struct exynos_pmu_context { - struct device *dev; - const struct exynos_pmu_data *pmu_data; -}; - -static void __iomem *pmu_base_addr; -static struct exynos_pmu_context *pmu_context; - -static inline void pmu_raw_writel(u32 val, u32 offset) -{ - writel_relaxed(val, pmu_base_addr + offset); -} - -static inline u32 pmu_raw_readl(u32 offset) -{ - return readl_relaxed(pmu_base_addr + offset); -} - -static struct exynos_pmu_conf exynos3250_pmu_config[] = { - /* { .offset = offset, .val = { AFTR, W-AFTR, SLEEP } */ - { EXYNOS3_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} }, - { EXYNOS3_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS3_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS3_ARM_CORE1_SYS_PWR_REG, { 0x0, 0x0, 0x2} }, - { EXYNOS3_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS3_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS3_ISP_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS3_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS3_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS3_ARM_COMMON_SYS_PWR_REG, { 0x0, 0x0, 0x2} }, - { EXYNOS3_ARM_L2_SYS_PWR_REG, { 0x0, 0x0, 0x3} }, - { EXYNOS3_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS3_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS3_CMU_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS3_DRAM_FREQ_DOWN_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, - { EXYNOS3_DDRPHY_DLLOFF_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, - { EXYNOS3_LPDDR_PHY_DLL_LOCK_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, - { EXYNOS3_CMU_ACLKSTOP_COREBLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS3_CMU_SCLKSTOP_COREBLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS3_CMU_RESET_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS3_APLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS3_MPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS3_BPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS3_VPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS3_EPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS3_UPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, - { EXYNOS3_EPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS3_MPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS3_BPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS3_CMU_CLKSTOP_CAM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS3_CMU_CLKSTOP_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS3_CMU_CLKSTOP_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS3_CMU_CLKSTOP_LCD0_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS3_CMU_CLKSTOP_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS3_CMU_CLKSTOP_MAUDIO_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS3_CMU_RESET_CAM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS3_CMU_RESET_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS3_CMU_RESET_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS3_CMU_RESET_LCD0_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS3_CMU_RESET_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS3_CMU_RESET_MAUDIO_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS3_TOP_BUS_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS3_TOP_RETENTION_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, - { EXYNOS3_TOP_PWR_SYS_PWR_REG, { 0x3, 0x3, 0x3} }, - { EXYNOS3_TOP_BUS_COREBLK_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS3_TOP_RETENTION_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, - { EXYNOS3_TOP_PWR_COREBLK_SYS_PWR_REG, { 0x3, 0x3, 0x3} }, - { EXYNOS3_LOGIC_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS3_OSCCLK_GATE_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, - { EXYNOS3_LOGIC_RESET_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS3_OSCCLK_GATE_COREBLK_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, - { EXYNOS3_PAD_RETENTION_DRAM_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS3_PAD_RETENTION_MAUDIO_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS3_PAD_RETENTION_GPIO_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS3_PAD_RETENTION_UART_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS3_PAD_RETENTION_MMC0_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS3_PAD_RETENTION_MMC1_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS3_PAD_RETENTION_MMC2_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS3_PAD_RETENTION_SPI_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS3_PAD_RETENTION_EBIA_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS3_PAD_RETENTION_EBIB_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS3_PAD_RETENTION_JTAG_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS3_PAD_ISOLATION_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS3_PAD_ALV_SEL_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS3_XUSBXTI_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS3_XXTI_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS3_EXT_REGULATOR_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS3_EXT_REGULATOR_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS3_GPIO_MODE_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS3_GPIO_MODE_MAUDIO_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS3_TOP_ASB_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS3_TOP_ASB_ISOLATION_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS3_TOP_ASB_RESET_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS3_TOP_ASB_ISOLATION_COREBLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS3_CAM_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, - { EXYNOS3_MFC_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, - { EXYNOS3_G3D_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, - { EXYNOS3_LCD0_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, - { EXYNOS3_ISP_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, - { EXYNOS3_MAUDIO_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, - { EXYNOS3_CMU_SYSCLK_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { PMU_TABLE_END,}, -}; - -static const struct exynos_pmu_conf exynos4210_pmu_config[] = { - /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */ - { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } }, - { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } }, - { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } }, - { S5P_ARM_CORE1_LOWPWR, { 0x0, 0x0, 0x2 } }, - { S5P_DIS_IRQ_CORE1, { 0x0, 0x0, 0x0 } }, - { S5P_DIS_IRQ_CENTRAL1, { 0x0, 0x0, 0x0 } }, - { S5P_ARM_COMMON_LOWPWR, { 0x0, 0x0, 0x2 } }, - { S5P_L2_0_LOWPWR, { 0x2, 0x2, 0x3 } }, - { S5P_L2_1_LOWPWR, { 0x2, 0x2, 0x3 } }, - { S5P_CMU_ACLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_SCLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_RESET_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_APLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_MPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_VPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_EPLL_SYSCLK_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_RESET_GPSALIVE_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_CLKSTOP_CAM_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_CLKSTOP_TV_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_CLKSTOP_MFC_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_CLKSTOP_G3D_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_CLKSTOP_LCD0_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_CLKSTOP_LCD1_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_CLKSTOP_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_CLKSTOP_GPS_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_RESET_CAM_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_RESET_TV_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_RESET_MFC_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_RESET_G3D_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_RESET_LCD0_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_RESET_LCD1_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_RESET_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_RESET_GPS_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_TOP_BUS_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_TOP_RETENTION_LOWPWR, { 0x1, 0x0, 0x1 } }, - { S5P_TOP_PWR_LOWPWR, { 0x3, 0x0, 0x3 } }, - { S5P_LOGIC_RESET_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_ONENAND_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_MODIMIF_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_G2D_ACP_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_USBOTG_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_HSMMC_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_CSSYS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_SECSS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_PCIE_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_SATA_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_DRAM_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_PAD_RETENTION_GPIO_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_UART_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_MMCA_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_MMCB_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_EBIA_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_EBIB_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_ISOLATION_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_ALV_SEL_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_XUSBXTI_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_XXTI_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_EXT_REGULATOR_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_GPIO_MODE_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_GPIO_MODE_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CAM_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_TV_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_MFC_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_G3D_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_LCD0_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_LCD1_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_MAUDIO_LOWPWR, { 0x7, 0x7, 0x0 } }, - { S5P_GPS_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_GPS_ALIVE_LOWPWR, { 0x7, 0x0, 0x0 } }, - { PMU_TABLE_END,}, -}; - -static const struct exynos_pmu_conf exynos4x12_pmu_config[] = { - { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } }, - { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } }, - { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } }, - { S5P_ARM_CORE1_LOWPWR, { 0x0, 0x0, 0x2 } }, - { S5P_DIS_IRQ_CORE1, { 0x0, 0x0, 0x0 } }, - { S5P_DIS_IRQ_CENTRAL1, { 0x0, 0x0, 0x0 } }, - { S5P_ISP_ARM_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR, { 0x0, 0x0, 0x0 } }, - { S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR, { 0x0, 0x0, 0x0 } }, - { S5P_ARM_COMMON_LOWPWR, { 0x0, 0x0, 0x2 } }, - { S5P_L2_0_LOWPWR, { 0x0, 0x0, 0x3 } }, - /* XXX_OPTION register should be set other field */ - { S5P_ARM_L2_0_OPTION, { 0x10, 0x10, 0x0 } }, - { S5P_L2_1_LOWPWR, { 0x0, 0x0, 0x3 } }, - { S5P_ARM_L2_1_OPTION, { 0x10, 0x10, 0x0 } }, - { S5P_CMU_ACLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_SCLKSTOP_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_RESET_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_DRAM_FREQ_DOWN_LOWPWR, { 0x1, 0x1, 0x1 } }, - { S5P_DDRPHY_DLLOFF_LOWPWR, { 0x1, 0x1, 0x1 } }, - { S5P_LPDDR_PHY_DLL_LOCK_LOWPWR, { 0x1, 0x1, 0x1 } }, - { S5P_CMU_ACLKSTOP_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_SCLKSTOP_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_RESET_COREBLK_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_APLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_MPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_VPLL_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_EPLL_SYSCLK_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_MPLLUSER_SYSCLK_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_RESET_GPSALIVE_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_CLKSTOP_CAM_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_CLKSTOP_TV_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_CLKSTOP_MFC_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_CLKSTOP_G3D_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_CLKSTOP_LCD0_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_CLKSTOP_ISP_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_CLKSTOP_MAUDIO_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_CLKSTOP_GPS_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_RESET_CAM_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_RESET_TV_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_RESET_MFC_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_RESET_G3D_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_RESET_LCD0_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_RESET_ISP_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_RESET_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_CMU_RESET_GPS_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_TOP_BUS_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_TOP_RETENTION_LOWPWR, { 0x1, 0x0, 0x1 } }, - { S5P_TOP_PWR_LOWPWR, { 0x3, 0x0, 0x3 } }, - { S5P_TOP_BUS_COREBLK_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_TOP_RETENTION_COREBLK_LOWPWR, { 0x1, 0x0, 0x1 } }, - { S5P_TOP_PWR_COREBLK_LOWPWR, { 0x3, 0x0, 0x3 } }, - { S5P_LOGIC_RESET_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_OSCCLK_GATE_LOWPWR, { 0x1, 0x0, 0x1 } }, - { S5P_LOGIC_RESET_COREBLK_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_OSCCLK_GATE_COREBLK_LOWPWR, { 0x1, 0x0, 0x1 } }, - { S5P_ONENAND_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_ONENAND_MEM_OPTION, { 0x10, 0x10, 0x0 } }, - { S5P_HSI_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_HSI_MEM_OPTION, { 0x10, 0x10, 0x0 } }, - { S5P_G2D_ACP_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_G2D_ACP_MEM_OPTION, { 0x10, 0x10, 0x0 } }, - { S5P_USBOTG_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_USBOTG_MEM_OPTION, { 0x10, 0x10, 0x0 } }, - { S5P_HSMMC_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_HSMMC_MEM_OPTION, { 0x10, 0x10, 0x0 } }, - { S5P_CSSYS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_CSSYS_MEM_OPTION, { 0x10, 0x10, 0x0 } }, - { S5P_SECSS_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_SECSS_MEM_OPTION, { 0x10, 0x10, 0x0 } }, - { S5P_ROTATOR_MEM_LOWPWR, { 0x3, 0x0, 0x0 } }, - { S5P_ROTATOR_MEM_OPTION, { 0x10, 0x10, 0x0 } }, - { S5P_PAD_RETENTION_DRAM_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_PAD_RETENTION_GPIO_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_UART_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_MMCA_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_MMCB_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_EBIA_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_EBIB_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR,{ 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_ISOLATION_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_ISOLATION_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_PAD_RETENTION_ALV_SEL_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_XUSBXTI_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_XXTI_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_EXT_REGULATOR_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_GPIO_MODE_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_GPIO_MODE_COREBLK_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_GPIO_MODE_MAUDIO_LOWPWR, { 0x1, 0x1, 0x0 } }, - { S5P_TOP_ASB_RESET_LOWPWR, { 0x1, 0x1, 0x1 } }, - { S5P_TOP_ASB_ISOLATION_LOWPWR, { 0x1, 0x0, 0x1 } }, - { S5P_CAM_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_TV_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_MFC_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_G3D_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_LCD0_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_ISP_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_MAUDIO_LOWPWR, { 0x7, 0x7, 0x0 } }, - { S5P_GPS_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_GPS_ALIVE_LOWPWR, { 0x7, 0x0, 0x0 } }, - { S5P_CMU_SYSCLK_ISP_LOWPWR, { 0x1, 0x0, 0x0 } }, - { S5P_CMU_SYSCLK_GPS_LOWPWR, { 0x1, 0x0, 0x0 } }, - { PMU_TABLE_END,}, -}; - -static const struct exynos_pmu_conf exynos4412_pmu_config[] = { - { S5P_ARM_CORE2_LOWPWR, { 0x0, 0x0, 0x2 } }, - { S5P_DIS_IRQ_CORE2, { 0x0, 0x0, 0x0 } }, - { S5P_DIS_IRQ_CENTRAL2, { 0x0, 0x0, 0x0 } }, - { S5P_ARM_CORE3_LOWPWR, { 0x0, 0x0, 0x2 } }, - { S5P_DIS_IRQ_CORE3, { 0x0, 0x0, 0x0 } }, - { S5P_DIS_IRQ_CENTRAL3, { 0x0, 0x0, 0x0 } }, - { PMU_TABLE_END,}, -}; - -static const struct exynos_pmu_conf exynos5250_pmu_config[] = { - /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */ - { EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x2} }, - { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5_ARM_CORE1_SYS_PWR_REG, { 0x0, 0x0, 0x2} }, - { EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5_FSYS_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, - { EXYNOS5_ISP_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5_ARM_COMMON_SYS_PWR_REG, { 0x0, 0x0, 0x2} }, - { EXYNOS5_ARM_L2_SYS_PWR_REG, { 0x3, 0x3, 0x3} }, - { EXYNOS5_ARM_L2_OPTION, { 0x10, 0x10, 0x0 } }, - { EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, - { EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, - { EXYNOS5_CMU_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, - { EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, - { EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, - { EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, - { EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, - { EXYNOS5_APLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_TOP_BUS_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_TOP_RETENTION_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, - { EXYNOS5_TOP_PWR_SYS_PWR_REG, { 0x3, 0x0, 0x3} }, - { EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, - { EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG, { 0x3, 0x0, 0x3} }, - { EXYNOS5_LOGIC_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_OSCCLK_GATE_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, - { EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, - { EXYNOS5_USBOTG_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_G2D_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_USBDRD_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_SDMMC_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_CSSYS_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_SECSS_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_ROTATOR_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_INTRAM_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_INTROM_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_JPEG_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_JPEG_MEM_OPTION, { 0x10, 0x10, 0x0} }, - { EXYNOS5_HSI_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_MCUIOP_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_SATA_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_PAD_ISOLATION_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_XUSBXTI_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, - { EXYNOS5_XXTI_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_EXT_REGULATOR_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_GPIO_MODE_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, - { EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, - { EXYNOS5_GSCL_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, - { EXYNOS5_ISP_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, - { EXYNOS5_MFC_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, - { EXYNOS5_G3D_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, - { EXYNOS5_DISP1_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, - { EXYNOS5_MAU_SYS_PWR_REG, { 0x7, 0x7, 0x0} }, - { EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { PMU_TABLE_END,}, -}; - -static struct exynos_pmu_conf exynos5420_pmu_config[] = { - /* { .offset = offset, .val = { AFTR, LPA, SLEEP } */ - { EXYNOS5_ARM_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5_ARM_CORE1_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_ARM_CORE2_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_DIS_IRQ_ARM_CORE2_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_DIS_IRQ_ARM_CORE2_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_ARM_CORE3_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_DIS_IRQ_ARM_CORE3_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_DIS_IRQ_ARM_CORE3_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_KFC_CORE0_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_DIS_IRQ_KFC_CORE0_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_DIS_IRQ_KFC_CORE0_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_KFC_CORE1_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_DIS_IRQ_KFC_CORE1_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_DIS_IRQ_KFC_CORE1_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_KFC_CORE2_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_DIS_IRQ_KFC_CORE2_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_DIS_IRQ_KFC_CORE2_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_KFC_CORE3_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_DIS_IRQ_KFC_CORE3_LOCAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_DIS_IRQ_KFC_CORE3_CENTRAL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5_ISP_ARM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5420_ARM_COMMON_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_KFC_COMMON_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5_ARM_L2_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_KFC_L2_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, - { EXYNOS5_CMU_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, - { EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, - { EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, - { EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, - { EXYNOS5_APLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5420_DPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5420_IPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5420_KPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5420_RPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5420_SPLL_SYSCLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_TOP_BUS_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_TOP_RETENTION_SYS_PWR_REG, { 0x1, 0x1, 0x1} }, - { EXYNOS5_TOP_PWR_SYS_PWR_REG, { 0x3, 0x3, 0x0} }, - { EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, - { EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG, { 0x3, 0x0, 0x0} }, - { EXYNOS5_LOGIC_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_OSCCLK_GATE_SYS_PWR_REG, { 0x1, 0x0, 0x1} }, - { EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5420_INTRAM_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x3} }, - { EXYNOS5420_INTROM_MEM_SYS_PWR_REG, { 0x3, 0x0, 0x3} }, - { EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5420_PAD_RETENTION_JTAG_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5420_PAD_RETENTION_DRAM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5420_PAD_RETENTION_UART_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5420_PAD_RETENTION_MMC0_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5420_PAD_RETENTION_MMC1_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5420_PAD_RETENTION_MMC2_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5420_PAD_RETENTION_HSI_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5420_PAD_RETENTION_EBIA_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5420_PAD_RETENTION_EBIB_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5420_PAD_RETENTION_SPI_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5420_PAD_RETENTION_DRAM_COREBLK_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_PAD_ISOLATION_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_XUSBXTI_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_XXTI_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_EXT_REGULATOR_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_GPIO_MODE_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG, { 0x1, 0x1, 0x0} }, - { EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG, { 0x1, 0x0, 0x0} }, - { EXYNOS5_GSCL_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, - { EXYNOS5_ISP_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, - { EXYNOS5_MFC_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, - { EXYNOS5_G3D_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, - { EXYNOS5420_DISP1_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, - { EXYNOS5420_MAU_SYS_PWR_REG, { 0x7, 0x7, 0x0} }, - { EXYNOS5420_G2D_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, - { EXYNOS5420_MSC_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, - { EXYNOS5420_FSYS_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, - { EXYNOS5420_FSYS2_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, - { EXYNOS5420_PSGEN_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, - { EXYNOS5420_PERIC_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, - { EXYNOS5420_WCORE_SYS_PWR_REG, { 0x7, 0x0, 0x0} }, - { EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_CMU_CLKSTOP_DISP1_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_CMU_CLKSTOP_MAU_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_CMU_CLKSTOP_G2D_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_CMU_CLKSTOP_MSC_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_CMU_CLKSTOP_FSYS_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_CMU_CLKSTOP_PSGEN_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_CMU_CLKSTOP_PERIC_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_CMU_CLKSTOP_WCORE_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_CMU_SYSCLK_DISP1_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_CMU_SYSCLK_MAU_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_CMU_SYSCLK_G2D_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_CMU_SYSCLK_MSC_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_CMU_SYSCLK_FSYS_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_CMU_SYSCLK_FSYS2_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_CMU_SYSCLK_PSGEN_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_CMU_SYSCLK_PERIC_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_CMU_SYSCLK_WCORE_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_CMU_RESET_FSYS2_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_CMU_RESET_PSGEN_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_CMU_RESET_PERIC_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_CMU_RESET_WCORE_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_CMU_RESET_DISP1_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_CMU_RESET_MAU_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_CMU_RESET_G2D_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_CMU_RESET_MSC_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG, { 0x0, 0x0, 0x0} }, - { PMU_TABLE_END,}, -}; - -static unsigned int const exynos3250_list_feed[] = { - EXYNOS3_ARM_CORE_OPTION(0), - EXYNOS3_ARM_CORE_OPTION(1), - EXYNOS3_ARM_CORE_OPTION(2), - EXYNOS3_ARM_CORE_OPTION(3), - EXYNOS3_ARM_COMMON_OPTION, - EXYNOS3_TOP_PWR_OPTION, - EXYNOS3_CORE_TOP_PWR_OPTION, - S5P_CAM_OPTION, - S5P_MFC_OPTION, - S5P_G3D_OPTION, - S5P_LCD0_OPTION, - S5P_ISP_OPTION, -}; - -static void exynos3250_powerdown_conf_extra(enum sys_powerdown mode) -{ - unsigned int i; - unsigned int tmp; - - /* Enable only SC_FEEDBACK */ - for (i = 0; i < ARRAY_SIZE(exynos3250_list_feed); i++) { - tmp = pmu_raw_readl(exynos3250_list_feed[i]); - tmp &= ~(EXYNOS3_OPTION_USE_SC_COUNTER); - tmp |= EXYNOS3_OPTION_USE_SC_FEEDBACK; - pmu_raw_writel(tmp, exynos3250_list_feed[i]); - } - - if (mode != SYS_SLEEP) - return; - - pmu_raw_writel(XUSBXTI_DURATION, EXYNOS3_XUSBXTI_DURATION); - pmu_raw_writel(XXTI_DURATION, EXYNOS3_XXTI_DURATION); - pmu_raw_writel(EXT_REGULATOR_DURATION, EXYNOS3_EXT_REGULATOR_DURATION); - pmu_raw_writel(EXT_REGULATOR_COREBLK_DURATION, - EXYNOS3_EXT_REGULATOR_COREBLK_DURATION); -} - -static unsigned int const exynos5_list_both_cnt_feed[] = { - EXYNOS5_ARM_CORE0_OPTION, - EXYNOS5_ARM_CORE1_OPTION, - EXYNOS5_ARM_COMMON_OPTION, - EXYNOS5_GSCL_OPTION, - EXYNOS5_ISP_OPTION, - EXYNOS5_MFC_OPTION, - EXYNOS5_G3D_OPTION, - EXYNOS5_DISP1_OPTION, - EXYNOS5_MAU_OPTION, - EXYNOS5_TOP_PWR_OPTION, - EXYNOS5_TOP_PWR_SYSMEM_OPTION, -}; - -static unsigned int const exynos5_list_disable_wfi_wfe[] = { - EXYNOS5_ARM_CORE1_OPTION, - EXYNOS5_FSYS_ARM_OPTION, - EXYNOS5_ISP_ARM_OPTION, -}; - -static unsigned int const exynos5420_list_disable_pmu_reg[] = { - EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG, - EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG, - EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG, - EXYNOS5420_CMU_CLKSTOP_DISP1_SYS_PWR_REG, - EXYNOS5420_CMU_CLKSTOP_MAU_SYS_PWR_REG, - EXYNOS5420_CMU_CLKSTOP_G2D_SYS_PWR_REG, - EXYNOS5420_CMU_CLKSTOP_MSC_SYS_PWR_REG, - EXYNOS5420_CMU_CLKSTOP_FSYS_SYS_PWR_REG, - EXYNOS5420_CMU_CLKSTOP_PSGEN_SYS_PWR_REG, - EXYNOS5420_CMU_CLKSTOP_PERIC_SYS_PWR_REG, - EXYNOS5420_CMU_CLKSTOP_WCORE_SYS_PWR_REG, - EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG, - EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG, - EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG, - EXYNOS5420_CMU_SYSCLK_DISP1_SYS_PWR_REG, - EXYNOS5420_CMU_SYSCLK_MAU_SYS_PWR_REG, - EXYNOS5420_CMU_SYSCLK_G2D_SYS_PWR_REG, - EXYNOS5420_CMU_SYSCLK_MSC_SYS_PWR_REG, - EXYNOS5420_CMU_SYSCLK_FSYS_SYS_PWR_REG, - EXYNOS5420_CMU_SYSCLK_FSYS2_SYS_PWR_REG, - EXYNOS5420_CMU_SYSCLK_PSGEN_SYS_PWR_REG, - EXYNOS5420_CMU_SYSCLK_PERIC_SYS_PWR_REG, - EXYNOS5420_CMU_SYSCLK_WCORE_SYS_PWR_REG, - EXYNOS5420_CMU_RESET_FSYS2_SYS_PWR_REG, - EXYNOS5420_CMU_RESET_PSGEN_SYS_PWR_REG, - EXYNOS5420_CMU_RESET_PERIC_SYS_PWR_REG, - EXYNOS5420_CMU_RESET_WCORE_SYS_PWR_REG, - EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG, - EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG, - EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG, - EXYNOS5420_CMU_RESET_DISP1_SYS_PWR_REG, - EXYNOS5420_CMU_RESET_MAU_SYS_PWR_REG, - EXYNOS5420_CMU_RESET_G2D_SYS_PWR_REG, - EXYNOS5420_CMU_RESET_MSC_SYS_PWR_REG, - EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG, -}; - -static void exynos5420_powerdown_conf(enum sys_powerdown mode) -{ - u32 this_cluster; - - this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1); - - /* - * set the cluster id to IROM register to ensure that we wake - * up with the current cluster. - */ - pmu_raw_writel(this_cluster, EXYNOS_IROM_DATA2); -} - - -static void exynos5_powerdown_conf(enum sys_powerdown mode) -{ - unsigned int i; - unsigned int tmp; - - /* - * Enable both SC_FEEDBACK and SC_COUNTER - */ - for (i = 0; i < ARRAY_SIZE(exynos5_list_both_cnt_feed); i++) { - tmp = pmu_raw_readl(exynos5_list_both_cnt_feed[i]); - tmp |= (EXYNOS5_USE_SC_FEEDBACK | - EXYNOS5_USE_SC_COUNTER); - pmu_raw_writel(tmp, exynos5_list_both_cnt_feed[i]); - } - - /* - * SKIP_DEACTIVATE_ACEACP_IN_PWDN_BITFIELD Enable - */ - tmp = pmu_raw_readl(EXYNOS5_ARM_COMMON_OPTION); - tmp |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN; - pmu_raw_writel(tmp, EXYNOS5_ARM_COMMON_OPTION); - - /* - * Disable WFI/WFE on XXX_OPTION - */ - for (i = 0; i < ARRAY_SIZE(exynos5_list_disable_wfi_wfe); i++) { - tmp = pmu_raw_readl(exynos5_list_disable_wfi_wfe[i]); - tmp &= ~(EXYNOS5_OPTION_USE_STANDBYWFE | - EXYNOS5_OPTION_USE_STANDBYWFI); - pmu_raw_writel(tmp, exynos5_list_disable_wfi_wfe[i]); - } -} - -void exynos_sys_powerdown_conf(enum sys_powerdown mode) -{ - unsigned int i; - const struct exynos_pmu_data *pmu_data; - - if (!pmu_context) - return; - - pmu_data = pmu_context->pmu_data; - - if (pmu_data->powerdown_conf) - pmu_data->powerdown_conf(mode); - - if (pmu_data->pmu_config) { - for (i = 0; (pmu_data->pmu_config[i].offset != PMU_TABLE_END); i++) - pmu_raw_writel(pmu_data->pmu_config[i].val[mode], - pmu_data->pmu_config[i].offset); - } - - if (pmu_data->powerdown_conf_extra) - pmu_data->powerdown_conf_extra(mode); - - if (pmu_data->pmu_config_extra) { - for (i = 0; pmu_data->pmu_config_extra[i].offset != PMU_TABLE_END; i++) - pmu_raw_writel(pmu_data->pmu_config_extra[i].val[mode], - pmu_data->pmu_config_extra[i].offset); - } -} - -static void exynos3250_pmu_init(void) -{ - unsigned int value; - - /* - * To prevent from issuing new bus request form L2 memory system - * If core status is power down, should be set '1' to L2 power down - */ - value = pmu_raw_readl(EXYNOS3_ARM_COMMON_OPTION); - value |= EXYNOS3_OPTION_SKIP_DEACTIVATE_ACEACP_IN_PWDN; - pmu_raw_writel(value, EXYNOS3_ARM_COMMON_OPTION); - - /* Enable USE_STANDBY_WFI for all CORE */ - pmu_raw_writel(S5P_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION); - - /* - * Set PSHOLD port for output high - */ - value = pmu_raw_readl(S5P_PS_HOLD_CONTROL); - value |= S5P_PS_HOLD_OUTPUT_HIGH; - pmu_raw_writel(value, S5P_PS_HOLD_CONTROL); - - /* - * Enable signal for PSHOLD port - */ - value = pmu_raw_readl(S5P_PS_HOLD_CONTROL); - value |= S5P_PS_HOLD_EN; - pmu_raw_writel(value, S5P_PS_HOLD_CONTROL); -} - -static void exynos5250_pmu_init(void) -{ - unsigned int value; - /* - * When SYS_WDTRESET is set, watchdog timer reset request - * is ignored by power management unit. - */ - value = pmu_raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE); - value &= ~EXYNOS5_SYS_WDTRESET; - pmu_raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE); - - value = pmu_raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST); - value &= ~EXYNOS5_SYS_WDTRESET; - pmu_raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST); -} - -static void exynos5420_pmu_init(void) -{ - unsigned int value; - int i; - - /* - * Set the CMU_RESET, CMU_SYSCLK and CMU_CLKSTOP registers - * for local power blocks to Low initially as per Table 8-4: - * "System-Level Power-Down Configuration Registers". - */ - for (i = 0; i < ARRAY_SIZE(exynos5420_list_disable_pmu_reg); i++) - pmu_raw_writel(0, exynos5420_list_disable_pmu_reg[i]); - - /* Enable USE_STANDBY_WFI for all CORE */ - pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION); - - value = pmu_raw_readl(EXYNOS_L2_OPTION(0)); - value &= ~EXYNOS5_USE_RETENTION; - pmu_raw_writel(value, EXYNOS_L2_OPTION(0)); - - value = pmu_raw_readl(EXYNOS_L2_OPTION(1)); - value &= ~EXYNOS5_USE_RETENTION; - pmu_raw_writel(value, EXYNOS_L2_OPTION(1)); - - /* - * If L2_COMMON is turned off, clocks related to ATB async - * bridge are gated. Thus, when ISP power is gated, LPI - * may get stuck. - */ - value = pmu_raw_readl(EXYNOS5420_LPI_MASK); - value |= EXYNOS5420_ATB_ISP_ARM; - pmu_raw_writel(value, EXYNOS5420_LPI_MASK); - - value = pmu_raw_readl(EXYNOS5420_LPI_MASK1); - value |= EXYNOS5420_ATB_KFC; - pmu_raw_writel(value, EXYNOS5420_LPI_MASK1); - - /* Prevent issue of new bus request from L2 memory */ - value = pmu_raw_readl(EXYNOS5420_ARM_COMMON_OPTION); - value |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN; - pmu_raw_writel(value, EXYNOS5420_ARM_COMMON_OPTION); - - value = pmu_raw_readl(EXYNOS5420_KFC_COMMON_OPTION); - value |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN; - pmu_raw_writel(value, EXYNOS5420_KFC_COMMON_OPTION); - - /* This setting is to reduce suspend/resume time */ - pmu_raw_writel(DUR_WAIT_RESET, EXYNOS5420_LOGIC_RESET_DURATION3); - - /* Serialized CPU wakeup of Eagle */ - pmu_raw_writel(SPREAD_ENABLE, EXYNOS5420_ARM_INTR_SPREAD_ENABLE); - - pmu_raw_writel(SPREAD_USE_STANDWFI, - EXYNOS5420_ARM_INTR_SPREAD_USE_STANDBYWFI); - - pmu_raw_writel(0x1, EXYNOS5420_UP_SCHEDULER); - pr_info("EXYNOS5420 PMU initialized\n"); -} - -static const struct exynos_pmu_data exynos3250_pmu_data = { - .pmu_config = exynos3250_pmu_config, - .pmu_init = exynos3250_pmu_init, - .powerdown_conf_extra = exynos3250_powerdown_conf_extra, -}; - -static const struct exynos_pmu_data exynos4210_pmu_data = { - .pmu_config = exynos4210_pmu_config, -}; - -static const struct exynos_pmu_data exynos4212_pmu_data = { - .pmu_config = exynos4x12_pmu_config, -}; - -static const struct exynos_pmu_data exynos4412_pmu_data = { - .pmu_config = exynos4x12_pmu_config, - .pmu_config_extra = exynos4412_pmu_config, -}; - -static const struct exynos_pmu_data exynos5250_pmu_data = { - .pmu_config = exynos5250_pmu_config, - .pmu_init = exynos5250_pmu_init, - .powerdown_conf = exynos5_powerdown_conf, -}; - -static const struct exynos_pmu_data exynos5420_pmu_data = { - .pmu_config = exynos5420_pmu_config, - .pmu_init = exynos5420_pmu_init, - .powerdown_conf = exynos5420_powerdown_conf, -}; - -/* - * PMU platform driver and devicetree bindings. - */ -static const struct of_device_id exynos_pmu_of_device_ids[] = { - { - .compatible = "samsung,exynos3250-pmu", - .data = &exynos3250_pmu_data, - }, { - .compatible = "samsung,exynos4210-pmu", - .data = &exynos4210_pmu_data, - }, { - .compatible = "samsung,exynos4212-pmu", - .data = &exynos4212_pmu_data, - }, { - .compatible = "samsung,exynos4412-pmu", - .data = &exynos4412_pmu_data, - }, { - .compatible = "samsung,exynos5250-pmu", - .data = &exynos5250_pmu_data, - }, { - .compatible = "samsung,exynos5420-pmu", - .data = &exynos5420_pmu_data, - }, - { /*sentinel*/ }, -}; - -static int exynos_pmu_probe(struct platform_device *pdev) -{ - const struct of_device_id *match; - struct device *dev = &pdev->dev; - struct resource *res; - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - pmu_base_addr = devm_ioremap_resource(dev, res); - if (IS_ERR(pmu_base_addr)) - return PTR_ERR(pmu_base_addr); - - pmu_context = devm_kzalloc(&pdev->dev, - sizeof(struct exynos_pmu_context), - GFP_KERNEL); - if (!pmu_context) { - dev_err(dev, "Cannot allocate memory.\n"); - return -ENOMEM; - } - pmu_context->dev = dev; - - match = of_match_node(exynos_pmu_of_device_ids, dev->of_node); - - pmu_context->pmu_data = match->data; - - if (pmu_context->pmu_data->pmu_init) - pmu_context->pmu_data->pmu_init(); - - platform_set_drvdata(pdev, pmu_context); - - dev_dbg(dev, "Exynos PMU Driver probe done\n"); - return 0; -} - -static struct platform_driver exynos_pmu_driver = { - .driver = { - .name = "exynos-pmu", - .of_match_table = exynos_pmu_of_device_ids, - }, - .probe = exynos_pmu_probe, -}; - -static int __init exynos_pmu_init(void) -{ - return platform_driver_register(&exynos_pmu_driver); - -} -postcore_initcall(exynos_pmu_init); diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h deleted file mode 100644 index 5e4f4c23b06a..000000000000 --- a/arch/arm/mach-exynos/regs-pmu.h +++ /dev/null @@ -1,693 +0,0 @@ -/* - * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * - * EXYNOS - Power management unit definition - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#ifndef __ASM_ARCH_REGS_PMU_H -#define __ASM_ARCH_REGS_PMU_H __FILE__ - -#define S5P_CENTRAL_SEQ_CONFIGURATION 0x0200 - -#define S5P_CENTRAL_LOWPWR_CFG (1 << 16) - -#define S5P_CENTRAL_SEQ_OPTION 0x0208 - -#define S5P_USE_STANDBY_WFI0 (1 << 16) -#define S5P_USE_STANDBY_WFI1 (1 << 17) -#define S5P_USE_STANDBY_WFI2 (1 << 19) -#define S5P_USE_STANDBY_WFI3 (1 << 20) -#define S5P_USE_STANDBY_WFE0 (1 << 24) -#define S5P_USE_STANDBY_WFE1 (1 << 25) -#define S5P_USE_STANDBY_WFE2 (1 << 27) -#define S5P_USE_STANDBY_WFE3 (1 << 28) - -#define S5P_USE_STANDBY_WFI_ALL \ - (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFI1 | \ - S5P_USE_STANDBY_WFI2 | S5P_USE_STANDBY_WFI3 | \ - S5P_USE_STANDBY_WFE0 | S5P_USE_STANDBY_WFE1 | \ - S5P_USE_STANDBY_WFE2 | S5P_USE_STANDBY_WFE3) - -#define S5P_USE_DELAYED_RESET_ASSERTION BIT(12) - -#define EXYNOS_CORE_PO_RESET(n) ((1 << 4) << n) -#define EXYNOS_WAKEUP_FROM_LOWPWR (1 << 28) -#define EXYNOS_SWRESET 0x0400 -#define EXYNOS5440_SWRESET 0x00C4 - -#define S5P_WAKEUP_STAT 0x0600 -#define S5P_EINT_WAKEUP_MASK 0x0604 -#define S5P_WAKEUP_MASK 0x0608 -#define S5P_WAKEUP_MASK2 0x0614 - -#define S5P_INFORM0 0x0800 -#define S5P_INFORM1 0x0804 -#define S5P_INFORM5 0x0814 -#define S5P_INFORM6 0x0818 -#define S5P_INFORM7 0x081C -#define S5P_PMU_SPARE2 0x0908 -#define S5P_PMU_SPARE3 0x090C - -#define EXYNOS_IROM_DATA2 0x0988 -#define S5P_ARM_CORE0_LOWPWR 0x1000 -#define S5P_DIS_IRQ_CORE0 0x1004 -#define S5P_DIS_IRQ_CENTRAL0 0x1008 -#define S5P_ARM_CORE1_LOWPWR 0x1010 -#define S5P_DIS_IRQ_CORE1 0x1014 -#define S5P_DIS_IRQ_CENTRAL1 0x1018 -#define S5P_ARM_COMMON_LOWPWR 0x1080 -#define S5P_L2_0_LOWPWR 0x10C0 -#define S5P_L2_1_LOWPWR 0x10C4 -#define S5P_CMU_ACLKSTOP_LOWPWR 0x1100 -#define S5P_CMU_SCLKSTOP_LOWPWR 0x1104 -#define S5P_CMU_RESET_LOWPWR 0x110C -#define S5P_APLL_SYSCLK_LOWPWR 0x1120 -#define S5P_MPLL_SYSCLK_LOWPWR 0x1124 -#define S5P_VPLL_SYSCLK_LOWPWR 0x1128 -#define S5P_EPLL_SYSCLK_LOWPWR 0x112C -#define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR 0x1138 -#define S5P_CMU_RESET_GPSALIVE_LOWPWR 0x113C -#define S5P_CMU_CLKSTOP_CAM_LOWPWR 0x1140 -#define S5P_CMU_CLKSTOP_TV_LOWPWR 0x1144 -#define S5P_CMU_CLKSTOP_MFC_LOWPWR 0x1148 -#define S5P_CMU_CLKSTOP_G3D_LOWPWR 0x114C -#define S5P_CMU_CLKSTOP_LCD0_LOWPWR 0x1150 -#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR 0x1158 -#define S5P_CMU_CLKSTOP_GPS_LOWPWR 0x115C -#define S5P_CMU_RESET_CAM_LOWPWR 0x1160 -#define S5P_CMU_RESET_TV_LOWPWR 0x1164 -#define S5P_CMU_RESET_MFC_LOWPWR 0x1168 -#define S5P_CMU_RESET_G3D_LOWPWR 0x116C -#define S5P_CMU_RESET_LCD0_LOWPWR 0x1170 -#define S5P_CMU_RESET_MAUDIO_LOWPWR 0x1178 -#define S5P_CMU_RESET_GPS_LOWPWR 0x117C -#define S5P_TOP_BUS_LOWPWR 0x1180 -#define S5P_TOP_RETENTION_LOWPWR 0x1184 -#define S5P_TOP_PWR_LOWPWR 0x1188 -#define S5P_LOGIC_RESET_LOWPWR 0x11A0 -#define S5P_ONENAND_MEM_LOWPWR 0x11C0 -#define S5P_G2D_ACP_MEM_LOWPWR 0x11C8 -#define S5P_USBOTG_MEM_LOWPWR 0x11CC -#define S5P_HSMMC_MEM_LOWPWR 0x11D0 -#define S5P_CSSYS_MEM_LOWPWR 0x11D4 -#define S5P_SECSS_MEM_LOWPWR 0x11D8 -#define S5P_PAD_RETENTION_DRAM_LOWPWR 0x1200 -#define S5P_PAD_RETENTION_MAUDIO_LOWPWR 0x1204 -#define S5P_PAD_RETENTION_GPIO_LOWPWR 0x1220 -#define S5P_PAD_RETENTION_UART_LOWPWR 0x1224 -#define S5P_PAD_RETENTION_MMCA_LOWPWR 0x1228 -#define S5P_PAD_RETENTION_MMCB_LOWPWR 0x122C -#define S5P_PAD_RETENTION_EBIA_LOWPWR 0x1230 -#define S5P_PAD_RETENTION_EBIB_LOWPWR 0x1234 -#define S5P_PAD_RETENTION_ISOLATION_LOWPWR 0x1240 -#define S5P_PAD_RETENTION_ALV_SEL_LOWPWR 0x1260 -#define S5P_XUSBXTI_LOWPWR 0x1280 -#define S5P_XXTI_LOWPWR 0x1284 -#define S5P_EXT_REGULATOR_LOWPWR 0x12C0 -#define S5P_GPIO_MODE_LOWPWR 0x1300 -#define S5P_GPIO_MODE_MAUDIO_LOWPWR 0x1340 -#define S5P_CAM_LOWPWR 0x1380 -#define S5P_TV_LOWPWR 0x1384 -#define S5P_MFC_LOWPWR 0x1388 -#define S5P_G3D_LOWPWR 0x138C -#define S5P_LCD0_LOWPWR 0x1390 -#define S5P_MAUDIO_LOWPWR 0x1398 -#define S5P_GPS_LOWPWR 0x139C -#define S5P_GPS_ALIVE_LOWPWR 0x13A0 - -#define EXYNOS_ARM_CORE0_CONFIGURATION 0x2000 -#define EXYNOS_ARM_CORE_CONFIGURATION(_nr) \ - (EXYNOS_ARM_CORE0_CONFIGURATION + (0x80 * (_nr))) -#define EXYNOS_ARM_CORE_STATUS(_nr) \ - (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4) -#define EXYNOS_ARM_CORE_OPTION(_nr) \ - (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x8) - -#define EXYNOS_ARM_COMMON_CONFIGURATION 0x2500 -#define EXYNOS_COMMON_CONFIGURATION(_nr) \ - (EXYNOS_ARM_COMMON_CONFIGURATION + (0x80 * (_nr))) -#define EXYNOS_COMMON_STATUS(_nr) \ - (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x4) -#define EXYNOS_COMMON_OPTION(_nr) \ - (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x8) - -#define EXYNOS_CORE_LOCAL_PWR_EN 0x3 - -#define EXYNOS_ARM_COMMON_STATUS 0x2504 -#define EXYNOS_COMMON_OPTION(_nr) \ - (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x8) - -#define EXYNOS_ARM_L2_CONFIGURATION 0x2600 -#define EXYNOS_L2_CONFIGURATION(_nr) \ - (EXYNOS_ARM_L2_CONFIGURATION + ((_nr) * 0x80)) -#define EXYNOS_L2_STATUS(_nr) \ - (EXYNOS_L2_CONFIGURATION(_nr) + 0x4) -#define EXYNOS_L2_OPTION(_nr) \ - (EXYNOS_L2_CONFIGURATION(_nr) + 0x8) -#define EXYNOS_L2_COMMON_PWR_EN 0x3 - -#define EXYNOS_ARM_CORE_X_STATUS_OFFSET 0x4 - -#define EXYNOS5_APLL_SYSCLK_CONFIGURATION 0x2A00 -#define EXYNOS5_APLL_SYSCLK_STATUS 0x2A04 - -#define EXYNOS5_ARM_L2_OPTION 0x2608 -#define EXYNOS5_USE_RETENTION BIT(4) - -#define EXYNOS5_L2RSTDISABLE_VALUE BIT(3) - -#define S5P_PAD_RET_MAUDIO_OPTION 0x3028 -#define S5P_PAD_RET_MMC2_OPTION 0x30c8 -#define S5P_PAD_RET_GPIO_OPTION 0x3108 -#define S5P_PAD_RET_UART_OPTION 0x3128 -#define S5P_PAD_RET_MMCA_OPTION 0x3148 -#define S5P_PAD_RET_MMCB_OPTION 0x3168 -#define S5P_PAD_RET_EBIA_OPTION 0x3188 -#define S5P_PAD_RET_EBIB_OPTION 0x31A8 -#define S5P_PAD_RET_SPI_OPTION 0x31c8 - -#define S5P_PS_HOLD_CONTROL 0x330C -#define S5P_PS_HOLD_EN (1 << 31) -#define S5P_PS_HOLD_OUTPUT_HIGH (3 << 8) - -#define S5P_CAM_OPTION 0x3C08 -#define S5P_MFC_OPTION 0x3C48 -#define S5P_G3D_OPTION 0x3C68 -#define S5P_LCD0_OPTION 0x3C88 -#define S5P_LCD1_OPTION 0x3CA8 -#define S5P_ISP_OPTION S5P_LCD1_OPTION - -#define S5P_CORE_LOCAL_PWR_EN 0x3 -#define S5P_CORE_WAKEUP_FROM_LOCAL_CFG (0x3 << 8) -#define S5P_CORE_AUTOWAKEUP_EN (1 << 31) - -/* Only for EXYNOS4210 */ -#define S5P_CMU_CLKSTOP_LCD1_LOWPWR 0x1154 -#define S5P_CMU_RESET_LCD1_LOWPWR 0x1174 -#define S5P_MODIMIF_MEM_LOWPWR 0x11C4 -#define S5P_PCIE_MEM_LOWPWR 0x11E0 -#define S5P_SATA_MEM_LOWPWR 0x11E4 -#define S5P_LCD1_LOWPWR 0x1394 - -/* Only for EXYNOS4x12 */ -#define S5P_ISP_ARM_LOWPWR 0x1050 -#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR 0x1054 -#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR 0x1058 -#define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR 0x1110 -#define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR 0x1114 -#define S5P_CMU_RESET_COREBLK_LOWPWR 0x111C -#define S5P_MPLLUSER_SYSCLK_LOWPWR 0x1130 -#define S5P_CMU_CLKSTOP_ISP_LOWPWR 0x1154 -#define S5P_CMU_RESET_ISP_LOWPWR 0x1174 -#define S5P_TOP_BUS_COREBLK_LOWPWR 0x1190 -#define S5P_TOP_RETENTION_COREBLK_LOWPWR 0x1194 -#define S5P_TOP_PWR_COREBLK_LOWPWR 0x1198 -#define S5P_OSCCLK_GATE_LOWPWR 0x11A4 -#define S5P_LOGIC_RESET_COREBLK_LOWPWR 0x11B0 -#define S5P_OSCCLK_GATE_COREBLK_LOWPWR 0x11B4 -#define S5P_HSI_MEM_LOWPWR 0x11C4 -#define S5P_ROTATOR_MEM_LOWPWR 0x11DC -#define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR 0x123C -#define S5P_PAD_ISOLATION_COREBLK_LOWPWR 0x1250 -#define S5P_GPIO_MODE_COREBLK_LOWPWR 0x1320 -#define S5P_TOP_ASB_RESET_LOWPWR 0x1344 -#define S5P_TOP_ASB_ISOLATION_LOWPWR 0x1348 -#define S5P_ISP_LOWPWR 0x1394 -#define S5P_DRAM_FREQ_DOWN_LOWPWR 0x13B0 -#define S5P_DDRPHY_DLLOFF_LOWPWR 0x13B4 -#define S5P_CMU_SYSCLK_ISP_LOWPWR 0x13B8 -#define S5P_CMU_SYSCLK_GPS_LOWPWR 0x13BC -#define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR 0x13C0 - -#define S5P_ARM_L2_0_OPTION 0x2608 -#define S5P_ARM_L2_1_OPTION 0x2628 -#define S5P_ONENAND_MEM_OPTION 0x2E08 -#define S5P_HSI_MEM_OPTION 0x2E28 -#define S5P_G2D_ACP_MEM_OPTION 0x2E48 -#define S5P_USBOTG_MEM_OPTION 0x2E68 -#define S5P_HSMMC_MEM_OPTION 0x2E88 -#define S5P_CSSYS_MEM_OPTION 0x2EA8 -#define S5P_SECSS_MEM_OPTION 0x2EC8 -#define S5P_ROTATOR_MEM_OPTION 0x2F48 - -/* Only for EXYNOS4412 */ -#define S5P_ARM_CORE2_LOWPWR 0x1020 -#define S5P_DIS_IRQ_CORE2 0x1024 -#define S5P_DIS_IRQ_CENTRAL2 0x1028 -#define S5P_ARM_CORE3_LOWPWR 0x1030 -#define S5P_DIS_IRQ_CORE3 0x1034 -#define S5P_DIS_IRQ_CENTRAL3 0x1038 - -/* Only for EXYNOS3XXX */ -#define EXYNOS3_ARM_CORE0_SYS_PWR_REG 0x1000 -#define EXYNOS3_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG 0x1004 -#define EXYNOS3_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG 0x1008 -#define EXYNOS3_ARM_CORE1_SYS_PWR_REG 0x1010 -#define EXYNOS3_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG 0x1014 -#define EXYNOS3_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG 0x1018 -#define EXYNOS3_ISP_ARM_SYS_PWR_REG 0x1050 -#define EXYNOS3_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG 0x1054 -#define EXYNOS3_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG 0x1058 -#define EXYNOS3_ARM_COMMON_SYS_PWR_REG 0x1080 -#define EXYNOS3_ARM_L2_SYS_PWR_REG 0x10C0 -#define EXYNOS3_CMU_ACLKSTOP_SYS_PWR_REG 0x1100 -#define EXYNOS3_CMU_SCLKSTOP_SYS_PWR_REG 0x1104 -#define EXYNOS3_CMU_RESET_SYS_PWR_REG 0x110C -#define EXYNOS3_CMU_ACLKSTOP_COREBLK_SYS_PWR_REG 0x1110 -#define EXYNOS3_CMU_SCLKSTOP_COREBLK_SYS_PWR_REG 0x1114 -#define EXYNOS3_CMU_RESET_COREBLK_SYS_PWR_REG 0x111C -#define EXYNOS3_APLL_SYSCLK_SYS_PWR_REG 0x1120 -#define EXYNOS3_MPLL_SYSCLK_SYS_PWR_REG 0x1124 -#define EXYNOS3_VPLL_SYSCLK_SYS_PWR_REG 0x1128 -#define EXYNOS3_EPLL_SYSCLK_SYS_PWR_REG 0x112C -#define EXYNOS3_MPLLUSER_SYSCLK_SYS_PWR_REG 0x1130 -#define EXYNOS3_BPLLUSER_SYSCLK_SYS_PWR_REG 0x1134 -#define EXYNOS3_EPLLUSER_SYSCLK_SYS_PWR_REG 0x1138 -#define EXYNOS3_CMU_CLKSTOP_CAM_SYS_PWR_REG 0x1140 -#define EXYNOS3_CMU_CLKSTOP_MFC_SYS_PWR_REG 0x1148 -#define EXYNOS3_CMU_CLKSTOP_G3D_SYS_PWR_REG 0x114C -#define EXYNOS3_CMU_CLKSTOP_LCD0_SYS_PWR_REG 0x1150 -#define EXYNOS3_CMU_CLKSTOP_ISP_SYS_PWR_REG 0x1154 -#define EXYNOS3_CMU_CLKSTOP_MAUDIO_SYS_PWR_REG 0x1158 -#define EXYNOS3_CMU_RESET_CAM_SYS_PWR_REG 0x1160 -#define EXYNOS3_CMU_RESET_MFC_SYS_PWR_REG 0x1168 -#define EXYNOS3_CMU_RESET_G3D_SYS_PWR_REG 0x116C -#define EXYNOS3_CMU_RESET_LCD0_SYS_PWR_REG 0x1170 -#define EXYNOS3_CMU_RESET_ISP_SYS_PWR_REG 0x1174 -#define EXYNOS3_CMU_RESET_MAUDIO_SYS_PWR_REG 0x1178 -#define EXYNOS3_TOP_BUS_SYS_PWR_REG 0x1180 -#define EXYNOS3_TOP_RETENTION_SYS_PWR_REG 0x1184 -#define EXYNOS3_TOP_PWR_SYS_PWR_REG 0x1188 -#define EXYNOS3_TOP_BUS_COREBLK_SYS_PWR_REG 0x1190 -#define EXYNOS3_TOP_RETENTION_COREBLK_SYS_PWR_REG 0x1194 -#define EXYNOS3_TOP_PWR_COREBLK_SYS_PWR_REG 0x1198 -#define EXYNOS3_LOGIC_RESET_SYS_PWR_REG 0x11A0 -#define EXYNOS3_OSCCLK_GATE_SYS_PWR_REG 0x11A4 -#define EXYNOS3_LOGIC_RESET_COREBLK_SYS_PWR_REG 0x11B0 -#define EXYNOS3_OSCCLK_GATE_COREBLK_SYS_PWR_REG 0x11B4 -#define EXYNOS3_PAD_RETENTION_DRAM_SYS_PWR_REG 0x1200 -#define EXYNOS3_PAD_RETENTION_MAUDIO_SYS_PWR_REG 0x1204 -#define EXYNOS3_PAD_RETENTION_SPI_SYS_PWR_REG 0x1208 -#define EXYNOS3_PAD_RETENTION_MMC2_SYS_PWR_REG 0x1218 -#define EXYNOS3_PAD_RETENTION_GPIO_SYS_PWR_REG 0x1220 -#define EXYNOS3_PAD_RETENTION_UART_SYS_PWR_REG 0x1224 -#define EXYNOS3_PAD_RETENTION_MMC0_SYS_PWR_REG 0x1228 -#define EXYNOS3_PAD_RETENTION_MMC1_SYS_PWR_REG 0x122C -#define EXYNOS3_PAD_RETENTION_EBIA_SYS_PWR_REG 0x1230 -#define EXYNOS3_PAD_RETENTION_EBIB_SYS_PWR_REG 0x1234 -#define EXYNOS3_PAD_RETENTION_JTAG_SYS_PWR_REG 0x1238 -#define EXYNOS3_PAD_ISOLATION_SYS_PWR_REG 0x1240 -#define EXYNOS3_PAD_ALV_SEL_SYS_PWR_REG 0x1260 -#define EXYNOS3_XUSBXTI_SYS_PWR_REG 0x1280 -#define EXYNOS3_XXTI_SYS_PWR_REG 0x1284 -#define EXYNOS3_EXT_REGULATOR_SYS_PWR_REG 0x12C0 -#define EXYNOS3_EXT_REGULATOR_COREBLK_SYS_PWR_REG 0x12C4 -#define EXYNOS3_GPIO_MODE_SYS_PWR_REG 0x1300 -#define EXYNOS3_GPIO_MODE_MAUDIO_SYS_PWR_REG 0x1340 -#define EXYNOS3_TOP_ASB_RESET_SYS_PWR_REG 0x1344 -#define EXYNOS3_TOP_ASB_ISOLATION_SYS_PWR_REG 0x1348 -#define EXYNOS3_TOP_ASB_RESET_COREBLK_SYS_PWR_REG 0x1350 -#define EXYNOS3_TOP_ASB_ISOLATION_COREBLK_SYS_PWR_REG 0x1354 -#define EXYNOS3_CAM_SYS_PWR_REG 0x1380 -#define EXYNOS3_MFC_SYS_PWR_REG 0x1388 -#define EXYNOS3_G3D_SYS_PWR_REG 0x138C -#define EXYNOS3_LCD0_SYS_PWR_REG 0x1390 -#define EXYNOS3_ISP_SYS_PWR_REG 0x1394 -#define EXYNOS3_MAUDIO_SYS_PWR_REG 0x1398 -#define EXYNOS3_DRAM_FREQ_DOWN_SYS_PWR_REG 0x13B0 -#define EXYNOS3_DDRPHY_DLLOFF_SYS_PWR_REG 0x13B4 -#define EXYNOS3_CMU_SYSCLK_ISP_SYS_PWR_REG 0x13B8 -#define EXYNOS3_LPDDR_PHY_DLL_LOCK_SYS_PWR_REG 0x13C0 -#define EXYNOS3_BPLL_SYSCLK_SYS_PWR_REG 0x13C4 -#define EXYNOS3_UPLL_SYSCLK_SYS_PWR_REG 0x13C8 - -#define EXYNOS3_ARM_CORE0_OPTION 0x2008 -#define EXYNOS3_ARM_CORE_OPTION(_nr) \ - (EXYNOS3_ARM_CORE0_OPTION + ((_nr) * 0x80)) - -#define EXYNOS3_ARM_COMMON_OPTION 0x2408 -#define EXYNOS3_ARM_L2_OPTION 0x2608 -#define EXYNOS3_TOP_PWR_OPTION 0x2C48 -#define EXYNOS3_CORE_TOP_PWR_OPTION 0x2CA8 -#define EXYNOS3_XUSBXTI_DURATION 0x341C -#define EXYNOS3_XXTI_DURATION 0x343C -#define EXYNOS3_EXT_REGULATOR_DURATION 0x361C -#define EXYNOS3_EXT_REGULATOR_COREBLK_DURATION 0x363C -#define XUSBXTI_DURATION 0x00000BB8 -#define XXTI_DURATION XUSBXTI_DURATION -#define EXT_REGULATOR_DURATION 0x00001D4C -#define EXT_REGULATOR_COREBLK_DURATION EXT_REGULATOR_DURATION - -/* for XXX_OPTION */ -#define EXYNOS3_OPTION_USE_SC_COUNTER (1 << 0) -#define EXYNOS3_OPTION_USE_SC_FEEDBACK (1 << 1) -#define EXYNOS3_OPTION_SKIP_DEACTIVATE_ACEACP_IN_PWDN (1 << 7) - -/* For EXYNOS5 */ - -#define EXYNOS5_AUTO_WDTRESET_DISABLE 0x0408 -#define EXYNOS5_MASK_WDTRESET_REQUEST 0x040C - -#define EXYNOS5_USE_RETENTION BIT(4) -#define EXYNOS5_SYS_WDTRESET (1 << 20) - -#define EXYNOS5_ARM_CORE0_SYS_PWR_REG 0x1000 -#define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG 0x1004 -#define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG 0x1008 -#define EXYNOS5_ARM_CORE1_SYS_PWR_REG 0x1010 -#define EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG 0x1014 -#define EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG 0x1018 -#define EXYNOS5_FSYS_ARM_SYS_PWR_REG 0x1040 -#define EXYNOS5_DIS_IRQ_FSYS_ARM_CENTRAL_SYS_PWR_REG 0x1048 -#define EXYNOS5_ISP_ARM_SYS_PWR_REG 0x1050 -#define EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG 0x1054 -#define EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG 0x1058 -#define EXYNOS5_ARM_COMMON_SYS_PWR_REG 0x1080 -#define EXYNOS5_ARM_L2_SYS_PWR_REG 0x10C0 -#define EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG 0x1100 -#define EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG 0x1104 -#define EXYNOS5_CMU_RESET_SYS_PWR_REG 0x110C -#define EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG 0x1120 -#define EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG 0x1124 -#define EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG 0x112C -#define EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG 0x1130 -#define EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG 0x1134 -#define EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG 0x1138 -#define EXYNOS5_APLL_SYSCLK_SYS_PWR_REG 0x1140 -#define EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG 0x1144 -#define EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG 0x1148 -#define EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG 0x114C -#define EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG 0x1150 -#define EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG 0x1154 -#define EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG 0x1164 -#define EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG 0x1170 -#define EXYNOS5_TOP_BUS_SYS_PWR_REG 0x1180 -#define EXYNOS5_TOP_RETENTION_SYS_PWR_REG 0x1184 -#define EXYNOS5_TOP_PWR_SYS_PWR_REG 0x1188 -#define EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG 0x1190 -#define EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG 0x1194 -#define EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG 0x1198 -#define EXYNOS5_LOGIC_RESET_SYS_PWR_REG 0x11A0 -#define EXYNOS5_OSCCLK_GATE_SYS_PWR_REG 0x11A4 -#define EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG 0x11B0 -#define EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG 0x11B4 -#define EXYNOS5_USBOTG_MEM_SYS_PWR_REG 0x11C0 -#define EXYNOS5_G2D_MEM_SYS_PWR_REG 0x11C8 -#define EXYNOS5_USBDRD_MEM_SYS_PWR_REG 0x11CC -#define EXYNOS5_SDMMC_MEM_SYS_PWR_REG 0x11D0 -#define EXYNOS5_CSSYS_MEM_SYS_PWR_REG 0x11D4 -#define EXYNOS5_SECSS_MEM_SYS_PWR_REG 0x11D8 -#define EXYNOS5_ROTATOR_MEM_SYS_PWR_REG 0x11DC -#define EXYNOS5_INTRAM_MEM_SYS_PWR_REG 0x11E0 -#define EXYNOS5_INTROM_MEM_SYS_PWR_REG 0x11E4 -#define EXYNOS5_JPEG_MEM_SYS_PWR_REG 0x11E8 -#define EXYNOS5_HSI_MEM_SYS_PWR_REG 0x11EC -#define EXYNOS5_MCUIOP_MEM_SYS_PWR_REG 0x11F4 -#define EXYNOS5_SATA_MEM_SYS_PWR_REG 0x11FC -#define EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG 0x1200 -#define EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG 0x1204 -#define EXYNOS5_PAD_RETENTION_EFNAND_SYS_PWR_REG 0x1208 -#define EXYNOS5_PAD_RETENTION_GPIO_SYS_PWR_REG 0x1220 -#define EXYNOS5_PAD_RETENTION_UART_SYS_PWR_REG 0x1224 -#define EXYNOS5_PAD_RETENTION_MMCA_SYS_PWR_REG 0x1228 -#define EXYNOS5_PAD_RETENTION_MMCB_SYS_PWR_REG 0x122C -#define EXYNOS5_PAD_RETENTION_EBIA_SYS_PWR_REG 0x1230 -#define EXYNOS5_PAD_RETENTION_EBIB_SYS_PWR_REG 0x1234 -#define EXYNOS5_PAD_RETENTION_SPI_SYS_PWR_REG 0x1238 -#define EXYNOS5_PAD_RETENTION_GPIO_SYSMEM_SYS_PWR_REG 0x123C -#define EXYNOS5_PAD_ISOLATION_SYS_PWR_REG 0x1240 -#define EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG 0x1250 -#define EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG 0x1260 -#define EXYNOS5_XUSBXTI_SYS_PWR_REG 0x1280 -#define EXYNOS5_XXTI_SYS_PWR_REG 0x1284 -#define EXYNOS5_EXT_REGULATOR_SYS_PWR_REG 0x12C0 -#define EXYNOS5_GPIO_MODE_SYS_PWR_REG 0x1300 -#define EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG 0x1320 -#define EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG 0x1340 -#define EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG 0x1344 -#define EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG 0x1348 -#define EXYNOS5_GSCL_SYS_PWR_REG 0x1400 -#define EXYNOS5_ISP_SYS_PWR_REG 0x1404 -#define EXYNOS5_MFC_SYS_PWR_REG 0x1408 -#define EXYNOS5_G3D_SYS_PWR_REG 0x140C -#define EXYNOS5_DISP1_SYS_PWR_REG 0x1414 -#define EXYNOS5_MAU_SYS_PWR_REG 0x1418 -#define EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG 0x1480 -#define EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG 0x1484 -#define EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG 0x1488 -#define EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG 0x148C -#define EXYNOS5_CMU_CLKSTOP_DISP1_SYS_PWR_REG 0x1494 -#define EXYNOS5_CMU_CLKSTOP_MAU_SYS_PWR_REG 0x1498 -#define EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG 0x14C0 -#define EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG 0x14C4 -#define EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG 0x14C8 -#define EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG 0x14CC -#define EXYNOS5_CMU_SYSCLK_DISP1_SYS_PWR_REG 0x14D4 -#define EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG 0x14D8 -#define EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG 0x1580 -#define EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG 0x1584 -#define EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG 0x1588 -#define EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG 0x158C -#define EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG 0x1594 -#define EXYNOS5_CMU_RESET_MAU_SYS_PWR_REG 0x1598 - -#define EXYNOS5_ARM_CORE0_OPTION 0x2008 -#define EXYNOS5_ARM_CORE1_OPTION 0x2088 -#define EXYNOS5_FSYS_ARM_OPTION 0x2208 -#define EXYNOS5_ISP_ARM_OPTION 0x2288 -#define EXYNOS5_ARM_COMMON_OPTION 0x2408 -#define EXYNOS5_ARM_L2_OPTION 0x2608 -#define EXYNOS5_TOP_PWR_OPTION 0x2C48 -#define EXYNOS5_TOP_PWR_SYSMEM_OPTION 0x2CC8 -#define EXYNOS5_JPEG_MEM_OPTION 0x2F48 -#define EXYNOS5_GSCL_OPTION 0x4008 -#define EXYNOS5_ISP_OPTION 0x4028 -#define EXYNOS5_MFC_OPTION 0x4048 -#define EXYNOS5_G3D_OPTION 0x4068 -#define EXYNOS5_DISP1_OPTION 0x40A8 -#define EXYNOS5_MAU_OPTION 0x40C8 - -#define EXYNOS5_USE_SC_FEEDBACK (1 << 1) -#define EXYNOS5_USE_SC_COUNTER (1 << 0) - -#define EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN (1 << 7) - -#define EXYNOS5_OPTION_USE_STANDBYWFE (1 << 24) -#define EXYNOS5_OPTION_USE_STANDBYWFI (1 << 16) - -#define EXYNOS5_OPTION_USE_RETENTION (1 << 4) - -#define EXYNOS5420_SWRESET_KFC_SEL 0x3 - -/* Only for EXYNOS5420 */ -#define EXYNOS5420_ISP_ARM_OPTION 0x2488 -#define EXYNOS5420_L2RSTDISABLE_VALUE BIT(3) - -#define EXYNOS5420_LPI_MASK 0x0004 -#define EXYNOS5420_LPI_MASK1 0x0008 -#define EXYNOS5420_UFS BIT(8) -#define EXYNOS5420_ATB_KFC BIT(13) -#define EXYNOS5420_ATB_ISP_ARM BIT(19) -#define EXYNOS5420_EMULATION BIT(31) -#define ATB_ISP_ARM BIT(12) -#define ATB_KFC BIT(13) -#define ATB_NOC BIT(14) - -#define EXYNOS5420_ARM_INTR_SPREAD_ENABLE 0x0100 -#define EXYNOS5420_ARM_INTR_SPREAD_USE_STANDBYWFI 0x0104 -#define EXYNOS5420_UP_SCHEDULER 0x0120 -#define SPREAD_ENABLE 0xF -#define SPREAD_USE_STANDWFI 0xF - -#define EXYNOS5420_KFC_CORE_RESET0 BIT(8) -#define EXYNOS5420_KFC_ETM_RESET0 BIT(20) - -#define EXYNOS5420_KFC_CORE_RESET(_nr) \ - ((EXYNOS5420_KFC_CORE_RESET0 | EXYNOS5420_KFC_ETM_RESET0) << (_nr)) - -#define EXYNOS5420_BB_CON1 0x0784 -#define EXYNOS5420_BB_SEL_EN BIT(31) -#define EXYNOS5420_BB_PMOS_EN BIT(7) -#define EXYNOS5420_BB_1300X 0XF - -#define EXYNOS5420_ARM_CORE2_SYS_PWR_REG 0x1020 -#define EXYNOS5420_DIS_IRQ_ARM_CORE2_LOCAL_SYS_PWR_REG 0x1024 -#define EXYNOS5420_DIS_IRQ_ARM_CORE2_CENTRAL_SYS_PWR_REG 0x1028 -#define EXYNOS5420_ARM_CORE3_SYS_PWR_REG 0x1030 -#define EXYNOS5420_DIS_IRQ_ARM_CORE3_LOCAL_SYS_PWR_REG 0x1034 -#define EXYNOS5420_DIS_IRQ_ARM_CORE3_CENTRAL_SYS_PWR_REG 0x1038 -#define EXYNOS5420_KFC_CORE0_SYS_PWR_REG 0x1040 -#define EXYNOS5420_DIS_IRQ_KFC_CORE0_LOCAL_SYS_PWR_REG 0x1044 -#define EXYNOS5420_DIS_IRQ_KFC_CORE0_CENTRAL_SYS_PWR_REG 0x1048 -#define EXYNOS5420_KFC_CORE1_SYS_PWR_REG 0x1050 -#define EXYNOS5420_DIS_IRQ_KFC_CORE1_LOCAL_SYS_PWR_REG 0x1054 -#define EXYNOS5420_DIS_IRQ_KFC_CORE1_CENTRAL_SYS_PWR_REG 0x1058 -#define EXYNOS5420_KFC_CORE2_SYS_PWR_REG 0x1060 -#define EXYNOS5420_DIS_IRQ_KFC_CORE2_LOCAL_SYS_PWR_REG 0x1064 -#define EXYNOS5420_DIS_IRQ_KFC_CORE2_CENTRAL_SYS_PWR_REG 0x1068 -#define EXYNOS5420_KFC_CORE3_SYS_PWR_REG 0x1070 -#define EXYNOS5420_DIS_IRQ_KFC_CORE3_LOCAL_SYS_PWR_REG 0x1074 -#define EXYNOS5420_DIS_IRQ_KFC_CORE3_CENTRAL_SYS_PWR_REG 0x1078 -#define EXYNOS5420_ISP_ARM_SYS_PWR_REG 0x1090 -#define EXYNOS5420_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG 0x1094 -#define EXYNOS5420_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG 0x1098 -#define EXYNOS5420_ARM_COMMON_SYS_PWR_REG 0x10A0 -#define EXYNOS5420_KFC_COMMON_SYS_PWR_REG 0x10B0 -#define EXYNOS5420_KFC_L2_SYS_PWR_REG 0x10D0 -#define EXYNOS5420_DPLL_SYSCLK_SYS_PWR_REG 0x1158 -#define EXYNOS5420_IPLL_SYSCLK_SYS_PWR_REG 0x115C -#define EXYNOS5420_KPLL_SYSCLK_SYS_PWR_REG 0x1160 -#define EXYNOS5420_RPLL_SYSCLK_SYS_PWR_REG 0x1174 -#define EXYNOS5420_SPLL_SYSCLK_SYS_PWR_REG 0x1178 -#define EXYNOS5420_INTRAM_MEM_SYS_PWR_REG 0x11B8 -#define EXYNOS5420_INTROM_MEM_SYS_PWR_REG 0x11BC -#define EXYNOS5420_ONENANDXL_MEM_SYS_PWR 0x11C0 -#define EXYNOS5420_USBDEV_MEM_SYS_PWR 0x11CC -#define EXYNOS5420_USBDEV1_MEM_SYS_PWR 0x11D0 -#define EXYNOS5420_SDMMC_MEM_SYS_PWR 0x11D4 -#define EXYNOS5420_CSSYS_MEM_SYS_PWR 0x11D8 -#define EXYNOS5420_SECSS_MEM_SYS_PWR 0x11DC -#define EXYNOS5420_ROTATOR_MEM_SYS_PWR 0x11E0 -#define EXYNOS5420_INTRAM_MEM_SYS_PWR 0x11E4 -#define EXYNOS5420_INTROM_MEM_SYS_PWR 0x11E8 -#define EXYNOS5420_PAD_RETENTION_JTAG_SYS_PWR_REG 0x1208 -#define EXYNOS5420_PAD_RETENTION_DRAM_SYS_PWR_REG 0x1210 -#define EXYNOS5420_PAD_RETENTION_UART_SYS_PWR_REG 0x1214 -#define EXYNOS5420_PAD_RETENTION_MMC0_SYS_PWR_REG 0x1218 -#define EXYNOS5420_PAD_RETENTION_MMC1_SYS_PWR_REG 0x121C -#define EXYNOS5420_PAD_RETENTION_MMC2_SYS_PWR_REG 0x1220 -#define EXYNOS5420_PAD_RETENTION_HSI_SYS_PWR_REG 0x1224 -#define EXYNOS5420_PAD_RETENTION_EBIA_SYS_PWR_REG 0x1228 -#define EXYNOS5420_PAD_RETENTION_EBIB_SYS_PWR_REG 0x122C -#define EXYNOS5420_PAD_RETENTION_SPI_SYS_PWR_REG 0x1230 -#define EXYNOS5420_PAD_RETENTION_DRAM_COREBLK_SYS_PWR_REG 0x1234 -#define EXYNOS5420_DISP1_SYS_PWR_REG 0x1410 -#define EXYNOS5420_MAU_SYS_PWR_REG 0x1414 -#define EXYNOS5420_G2D_SYS_PWR_REG 0x1418 -#define EXYNOS5420_MSC_SYS_PWR_REG 0x141C -#define EXYNOS5420_FSYS_SYS_PWR_REG 0x1420 -#define EXYNOS5420_FSYS2_SYS_PWR_REG 0x1424 -#define EXYNOS5420_PSGEN_SYS_PWR_REG 0x1428 -#define EXYNOS5420_PERIC_SYS_PWR_REG 0x142C -#define EXYNOS5420_WCORE_SYS_PWR_REG 0x1430 -#define EXYNOS5420_CMU_CLKSTOP_DISP1_SYS_PWR_REG 0x1490 -#define EXYNOS5420_CMU_CLKSTOP_MAU_SYS_PWR_REG 0x1494 -#define EXYNOS5420_CMU_CLKSTOP_G2D_SYS_PWR_REG 0x1498 -#define EXYNOS5420_CMU_CLKSTOP_MSC_SYS_PWR_REG 0x149C -#define EXYNOS5420_CMU_CLKSTOP_FSYS_SYS_PWR_REG 0x14A0 -#define EXYNOS5420_CMU_CLKSTOP_FSYS2_SYS_PWR_REG 0x14A4 -#define EXYNOS5420_CMU_CLKSTOP_PSGEN_SYS_PWR_REG 0x14A8 -#define EXYNOS5420_CMU_CLKSTOP_PERIC_SYS_PWR_REG 0x14AC -#define EXYNOS5420_CMU_CLKSTOP_WCORE_SYS_PWR_REG 0x14B0 -#define EXYNOS5420_CMU_SYSCLK_TOPPWR_SYS_PWR_REG 0x14BC -#define EXYNOS5420_CMU_SYSCLK_DISP1_SYS_PWR_REG 0x14D0 -#define EXYNOS5420_CMU_SYSCLK_MAU_SYS_PWR_REG 0x14D4 -#define EXYNOS5420_CMU_SYSCLK_G2D_SYS_PWR_REG 0x14D8 -#define EXYNOS5420_CMU_SYSCLK_MSC_SYS_PWR_REG 0x14DC -#define EXYNOS5420_CMU_SYSCLK_FSYS_SYS_PWR_REG 0x14E0 -#define EXYNOS5420_CMU_SYSCLK_FSYS2_SYS_PWR_REG 0x14E4 -#define EXYNOS5420_CMU_SYSCLK_PSGEN_SYS_PWR_REG 0x14E8 -#define EXYNOS5420_CMU_SYSCLK_PERIC_SYS_PWR_REG 0x14EC -#define EXYNOS5420_CMU_SYSCLK_WCORE_SYS_PWR_REG 0x14F0 -#define EXYNOS5420_CMU_SYSCLK_SYSMEM_TOPPWR_SYS_PWR_REG 0x14F4 -#define EXYNOS5420_CMU_RESET_FSYS2_SYS_PWR_REG 0x1570 -#define EXYNOS5420_CMU_RESET_PSGEN_SYS_PWR_REG 0x1574 -#define EXYNOS5420_CMU_RESET_PERIC_SYS_PWR_REG 0x1578 -#define EXYNOS5420_CMU_RESET_WCORE_SYS_PWR_REG 0x157C -#define EXYNOS5420_CMU_RESET_DISP1_SYS_PWR_REG 0x1590 -#define EXYNOS5420_CMU_RESET_MAU_SYS_PWR_REG 0x1594 -#define EXYNOS5420_CMU_RESET_G2D_SYS_PWR_REG 0x1598 -#define EXYNOS5420_CMU_RESET_MSC_SYS_PWR_REG 0x159C -#define EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG 0x15A0 -#define EXYNOS5420_SFR_AXI_CGDIS1 0x15E4 -#define EXYNOS_ARM_CORE2_CONFIGURATION 0x2100 -#define EXYNOS5420_ARM_CORE2_OPTION 0x2108 -#define EXYNOS_ARM_CORE3_CONFIGURATION 0x2180 -#define EXYNOS5420_ARM_CORE3_OPTION 0x2188 -#define EXYNOS5420_ARM_COMMON_STATUS 0x2504 -#define EXYNOS5420_ARM_COMMON_OPTION 0x2508 -#define EXYNOS5420_KFC_COMMON_STATUS 0x2584 -#define EXYNOS5420_KFC_COMMON_OPTION 0x2588 -#define EXYNOS5420_LOGIC_RESET_DURATION3 0x2D1C - -#define EXYNOS5420_PAD_RET_GPIO_OPTION 0x30C8 -#define EXYNOS5420_PAD_RET_UART_OPTION 0x30E8 -#define EXYNOS5420_PAD_RET_MMCA_OPTION 0x3108 -#define EXYNOS5420_PAD_RET_MMCB_OPTION 0x3128 -#define EXYNOS5420_PAD_RET_MMCC_OPTION 0x3148 -#define EXYNOS5420_PAD_RET_HSI_OPTION 0x3168 -#define EXYNOS5420_PAD_RET_SPI_OPTION 0x31C8 -#define EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION 0x31E8 -#define EXYNOS_PAD_RET_DRAM_OPTION 0x3008 -#define EXYNOS_PAD_RET_MAUDIO_OPTION 0x3028 -#define EXYNOS_PAD_RET_JTAG_OPTION 0x3048 -#define EXYNOS_PAD_RET_GPIO_OPTION 0x3108 -#define EXYNOS_PAD_RET_UART_OPTION 0x3128 -#define EXYNOS_PAD_RET_MMCA_OPTION 0x3148 -#define EXYNOS_PAD_RET_MMCB_OPTION 0x3168 -#define EXYNOS_PAD_RET_EBIA_OPTION 0x3188 -#define EXYNOS_PAD_RET_EBIB_OPTION 0x31A8 - -#define EXYNOS_PS_HOLD_CONTROL 0x330C - -/* For SYS_PWR_REG */ -#define EXYNOS_SYS_PWR_CFG BIT(0) - -#define EXYNOS5420_MFC_CONFIGURATION 0x4060 -#define EXYNOS5420_MFC_STATUS 0x4064 -#define EXYNOS5420_MFC_OPTION 0x4068 -#define EXYNOS5420_G3D_CONFIGURATION 0x4080 -#define EXYNOS5420_G3D_STATUS 0x4084 -#define EXYNOS5420_G3D_OPTION 0x4088 -#define EXYNOS5420_DISP0_CONFIGURATION 0x40A0 -#define EXYNOS5420_DISP0_STATUS 0x40A4 -#define EXYNOS5420_DISP0_OPTION 0x40A8 -#define EXYNOS5420_DISP1_CONFIGURATION 0x40C0 -#define EXYNOS5420_DISP1_STATUS 0x40C4 -#define EXYNOS5420_DISP1_OPTION 0x40C8 -#define EXYNOS5420_MAU_CONFIGURATION 0x40E0 -#define EXYNOS5420_MAU_STATUS 0x40E4 -#define EXYNOS5420_MAU_OPTION 0x40E8 -#define EXYNOS5420_FSYS2_OPTION 0x4168 -#define EXYNOS5420_PSGEN_OPTION 0x4188 - -/* For EXYNOS_CENTRAL_SEQ_OPTION */ -#define EXYNOS5_USE_STANDBYWFI_ARM_CORE0 BIT(16) -#define EXYNOS5_USE_STANDBYWFI_ARM_CORE1 BUT(17) -#define EXYNOS5_USE_STANDBYWFE_ARM_CORE0 BIT(24) -#define EXYNOS5_USE_STANDBYWFE_ARM_CORE1 BIT(25) - -#define EXYNOS5420_ARM_USE_STANDBY_WFI0 BIT(4) -#define EXYNOS5420_ARM_USE_STANDBY_WFI1 BIT(5) -#define EXYNOS5420_ARM_USE_STANDBY_WFI2 BIT(6) -#define EXYNOS5420_ARM_USE_STANDBY_WFI3 BIT(7) -#define EXYNOS5420_KFC_USE_STANDBY_WFI0 BIT(8) -#define EXYNOS5420_KFC_USE_STANDBY_WFI1 BIT(9) -#define EXYNOS5420_KFC_USE_STANDBY_WFI2 BIT(10) -#define EXYNOS5420_KFC_USE_STANDBY_WFI3 BIT(11) -#define EXYNOS5420_ARM_USE_STANDBY_WFE0 BIT(16) -#define EXYNOS5420_ARM_USE_STANDBY_WFE1 BIT(17) -#define EXYNOS5420_ARM_USE_STANDBY_WFE2 BIT(18) -#define EXYNOS5420_ARM_USE_STANDBY_WFE3 BIT(19) -#define EXYNOS5420_KFC_USE_STANDBY_WFE0 BIT(20) -#define EXYNOS5420_KFC_USE_STANDBY_WFE1 BIT(21) -#define EXYNOS5420_KFC_USE_STANDBY_WFE2 BIT(22) -#define EXYNOS5420_KFC_USE_STANDBY_WFE3 BIT(23) - -#define DUR_WAIT_RESET 0xF - -#define EXYNOS5420_USE_STANDBY_WFI_ALL (EXYNOS5420_ARM_USE_STANDBY_WFI0 \ - | EXYNOS5420_ARM_USE_STANDBY_WFI1 \ - | EXYNOS5420_ARM_USE_STANDBY_WFI2 \ - | EXYNOS5420_ARM_USE_STANDBY_WFI3 \ - | EXYNOS5420_KFC_USE_STANDBY_WFI0 \ - | EXYNOS5420_KFC_USE_STANDBY_WFI1 \ - | EXYNOS5420_KFC_USE_STANDBY_WFI2 \ - | EXYNOS5420_KFC_USE_STANDBY_WFI3) - -#endif /* __ASM_ARCH_REGS_PMU_H */ diff --git a/arch/arm/mach-exynos/s5p-dev-mfc.c b/arch/arm/mach-exynos/s5p-dev-mfc.c index 0b04b6b0fa30..8ef1f3ee4e98 100644 --- a/arch/arm/mach-exynos/s5p-dev-mfc.c +++ b/arch/arm/mach-exynos/s5p-dev-mfc.c @@ -9,7 +9,6 @@ */ #include <linux/kernel.h> -#include <linux/interrupt.h> #include <linux/platform_device.h> #include <linux/dma-mapping.h> #include <linux/memblock.h> diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c index c169cc3049aa..fee2b003e662 100644 --- a/arch/arm/mach-exynos/suspend.c +++ b/arch/arm/mach-exynos/suspend.c @@ -24,6 +24,8 @@ #include <linux/of_address.h> #include <linux/err.h> #include <linux/regulator/machine.h> +#include <linux/soc/samsung/exynos-pmu.h> +#include <linux/soc/samsung/exynos-regs-pmu.h> #include <asm/cacheflush.h> #include <asm/hardware/cache-l2x0.h> @@ -35,8 +37,6 @@ #include <plat/pm-common.h> #include "common.h" -#include "exynos-pmu.h" -#include "regs-pmu.h" #include "regs-srom.h" #define REG_TABLE_END (-1U) |