diff options
| author | Anson Huang <b20788@freescale.com> | 2014-06-23 16:42:43 +0800 |
|---|---|---|
| committer | Shawn Guo <shawn.guo@freescale.com> | 2014-07-18 16:11:30 +0800 |
| commit | dfea953ae221111c14d2fcfebad7b1973a0f49bd (patch) | |
| tree | 08b6f64b00c0b058a8c05017c8a6c233d8985131 /arch/arm/mach-imx/common.h | |
| parent | d2d2e54d6655d78e619bfa22e186d82ca5d6e880 (diff) | |
ARM: imx: mem bit must be cleared before entering DSM mode
According to hardware design, mem bit must be clear before
entering DSM mode, as ARM core will be power gated in DSM mode.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Diffstat (limited to 'arch/arm/mach-imx/common.h')
| -rw-r--r-- | arch/arm/mach-imx/common.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 50ee9c23974c..13a6e1f8e11e 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -116,7 +116,7 @@ void imx_anatop_init(void); void imx_anatop_pre_suspend(void); void imx_anatop_post_resume(void); int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); -void imx6q_set_int_mem_clk_lpm(void); +void imx6q_set_int_mem_clk_lpm(bool enable); void imx6sl_set_wait_clk(bool enter); void imx_cpu_die(unsigned int cpu); |