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authorLucas De Marchi <lucas.demarchi@profusion.mobi>2011-03-30 22:57:33 -0300
committerLucas De Marchi <lucas.demarchi@profusion.mobi>2011-03-31 11:26:23 -0300
commit25985edcedea6396277003854657b5f3cb31a628 (patch)
treef026e810210a2ee7290caeb737c23cb6472b7c38 /arch/arm/mach-lpc32xx
parent6aba74f2791287ec407e0f92487a725a25908067 (diff)
Fix common misspellings
Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
Diffstat (limited to 'arch/arm/mach-lpc32xx')
-rw-r--r--arch/arm/mach-lpc32xx/pm.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-lpc32xx/pm.c b/arch/arm/mach-lpc32xx/pm.c
index e76d41bb7056..b9c80597b7bf 100644
--- a/arch/arm/mach-lpc32xx/pm.c
+++ b/arch/arm/mach-lpc32xx/pm.c
@@ -41,7 +41,7 @@
* DRAM clocking and refresh are slightly different for systems with DDR
* DRAM or regular SDRAM devices. If SDRAM is used in the system, the
* SDRAM will still be accessible in direct-run mode. In DDR based systems,
- * a transistion to direct-run mode will stop all DDR accesses (no clocks).
+ * a transition to direct-run mode will stop all DDR accesses (no clocks).
* Because of this, the code to switch power modes and the code to enter
* and exit DRAM self-refresh modes must not be executed in DRAM. A small
* section of IRAM is used instead for this.