diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2023-02-20 15:28:57 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2023-02-20 15:28:57 -0800 |
| commit | ff0c7e18629b8bd64681313a88ce55e182c9fee6 (patch) | |
| tree | 70efa650f6458514e1d7e5e3f72cc8f87fc5cf2c /arch/arm/mach-mmp | |
| parent | 5b0ed5964928b0aaf0d644c17c886c7f5ea4bb3f (diff) | |
| parent | a1f925bc4fa899b3c0f2dcbc432d572c36e74e71 (diff) | |
Merge tag 'arm-boardfile-remove-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC boardfile updates from Arnd Bergmann
"Unused boardfile removal for 6.3
This is a follow-up to the deprecation of most of the old-style board
files that was merged in linux-6.0, removing them for good.
This branch is almost exclusively dead code removal based on those
annotations. Some device driver removals went through separate
subsystem trees, but the majority is in the same branch, in order to
better handle dependencies between the patches and avoid breaking
bisection.
Unfortunately that leads to merge conflicts against other changes in
the subsystem trees, but they should all be trivial to resolve by
removing the files.
See commit 7d0d3fa7339e ("Merge tag 'arm-boardfiles-6.0' of
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc") for the
description of which machines were marked unused and are now removed.
The only removals that got postponed are Terastation WXL (mv78xx0) and
Jornada720 (StrongARM1100), which turned out to still have potential
users"
* tag 'arm-boardfile-remove-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (91 commits)
mmc: omap: drop TPS65010 dependency
ARM: pxa: restore mfp-pxa320.h
usb: ohci-omap: avoid unused-variable warning
ARM: debug: remove references in DEBUG_UART_8250_SHIFT to removed configs
ARM: s3c: remove obsolete s3c-cpu-freq header
MAINTAINERS: adjust SAMSUNG SOC CLOCK DRIVERS after s3c24xx support removal
MAINTAINERS: update file entries after arm multi-platform rework and mach-pxa removal
ARM: remove CONFIG_UNUSED_BOARD_FILES
mfd: remove htc-pasic3 driver
w1: remove ds1wm driver
usb: remove ohci-tmio driver
fbdev: remove w100fb driver
fbdev: remove tmiofb driver
mmc: remove tmio_mmc driver
mfd: remove ucb1400 support
mfd: remove toshiba tmio drivers
rtc: remove v3020 driver
power: remove pda_power supply driver
ASoC: pxa: remove unused board support
pcmcia: remove unused pxa/sa1100 drivers
...
Diffstat (limited to 'arch/arm/mach-mmp')
37 files changed, 3 insertions, 5247 deletions
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig index d71417d57961..85b0d9ddb7d8 100644 --- a/arch/arm/mach-mmp/Kconfig +++ b/arch/arm/mach-mmp/Kconfig @@ -13,99 +13,6 @@ if ARCH_MMP menu "Marvell PXA168/910/MMP2 Implementations" -if ATAGS - -config MACH_ASPENITE - bool "Marvell's PXA168 Aspenite Development Board" - depends on ARCH_MULTI_V5 - depends on UNUSED_BOARD_FILES - select CPU_PXA168 - help - Say 'Y' here if you want to support the Marvell PXA168-based - Aspenite Development Board. - -config MACH_ZYLONITE2 - bool "Marvell's PXA168 Zylonite2 Development Board" - depends on ARCH_MULTI_V5 - depends on UNUSED_BOARD_FILES - select CPU_PXA168 - help - Say 'Y' here if you want to support the Marvell PXA168-based - Zylonite2 Development Board. - -config MACH_AVENGERS_LITE - bool "Marvell's PXA168 Avengers Lite Development Board" - depends on ARCH_MULTI_V5 - depends on UNUSED_BOARD_FILES - select CPU_PXA168 - help - Say 'Y' here if you want to support the Marvell PXA168-based - Avengers Lite Development Board. - -config MACH_TTC_DKB - bool "Marvell's PXA910 TavorEVB/TTC_DKB Development Board" - depends on ARCH_MULTI_V5 - depends on UNUSED_BOARD_FILES - select CPU_PXA910 - help - Say 'Y' here if you want to support the Marvell PXA910-based - TTC_DKB Development Board. - -config MACH_BROWNSTONE - bool "Marvell's Brownstone Development Platform" - depends on ARCH_MULTI_V7 - depends on UNUSED_BOARD_FILES - select CPU_MMP2 - help - Say 'Y' here if you want to support the Marvell MMP2-based - Brown Development Platform. - MMP2-based board can't be co-existed with PXA168-based & - PXA910-based development board. Since MMP2 is compatible to - ARMv7 architecture. - -config MACH_FLINT - bool "Marvell's Flint Development Platform" - depends on ARCH_MULTI_V7 - depends on UNUSED_BOARD_FILES - select CPU_MMP2 - help - Say 'Y' here if you want to support the Marvell MMP2-based - Flint Development Platform. - MMP2-based board can't be co-existed with PXA168-based & - PXA910-based development board. Since MMP2 is compatible to - ARMv7 architecture. - -config MACH_MARVELL_JASPER - bool "Marvell's Jasper Development Platform" - depends on ARCH_MULTI_V7 - depends on UNUSED_BOARD_FILES - select CPU_MMP2 - help - Say 'Y' here if you want to support the Marvell MMP2-base - Jasper Development Platform. - MMP2-based board can't be co-existed with PXA168-based & - PXA910-based development board. Since MMP2 is compatible to - ARMv7 architecture. - -config MACH_TETON_BGA - bool "Marvell's PXA168 Teton BGA Development Board" - depends on ARCH_MULTI_V5 - depends on UNUSED_BOARD_FILES - select CPU_PXA168 - help - Say 'Y' here if you want to support the Marvell PXA168-based - Teton BGA Development Board. - -config MACH_GPLUGD - bool "Marvell's PXA168 GuruPlug Display (gplugD) Board" - depends on ARCH_MULTI_V5 - depends on UNUSED_BOARD_FILES - select CPU_PXA168 - help - Say 'Y' here if you want to support the Marvell PXA168-based - GuruPlug Display (gplugD) Board -endif - config MACH_MMP_DT bool "Support MMP (ARMv5) platforms from device tree" depends on ARCH_MULTI_V5 @@ -175,7 +82,4 @@ config USB_EHCI_MV_U2O help Enables support for OTG controller which can be switched to host mode. -config MMP_SRAM - bool - endif diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile index 539d750aaf10..5d4a1a4a48cf 100644 --- a/arch/arm/mach-mmp/Makefile +++ b/arch/arm/mach-mmp/Makefile @@ -2,32 +2,13 @@ # # Makefile for Marvell's PXA168 processors line # -obj-y += common.o devices.o time.o +obj-y += common.o time.o -# SoC support -obj-$(CONFIG_CPU_PXA168) += pxa168.o -obj-$(CONFIG_CPU_PXA910) += pxa910.o -obj-$(CONFIG_CPU_MMP2) += mmp2.o -obj-$(CONFIG_MMP_SRAM) += sram.o - -ifeq ($(CONFIG_PM),y) -obj-$(CONFIG_CPU_PXA910) += pm-pxa910.o -obj-$(CONFIG_CPU_MMP2) += pm-mmp2.o -endif ifeq ($(CONFIG_SMP),y) obj-$(CONFIG_MACH_MMP3_DT) += platsmp.o endif # board support -obj-$(CONFIG_MACH_ASPENITE) += aspenite.o -obj-$(CONFIG_MACH_ZYLONITE2) += aspenite.o -obj-$(CONFIG_MACH_AVENGERS_LITE)+= avengers_lite.o -obj-$(CONFIG_MACH_TTC_DKB) += ttc_dkb.o -obj-$(CONFIG_MACH_BROWNSTONE) += brownstone.o -obj-$(CONFIG_MACH_FLINT) += flint.o -obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o obj-$(CONFIG_MACH_MMP_DT) += mmp-dt.o obj-$(CONFIG_MACH_MMP2_DT) += mmp2-dt.o obj-$(CONFIG_MACH_MMP3_DT) += mmp3.o -obj-$(CONFIG_MACH_TETON_BGA) += teton_bga.o -obj-$(CONFIG_MACH_GPLUGD) += gplugd.o diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c deleted file mode 100644 index 6314824b62fc..000000000000 --- a/arch/arm/mach-mmp/aspenite.c +++ /dev/null @@ -1,284 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-mmp/aspenite.c - * - * Support for the Marvell PXA168-based Aspenite and Zylonite2 - * Development Platform. - */ -#include <linux/gpio.h> -#include <linux/gpio-pxa.h> -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/smc91x.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/mtd/rawnand.h> -#include <linux/interrupt.h> -#include <linux/platform_data/mv_usb.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <video/pxa168fb.h> -#include <linux/input.h> -#include <linux/platform_data/keypad-pxa27x.h> - -#include "addr-map.h" -#include "mfp-pxa168.h" -#include "pxa168.h" -#include "pxa910.h" -#include "irqs.h" -#include "common.h" - -static unsigned long common_pin_config[] __initdata = { - /* Data Flash Interface */ - GPIO0_DFI_D15, - GPIO1_DFI_D14, - GPIO2_DFI_D13, - GPIO3_DFI_D12, - GPIO4_DFI_D11, - GPIO5_DFI_D10, - GPIO6_DFI_D9, - GPIO7_DFI_D8, - GPIO8_DFI_D7, - GPIO9_DFI_D6, - GPIO10_DFI_D5, - GPIO11_DFI_D4, - GPIO12_DFI_D3, - GPIO13_DFI_D2, - GPIO14_DFI_D1, - GPIO15_DFI_D0, - - /* Static Memory Controller */ - GPIO18_SMC_nCS0, - GPIO34_SMC_nCS1, - GPIO23_SMC_nLUA, - GPIO25_SMC_nLLA, - GPIO28_SMC_RDY, - GPIO29_SMC_SCLK, - GPIO35_SMC_BE1, - GPIO36_SMC_BE2, - GPIO27_GPIO, /* Ethernet IRQ */ - - /* UART1 */ - GPIO107_UART1_RXD, - GPIO108_UART1_TXD, - - /* SSP1 */ - GPIO113_I2S_MCLK, - GPIO114_I2S_FRM, - GPIO115_I2S_BCLK, - GPIO116_I2S_RXD, - GPIO117_I2S_TXD, - - /* LCD */ - GPIO56_LCD_FCLK_RD, - GPIO57_LCD_LCLK_A0, - GPIO58_LCD_PCLK_WR, - GPIO59_LCD_DENA_BIAS, - GPIO60_LCD_DD0, - GPIO61_LCD_DD1, - GPIO62_LCD_DD2, - GPIO63_LCD_DD3, - GPIO64_LCD_DD4, - GPIO65_LCD_DD5, - GPIO66_LCD_DD6, - GPIO67_LCD_DD7, - GPIO68_LCD_DD8, - GPIO69_LCD_DD9, - GPIO70_LCD_DD10, - GPIO71_LCD_DD11, - GPIO72_LCD_DD12, - GPIO73_LCD_DD13, - GPIO74_LCD_DD14, - GPIO75_LCD_DD15, - GPIO76_LCD_DD16, - GPIO77_LCD_DD17, - GPIO78_LCD_DD18, - GPIO79_LCD_DD19, - GPIO80_LCD_DD20, - GPIO81_LCD_DD21, - GPIO82_LCD_DD22, - GPIO83_LCD_DD23, - - /* Keypad */ - GPIO109_KP_MKIN1, - GPIO110_KP_MKIN0, - GPIO111_KP_MKOUT7, - GPIO112_KP_MKOUT6, - GPIO121_KP_MKIN4, -}; - -static struct pxa_gpio_platform_data pxa168_gpio_pdata = { - .irq_base = MMP_GPIO_TO_IRQ(0), -}; - -static struct smc91x_platdata smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, -}; - -static struct resource smc91x_resources[] = { - [0] = { - .start = SMC_CS1_PHYS_BASE + 0x300, - .end = SMC_CS1_PHYS_BASE + 0xfffff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = MMP_GPIO_TO_IRQ(27), - .end = MMP_GPIO_TO_IRQ(27), - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, - } -}; - -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = 0, - .dev = { - .platform_data = &smc91x_info, - }, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, -}; - -static struct mtd_partition aspenite_nand_partitions[] = { - { - .name = "bootloader", - .offset = 0, - .size = SZ_1M, - .mask_flags = MTD_WRITEABLE, - }, { - .name = "reserved", - .offset = MTDPART_OFS_APPEND, - .size = SZ_128K, - .mask_flags = MTD_WRITEABLE, - }, { - .name = "reserved", - .offset = MTDPART_OFS_APPEND, - .size = SZ_8M, - .mask_flags = MTD_WRITEABLE, - }, { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = (SZ_2M + SZ_1M), - .mask_flags = 0, - }, { - .name = "filesystem", - .offset = MTDPART_OFS_APPEND, - .size = SZ_32M + SZ_16M, - .mask_flags = 0, - } -}; - -static struct pxa3xx_nand_platform_data aspenite_nand_info = { - .parts = aspenite_nand_partitions, - .nr_parts = ARRAY_SIZE(aspenite_nand_partitions), -}; - -static struct i2c_board_info aspenite_i2c_info[] __initdata = { - { I2C_BOARD_INFO("wm8753", 0x1b), }, -}; - -static struct fb_videomode video_modes[] = { - [0] = { - .pixclock = 30120, - .refresh = 60, - .xres = 800, - .yres = 480, - .hsync_len = 1, - .left_margin = 215, - .right_margin = 40, - .vsync_len = 1, - .upper_margin = 34, - .lower_margin = 10, - .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT, - }, -}; - -struct pxa168fb_mach_info aspenite_lcd_info = { - .id = "Graphic Frame", - .modes = video_modes, - .num_modes = ARRAY_SIZE(video_modes), - .pix_fmt = PIX_FMT_RGB565, - .io_pin_allocation_mode = PIN_MODE_DUMB_24, - .dumb_mode = DUMB_MODE_RGB888, - .active = 1, - .panel_rbswap = 0, - .invert_pixclock = 0, -}; - -static const unsigned int aspenite_matrix_key_map[] = { - KEY(0, 6, KEY_UP), /* SW 4 */ - KEY(0, 7, KEY_DOWN), /* SW 5 */ - KEY(1, 6, KEY_LEFT), /* SW 6 */ - KEY(1, 7, KEY_RIGHT), /* SW 7 */ - KEY(4, 6, KEY_ENTER), /* SW 8 */ - KEY(4, 7, KEY_ESC), /* SW 9 */ -}; - -static struct matrix_keymap_data aspenite_matrix_keymap_data = { - .keymap = aspenite_matrix_key_map, - .keymap_size = ARRAY_SIZE(aspenite_matrix_key_map), -}; - -static struct pxa27x_keypad_platform_data aspenite_keypad_info __initdata = { - .matrix_key_rows = 5, - .matrix_key_cols = 8, - .matrix_keymap_data = &aspenite_matrix_keymap_data, - .debounce_interval = 30, -}; - -#if IS_ENABLED(CONFIG_USB_EHCI_MV) -static struct mv_usb_platform_data pxa168_sph_pdata = { - .mode = MV_USB_MODE_HOST, - .phy_init = pxa_usb_phy_init, - .phy_deinit = pxa_usb_phy_deinit, - .set_vbus = NULL, -}; -#endif - -static void __init common_init(void) -{ - mfp_config(ARRAY_AND_SIZE(common_pin_config)); - - /* on-chip devices */ - pxa168_add_uart(1); - pxa168_add_twsi(1, NULL, ARRAY_AND_SIZE(aspenite_i2c_info)); - pxa168_add_ssp(1); - pxa168_add_nand(&aspenite_nand_info); - pxa168_add_fb(&aspenite_lcd_info); - pxa168_add_keypad(&aspenite_keypad_info); - platform_device_add_data(&pxa168_device_gpio, &pxa168_gpio_pdata, - sizeof(struct pxa_gpio_platform_data)); - platform_device_register(&pxa168_device_gpio); - - /* off-chip devices */ - platform_device_register(&smc91x_device); - -#if IS_ENABLED(CONFIG_USB_SUPPORT) -#if IS_ENABLED(CONFIG_PHY_PXA_USB) - platform_device_register(&pxa168_device_usb_phy); -#endif - -#if IS_ENABLED(CONFIG_USB_EHCI_MV) - pxa168_add_usb_host(&pxa168_sph_pdata); -#endif -#endif -} - -MACHINE_START(ASPENITE, "PXA168-based Aspenite Development Platform") - .map_io = mmp_map_io, - .nr_irqs = MMP_NR_IRQS, - .init_irq = pxa168_init_irq, - .init_time = pxa168_timer_init, - .init_machine = common_init, - .restart = pxa168_restart, -MACHINE_END - -MACHINE_START(ZYLONITE2, "PXA168-based Zylonite2 Development Platform") - .map_io = mmp_map_io, - .nr_irqs = MMP_NR_IRQS, - .init_irq = pxa168_init_irq, - .init_time = pxa168_timer_init, - .init_machine = common_init, - .restart = pxa168_restart, -MACHINE_END diff --git a/arch/arm/mach-mmp/avengers_lite.c b/arch/arm/mach-mmp/avengers_lite.c deleted file mode 100644 index 12e5a9441df9..000000000000 --- a/arch/arm/mach-mmp/avengers_lite.c +++ /dev/null @@ -1,55 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-mmp/avengers_lite.c - * - * Support for the Marvell PXA168-based Avengers lite Development Platform. - * - * Copyright (C) 2009-2010 Marvell International Ltd. - */ - -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/gpio-pxa.h> -#include <linux/platform_device.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include "addr-map.h" -#include "mfp-pxa168.h" -#include "pxa168.h" -#include "irqs.h" - - -#include "common.h" -#include <linux/delay.h> - -/* Avengers lite MFP configurations */ -static unsigned long avengers_lite_pin_config_V16F[] __initdata = { - /* DEBUG_UART */ - GPIO88_UART2_TXD, - GPIO89_UART2_RXD, -}; - -static struct pxa_gpio_platform_data pxa168_gpio_pdata = { - .irq_base = MMP_GPIO_TO_IRQ(0), -}; - -static void __init avengers_lite_init(void) -{ - mfp_config(ARRAY_AND_SIZE(avengers_lite_pin_config_V16F)); - - /* on-chip devices */ - pxa168_add_uart(2); - platform_device_add_data(&pxa168_device_gpio, &pxa168_gpio_pdata, - sizeof(struct pxa_gpio_platform_data)); - platform_device_register(&pxa168_device_gpio); -} - -MACHINE_START(AVENGERS_LITE, "PXA168 Avengers lite Development Platform") - .map_io = mmp_map_io, - .nr_irqs = MMP_NR_IRQS, - .init_irq = pxa168_init_irq, - .init_time = pxa168_timer_init, - .init_machine = avengers_lite_init, - .restart = pxa168_restart, -MACHINE_END diff --git a/arch/arm/mach-mmp/brownstone.c b/arch/arm/mach-mmp/brownstone.c deleted file mode 100644 index ce93bc395546..000000000000 --- a/arch/arm/mach-mmp/brownstone.c +++ /dev/null @@ -1,237 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-mmp/brownstone.c - * - * Support for the Marvell Brownstone Development Platform. - * - * Copyright (C) 2009-2010 Marvell International Ltd. - */ - -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/gpio-pxa.h> -#include <linux/gpio/machine.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/max8649.h> -#include <linux/regulator/fixed.h> -#include <linux/mfd/max8925.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include "addr-map.h" -#include "mfp-mmp2.h" -#include "mmp2.h" -#include "irqs.h" - -#include "common.h" - -#define BROWNSTONE_NR_IRQS (MMP_NR_IRQS + 40) - -#define GPIO_5V_ENABLE (89) - -static unsigned long brownstone_pin_config[] __initdata = { - /* UART1 */ - GPIO29_UART1_RXD, - GPIO30_UART1_TXD, - - /* UART3 */ - GPIO51_UART3_RXD, - GPIO52_UART3_TXD, - - /* DFI */ - GPIO168_DFI_D0, - GPIO167_DFI_D1, - GPIO166_DFI_D2, - GPIO165_DFI_D3, - GPIO107_DFI_D4, - GPIO106_DFI_D5, - GPIO105_DFI_D6, - GPIO104_DFI_D7, - GPIO111_DFI_D8, - GPIO164_DFI_D9, - GPIO163_DFI_D10, - GPIO162_DFI_D11, - GPIO161_DFI_D12, - GPIO110_DFI_D13, - GPIO109_DFI_D14, - GPIO108_DFI_D15, - GPIO143_ND_nCS0, - GPIO144_ND_nCS1, - GPIO147_ND_nWE, - GPIO148_ND_nRE, - GPIO150_ND_ALE, - GPIO149_ND_CLE, - GPIO112_ND_RDY0, - GPIO160_ND_RDY1, - - /* PMIC */ - PMIC_PMIC_INT | MFP_LPM_EDGE_FALL, - - /* MMC0 */ - GPIO131_MMC1_DAT3 | MFP_PULL_HIGH, - GPIO132_MMC1_DAT2 | MFP_PULL_HIGH, - GPIO133_MMC1_DAT1 | MFP_PULL_HIGH, - GPIO134_MMC1_DAT0 | MFP_PULL_HIGH, - GPIO136_MMC1_CMD | MFP_PULL_HIGH, - GPIO139_MMC1_CLK, - GPIO140_MMC1_CD | MFP_PULL_LOW, - GPIO141_MMC1_WP | MFP_PULL_LOW, - - /* MMC1 */ - GPIO37_MMC2_DAT3 | MFP_PULL_HIGH, - GPIO38_MMC2_DAT2 | MFP_PULL_HIGH, - GPIO39_MMC2_DAT1 | MFP_PULL_HIGH, - GPIO40_MMC2_DAT0 | MFP_PULL_HIGH, - GPIO41_MMC2_CMD | MFP_PULL_HIGH, - GPIO42_MMC2_CLK, - - /* MMC2 */ - GPIO165_MMC3_DAT7 | MFP_PULL_HIGH, - GPIO162_MMC3_DAT6 | MFP_PULL_HIGH, - GPIO166_MMC3_DAT5 | MFP_PULL_HIGH, - GPIO163_MMC3_DAT4 | MFP_PULL_HIGH, - GPIO167_MMC3_DAT3 | MFP_PULL_HIGH, - GPIO164_MMC3_DAT2 | MFP_PULL_HIGH, - GPIO168_MMC3_DAT1 | MFP_PULL_HIGH, - GPIO111_MMC3_DAT0 | MFP_PULL_HIGH, - GPIO112_MMC3_CMD | MFP_PULL_HIGH, - GPIO151_MMC3_CLK, - - /* 5V regulator */ - GPIO89_GPIO, -}; - -static struct pxa_gpio_platform_data mmp2_gpio_pdata = { - .irq_base = MMP_GPIO_TO_IRQ(0), -}; - -static struct regulator_consumer_supply max8649_supply[] = { - REGULATOR_SUPPLY("vcc_core", NULL), -}; - -static struct regulator_init_data max8649_init_data = { - .constraints = { - .name = "vcc_core range", - .min_uV = 1150000, - .max_uV = 1280000, - .always_on = 1, - .boot_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &max8649_supply[0], -}; - -static struct max8649_platform_data brownstone_max8649_info = { - .mode = 2, /* VID1 = 1, VID0 = 0 */ - .extclk = 0, - .ramp_timing = MAX8649_RAMP_32MV, - .regulator = &max8649_init_data, -}; - -static struct regulator_consumer_supply brownstone_v_5vp_supplies[] = { - REGULATOR_SUPPLY("v_5vp", NULL), -}; - -static struct regulator_init_data brownstone_v_5vp_data = { - .constraints = { - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, - .num_consumer_supplies = ARRAY_SIZE(brownstone_v_5vp_supplies), - .consumer_supplies = brownstone_v_5vp_supplies, -}; - -static struct fixed_voltage_config brownstone_v_5vp = { - .supply_name = "v_5vp", - .microvolts = 5000000, - .enabled_at_boot = 1, - .init_data = &brownstone_v_5vp_data, -}; - -static struct platform_device brownstone_v_5vp_device = { - .name = "reg-fixed-voltage", - .id = 1, - .dev = { - .platform_data = &brownstone_v_5vp, - }, -}; - -static struct gpiod_lookup_table brownstone_v_5vp_gpiod_table = { - .dev_id = "reg-fixed-voltage.1", /* .id set to 1 above */ - .table = { - GPIO_LOOKUP("gpio-pxa", GPIO_5V_ENABLE, - NULL, GPIO_ACTIVE_HIGH), - { }, - }, -}; - -static struct max8925_platform_data brownstone_max8925_info = { - .irq_base = MMP_NR_IRQS, -}; - -static struct i2c_board_info brownstone_twsi1_info[] = { - [0] = { - .type = "max8649", - .addr = 0x60, - .platform_data = &brownstone_max8649_info, - }, - [1] = { - .type = "max8925", - .addr = 0x3c, - .irq = IRQ_MMP2_PMIC, - .platform_data = &brownstone_max8925_info, - }, -}; - -static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc0 = { - .clk_delay_cycles = 0x1f, -}; - -static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc2 = { - .clk_delay_cycles = 0x1f, - .flags = PXA_FLAG_CARD_PERMANENT - | PXA_FLAG_SD_8_BIT_CAPABLE_SLOT, -}; - -static struct sram_platdata mmp2_asram_platdata = { - .pool_name = "asram", - .granularity = SRAM_GRANULARITY, -}; - -static struct sram_platdata mmp2_isram_platdata = { - .pool_name = "isram", - .granularity = SRAM_GRANULARITY, -}; - -static void __init brownstone_init(void) -{ - mfp_config(ARRAY_AND_SIZE(brownstone_pin_config)); - - /* on-chip devices */ - mmp2_add_uart(1); - mmp2_add_uart(3); - platform_device_add_data(&mmp2_device_gpio, &mmp2_gpio_pdata, - sizeof(struct pxa_gpio_platform_data)); - platform_device_register(&mmp2_device_gpio); - mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(brownstone_twsi1_info)); - mmp2_add_sdhost(0, &mmp2_sdh_platdata_mmc0); /* SD/MMC */ - mmp2_add_sdhost(2, &mmp2_sdh_platdata_mmc2); /* eMMC */ - mmp2_add_asram(&mmp2_asram_platdata); - mmp2_add_isram(&mmp2_isram_platdata); - - /* enable 5v regulator */ - gpiod_add_lookup_table(&brownstone_v_5vp_gpiod_table); - platform_device_register(&brownstone_v_5vp_device); -} - -MACHINE_START(BROWNSTONE, "Brownstone Development Platform") - /* Maintainer: Haojian Zhuang <haojian.zhuang@marvell.com> */ - .map_io = mmp_map_io, - .nr_irqs = BROWNSTONE_NR_IRQS, - .init_irq = mmp2_init_irq, - .init_time = mmp2_timer_init, - .init_machine = brownstone_init, - .restart = mmp_restart, -MACHINE_END diff --git a/arch/arm/mach-mmp/common.c b/arch/arm/mach-mmp/common.c index e94349d4726c..b3c1a248db31 100644 --- a/arch/arm/mach-mmp/common.c +++ b/arch/arm/mach-mmp/common.c @@ -58,8 +58,3 @@ void __init mmp2_map_io(void) mmp_map_io(); iotable_init(mmp2_io_desc, ARRAY_SIZE(mmp2_io_desc)); } - -void mmp_restart(enum reboot_mode mode, const char *cmd) -{ - soft_restart(0); -} diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h index ed56b3f15b45..e18f05d5d68d 100644 --- a/arch/arm/mach-mmp/common.h +++ b/arch/arm/mach-mmp/common.h @@ -1,9 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ #include <linux/reboot.h> -#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x) extern void mmp_timer_init(int irq, unsigned long rate); extern void __init mmp_map_io(void); extern void __init mmp2_map_io(void); -extern void mmp_restart(enum reboot_mode, const char *); diff --git a/arch/arm/mach-mmp/devices.c b/arch/arm/mach-mmp/devices.c deleted file mode 100644 index 9968239d8041..000000000000 --- a/arch/arm/mach-mmp/devices.c +++ /dev/null @@ -1,359 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-mmp/devices.c - */ - -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/dma-mapping.h> -#include <linux/delay.h> - -#include <asm/irq.h> -#include "irqs.h" -#include "devices.h" -#include <linux/soc/mmp/cputype.h> -#include "regs-usb.h" - -int __init mmp_register_device(struct mmp_device_desc *desc, - void *data, size_t size) -{ - struct platform_device *pdev; - struct resource res[2 + MAX_RESOURCE_DMA]; - int i, ret = 0, nres = 0; - - pdev = platform_device_alloc(desc->drv_name, desc->id); - if (pdev == NULL) - return -ENOMEM; - - pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); - - memset(res, 0, sizeof(res)); - - if (desc->start != -1ul && desc->size > 0) { - res[nres].start = desc->start; - res[nres].end = desc->start + desc->size - 1; - res[nres].flags = IORESOURCE_MEM; - nres++; - } - - if (desc->irq != NO_IRQ) { - res[nres].start = desc->irq; - res[nres].end = desc->irq; - res[nres].flags = IORESOURCE_IRQ; - nres++; - } - - for (i = 0; i < MAX_RESOURCE_DMA; i++, nres++) { - if (desc->dma[i] == 0) - break; - - res[nres].start = desc->dma[i]; - res[nres].end = desc->dma[i]; - res[nres].flags = IORESOURCE_DMA; - } - - ret = platform_device_add_resources(pdev, res, nres); - if (ret) { - platform_device_put(pdev); - return ret; - } - - if (data && size) { - ret = platform_device_add_data(pdev, data, size); - if (ret) { - platform_device_put(pdev); - return ret; - } - } - - return platform_device_add(pdev); -} - -#if IS_ENABLED(CONFIG_USB) || IS_ENABLED(CONFIG_USB_GADGET) -#if IS_ENABLED(CONFIG_USB_MV_UDC) || IS_ENABLED(CONFIG_USB_EHCI_MV) -#if IS_ENABLED(CONFIG_CPU_PXA910) || IS_ENABLED(CONFIG_CPU_PXA168) - -/***************************************************************************** - * The registers read/write routines - *****************************************************************************/ - -static unsigned int u2o_get(void __iomem *base, unsigned int offset) -{ - return readl_relaxed(base + offset); -} - -static void u2o_set(void __iomem *base, unsigned int offset, - unsigned int value) -{ - u32 reg; - - reg = readl_relaxed(base + offset); - reg |= value; - writel_relaxed(reg, base + offset); - readl_relaxed(base + offset); -} - -static void u2o_clear(void __iomem *base, unsigned int offset, - unsigned int value) -{ - u32 reg; - - reg = readl_relaxed(base + offset); - reg &= ~value; - writel_relaxed(reg, base + offset); - readl_relaxed(base + offset); -} - -static void u2o_write(void __iomem *base, unsigned int offset, - unsigned int value) -{ - writel_relaxed(value, base + offset); - readl_relaxed(base + offset); -} - - -static DEFINE_MUTEX(phy_lock); -static int phy_init_cnt; - -static int usb_phy_init_internal(void __iomem *base) -{ - int loops; - - pr_info("Init usb phy!!!\n"); - - /* Initialize the USB PHY power */ - if (cpu_is_pxa910()) { - u2o_set(base, UTMI_CTRL, (1<<UTMI_CTRL_INPKT_DELAY_SOF_SHIFT) - | (1<<UTMI_CTRL_PU_REF_SHIFT)); - } - - u2o_set(base, UTMI_CTRL, 1<<UTMI_CTRL_PLL_PWR_UP_SHIFT); - u2o_set(base, UTMI_CTRL, 1<<UTMI_CTRL_PWR_UP_SHIFT); - - /* UTMI_PLL settings */ - u2o_clear(base, UTMI_PLL, UTMI_PLL_PLLVDD18_MASK - | UTMI_PLL_PLLVDD12_MASK | UTMI_PLL_PLLCALI12_MASK - | UTMI_PLL_FBDIV_MASK | UTMI_PLL_REFDIV_MASK - | UTMI_PLL_ICP_MASK | UTMI_PLL_KVCO_MASK); - - u2o_set(base, UTMI_PLL, 0xee<<UTMI_PLL_FBDIV_SHIFT - | 0xb<<UTMI_PLL_REFDIV_SHIFT | 3<<UTMI_PLL_PLLVDD18_SHIFT - | 3<<UTMI_PLL_PLLVDD12_SHIFT | 3<<UTMI_PLL_PLLCALI12_SHIFT - | 1<<UTMI_PLL_ICP_SHIFT | 3<<UTMI_PLL_KVCO_SHIFT); - - /* UTMI_TX */ - u2o_clear(base, UTMI_TX, UTMI_TX_REG_EXT_FS_RCAL_EN_MASK - | UTMI_TX_TXVDD12_MASK | UTMI_TX_CK60_PHSEL_MASK - | UTMI_TX_IMPCAL_VTH_MASK | UTMI_TX_REG_EXT_FS_RCAL_MASK - | UTMI_TX_AMP_MASK); - u2o_set(base, UTMI_TX, 3<<UTMI_TX_TXVDD12_SHIFT - | 4<<UTMI_TX_CK60_PHSEL_SHIFT | 4<<UTMI_TX_IMPCAL_VTH_SHIFT - | 8<<UTMI_TX_REG_EXT_FS_RCAL_SHIFT | 3<<UTMI_TX_AMP_SHIFT); - - /* UTMI_RX */ - u2o_clear(base, UTMI_RX, UTMI_RX_SQ_THRESH_MASK - | UTMI_REG_SQ_LENGTH_MASK); - u2o_set(base, UTMI_RX, 7<<UTMI_RX_SQ_THRESH_SHIFT - | 2<<UTMI_REG_SQ_LENGTH_SHIFT); - - /* UTMI_IVREF */ - if (cpu_is_pxa168()) - /* fixing Microsoft Altair board interface with NEC hub issue - - * Set UTMI_IVREF from 0x4a3 to 0x4bf */ - u2o_write(base, UTMI_IVREF, 0x4bf); - - /* toggle VCOCAL_START bit of UTMI_PLL */ - udelay(200); - u2o_set(base, UTMI_PLL, VCOCAL_START); - udelay(40); - u2o_clear(base, UTMI_PLL, VCOCAL_START); - - /* toggle REG_RCAL_START bit of UTMI_TX */ - udelay(400); - u2o_set(base, UTMI_TX, REG_RCAL_START); - udelay(40); - u2o_clear(base, UTMI_TX, REG_RCAL_START); - udelay(400); - - /* Make sure PHY PLL is ready */ - loops = 0; - while ((u2o_get(base, UTMI_PLL) & PLL_READY) == 0) { - mdelay(1); - loops++; - if (loops > 100) { - printk(KERN_WARNING "calibrate timeout, UTMI_PLL %x\n", - u2o_get(base, UTMI_PLL)); - break; - } - } - - if (cpu_is_pxa168()) { - u2o_set(base, UTMI_RESERVE, 1 << 5); - /* Turn on UTMI PHY OTG extension */ - u2o_write(base, UTMI_OTG_ADDON, 1); - } - - return 0; -} - -static int usb_phy_deinit_internal(void __iomem *base) -{ - pr_info("Deinit usb phy!!!\n"); - - if (cpu_is_pxa168()) - u2o_clear(base, UTMI_OTG_ADDON, UTMI_OTG_ADDON_OTG_ON); - - u2o_clear(base, UTMI_CTRL, UTMI_CTRL_RXBUF_PDWN); - u2o_clear(base, UTMI_CTRL, UTMI_CTRL_TXBUF_PDWN); - u2o_clear(base, UTMI_CTRL, UTMI_CTRL_USB_CLK_EN); - u2o_clear(base, UTMI_CTRL, 1<<UTMI_CTRL_PWR_UP_SHIFT); - u2o_clear(base, UTMI_CTRL, 1<<UTMI_CTRL_PLL_PWR_UP_SHIFT); - - return 0; -} - -int pxa_usb_phy_init(void __iomem *phy_reg) -{ - mutex_lock(&phy_lock); - if (phy_init_cnt++ == 0) - usb_phy_init_internal(phy_reg); - mutex_unlock(&phy_lock); - return 0; -} - -void pxa_usb_phy_deinit(void __iomem *phy_reg) -{ - WARN_ON(phy_init_cnt == 0); - - mutex_lock(&phy_lock); - if (--phy_init_cnt == 0) - usb_phy_deinit_internal(phy_reg); - mutex_unlock(&phy_lock); -} -#endif -#endif -#endif - -#if IS_ENABLED(CONFIG_USB_SUPPORT) -static u64 __maybe_unused usb_dma_mask = ~(u32)0; - -#if IS_ENABLED(CONFIG_PHY_PXA_USB) -static struct resource pxa168_usb_phy_resources[] = { - [0] = { - .start = PXA168_U2O_PHYBASE, - .end = PXA168_U2O_PHYBASE + USB_PHY_RANGE, - .flags = IORESOURCE_MEM, - }, -}; - -struct platform_device pxa168_device_usb_phy = { - .name = "pxa-usb-phy", - .id = -1, - .resource = pxa168_usb_phy_resources, - .num_resources = ARRAY_SIZE(pxa168_usb_phy_resources), - .dev = { - .dma_mask = &usb_dma_mask, - .coherent_dma_mask = 0xffffffff, - } -}; -#endif /* CONFIG_PHY_PXA_USB */ - -#if IS_ENABLED(CONFIG_USB_MV_UDC) -static struct resource pxa168_u2o_resources[] = { - /* regbase */ - [0] = { - .start = PXA168_U2O_REGBASE + U2x_CAPREGS_OFFSET, - .end = PXA168_U2O_REGBASE + USB_REG_RANGE, - .flags = IORESOURCE_MEM, - .name = "capregs", - }, - /* phybase */ - [1] = { - .start = PXA168_U2O_PHYBASE, - .end = PXA168_U2O_PHYBASE + USB_PHY_RANGE, - .flags = IORESOURCE_MEM, - .name = "phyregs", - }, - [2] = { - .start = IRQ_PXA168_USB1, - .end = IRQ_PXA168_USB1, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device pxa168_device_u2o = { - .name = "mv-udc", - .id = -1, - .resource = pxa168_u2o_resources, - .num_resources = ARRAY_SIZE(pxa168_u2o_resources), - .dev = { - .dma_mask = &usb_dma_mask, - .coherent_dma_mask = 0xffffffff, - } -}; -#endif /* CONFIG_USB_MV_UDC */ - -#if IS_ENABLED(CONFIG_USB_EHCI_MV_U2O) -static struct resource pxa168_u2oehci_resources[] = { - [0] = { - .start = PXA168_U2O_REGBASE, - .end = PXA168_U2O_REGBASE + USB_REG_RANGE, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_PXA168_USB1, - .end = IRQ_PXA168_USB1, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device pxa168_device_u2oehci = { - .name = "pxa-u2oehci", - .id = -1, - .dev = { - .dma_mask = &usb_dma_mask, - .coherent_dma_mask = 0xffffffff, - }, - - .num_resources = ARRAY_SIZE(pxa168_u2oehci_resources), - .resource = pxa168_u2oehci_resources, -}; -#endif - -#if IS_ENABLED(CONFIG_USB_MV_OTG) -static struct resource pxa168_u2ootg_resources[] = { - /* regbase */ - [0] = { - .start = PXA168_U2O_REGBASE + U2x_CAPREGS_OFFSET, - .end = PXA168_U2O_REGBASE + USB_REG_RANGE, - .flags = IORESOURCE_MEM, - .name = "capregs", - }, - /* phybase */ - [1] = { - .start = PXA168_U2O_PHYBASE, - .end = PXA168_U2O_PHYBASE + USB_PHY_RANGE, - .flags = IORESOURCE_MEM, - .name = "phyregs", - }, - [2] = { - .start = IRQ_PXA168_USB1, - .end = IRQ_PXA168_USB1, - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device pxa168_device_u2ootg = { - .name = "mv-otg", - .id = -1, - .dev = { - .dma_mask = &usb_dma_mask, - .coherent_dma_mask = 0xffffffff, - }, - - .num_resources = ARRAY_SIZE(pxa168_u2ootg_resources), - .resource = pxa168_u2ootg_resources, -}; -#endif /* CONFIG_USB_MV_OTG */ - -#endif diff --git a/arch/arm/mach-mmp/devices.h b/arch/arm/mach-mmp/devices.h deleted file mode 100644 index d4920ebfebc5..000000000000 --- a/arch/arm/mach-mmp/devices.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __MACH_DEVICE_H -#define __MACH_DEVICE_H - -#include <linux/types.h> - -#define MAX_RESOURCE_DMA 2 - -/* structure for describing the on-chip devices */ -struct mmp_device_desc { - const char *dev_name; - const char *drv_name; - int id; - int irq; - unsigned long start; - unsigned long size; - int dma[MAX_RESOURCE_DMA]; -}; - -#define PXA168_DEVICE(_name, _drv, _id, _irq, _start, _size, _dma...) \ -struct mmp_device_desc pxa168_device_##_name __initdata = { \ - .dev_name = "pxa168-" #_name, \ - .drv_name = _drv, \ - .id = _id, \ - .irq = IRQ_PXA168_##_irq, \ - .start = _start, \ - .size = _size, \ - .dma = { _dma }, \ -}; - -#define PXA910_DEVICE(_name, _drv, _id, _irq, _start, _size, _dma...) \ -struct mmp_device_desc pxa910_device_##_name __initdata = { \ - .dev_name = "pxa910-" #_name, \ - .drv_name = _drv, \ - .id = _id, \ - .irq = IRQ_PXA910_##_irq, \ - .start = _start, \ - .size = _size, \ - .dma = { _dma }, \ -}; - -#define MMP2_DEVICE(_name, _drv, _id, _irq, _start, _size, _dma...) \ -struct mmp_device_desc mmp2_device_##_name __initdata = { \ - .dev_name = "mmp2-" #_name, \ - .drv_name = _drv, \ - .id = _id, \ - .irq = IRQ_MMP2_##_irq, \ - .start = _start, \ - .size = _size, \ - .dma = { _dma }, \ -} - -extern int mmp_register_device(struct mmp_device_desc *, void *, size_t); -extern int pxa_usb_phy_init(void __iomem *phy_reg); -extern void pxa_usb_phy_deinit(void __iomem *phy_reg); - -#endif /* __MACH_DEVICE_H */ diff --git a/arch/arm/mach-mmp/flint.c b/arch/arm/mach-mmp/flint.c deleted file mode 100644 index 9a7054368e55..000000000000 --- a/arch/arm/mach-mmp/flint.c +++ /dev/null @@ -1,131 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-mmp/flint.c - * - * Support for the Marvell Flint Development Platform. - * - * Copyright (C) 2009 Marvell International Ltd. - */ - -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/smc91x.h> -#include <linux/io.h> -#include <linux/gpio.h> -#include <linux/gpio-pxa.h> -#include <linux/interrupt.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include "addr-map.h" -#include "mfp-mmp2.h" -#include "mmp2.h" -#include "irqs.h" - -#include "common.h" - -#define FLINT_NR_IRQS (MMP_NR_IRQS + 48) - -static unsigned long flint_pin_config[] __initdata = { - /* UART1 */ - GPIO45_UART1_RXD, - GPIO46_UART1_TXD, - - /* UART2 */ - GPIO47_UART2_RXD, - GPIO48_UART2_TXD, - - /* SMC */ - GPIO151_SMC_SCLK, - GPIO145_SMC_nCS0, - GPIO146_SMC_nCS1, - GPIO152_SMC_BE0, - GPIO153_SMC_BE1, - GPIO154_SMC_IRQ, - GPIO113_SMC_RDY, - - /*Ethernet*/ - GPIO155_GPIO, - - /* DFI */ - GPIO168_DFI_D0, - GPIO167_DFI_D1, - GPIO166_DFI_D2, - GPIO165_DFI_D3, - GPIO107_DFI_D4, - GPIO106_DFI_D5, - GPIO105_DFI_D6, - GPIO104_DFI_D7, - GPIO111_DFI_D8, - GPIO164_DFI_D9, - GPIO163_DFI_D10, - GPIO162_DFI_D11, - GPIO161_DFI_D12, - GPIO110_DFI_D13, - GPIO109_DFI_D14, - GPIO108_DFI_D15, - GPIO143_ND_nCS0, - GPIO144_ND_nCS1, - GPIO147_ND_nWE, - GPIO148_ND_nRE, - GPIO150_ND_ALE, - GPIO149_ND_CLE, - GPIO112_ND_RDY0, - GPIO160_ND_RDY1, -}; - -static struct pxa_gpio_platform_data mmp2_gpio_pdata = { - .irq_base = MMP_GPIO_TO_IRQ(0), -}; - -static struct smc91x_platdata flint_smc91x_info = { - .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT, -}; - -static struct resource smc91x_resources[] = { - [0] = { - .start = SMC_CS1_PHYS_BASE + 0x300, - .end = SMC_CS1_PHYS_BASE + 0xfffff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = MMP_GPIO_TO_IRQ(155), - .end = MMP_GPIO_TO_IRQ(155), - .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE, - } -}; - -static struct platform_device smc91x_device = { - .name = "smc91x", - .id = 0, - .dev = { - .platform_data = &flint_smc91x_info, - }, - .num_resources = ARRAY_SIZE(smc91x_resources), - .resource = smc91x_resources, -}; - -static void __init flint_init(void) -{ - mfp_config(ARRAY_AND_SIZE(flint_pin_config)); - - /* on-chip devices */ - mmp2_add_uart(1); - mmp2_add_uart(2); - platform_device_add_data(&mmp2_device_gpio, &mmp2_gpio_pdata, - sizeof(struct pxa_gpio_platform_data)); - platform_device_register(&mmp2_device_gpio); - - /* off-chip devices */ - platform_device_register(&smc91x_device); -} - -MACHINE_START(FLINT, "Flint Development Platform") - .map_io = mmp_map_io, - .nr_irqs = FLINT_NR_IRQS, - .init_irq = mmp2_init_irq, - .init_time = mmp2_timer_init, - .init_machine = flint_init, - .restart = mmp_restart, -MACHINE_END diff --git a/arch/arm/mach-mmp/gplugd.c b/arch/arm/mach-mmp/gplugd.c deleted file mode 100644 index 5888b71944b8..000000000000 --- a/arch/arm/mach-mmp/gplugd.c +++ /dev/null @@ -1,206 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-mmp/gplugd.c - * - * Support for the Marvell PXA168-based GuruPlug Display (gplugD) Platform. - */ - -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/gpio.h> -#include <linux/gpio-pxa.h> - -#include <asm/mach/arch.h> -#include <asm/mach-types.h> - -#include "irqs.h" -#include "pxa168.h" -#include "mfp-pxa168.h" - -#include "common.h" - -static unsigned long gplugd_pin_config[] __initdata = { - /* UART3 */ - GPIO8_UART3_TXD, - GPIO9_UART3_RXD, - GPIO1O_UART3_CTS, - GPIO11_UART3_RTS, - - /* USB OTG PEN */ - GPIO18_GPIO, - - /* MMC2 */ - GPIO28_MMC2_CMD, - GPIO29_MMC2_CLK, - GPIO30_MMC2_DAT0, - GPIO31_MMC2_DAT1, - GPIO32_MMC2_DAT2, - GPIO33_MMC2_DAT3, - - /* LCD & HDMI clock selection GPIO: 0: 74.176MHz, 1: 74.25 MHz */ - GPIO35_GPIO, - GPIO36_GPIO, /* CEC Interrupt */ - - /* MMC1 */ - GPIO43_MMC1_CLK, - GPIO49_MMC1_CMD, - GPIO41_MMC1_DAT0, - GPIO40_MMC1_DAT1, - GPIO52_MMC1_DAT2, - GPIO51_MMC1_DAT3, - GPIO53_MMC1_CD, - - /* LCD */ - GPIO56_LCD_FCLK_RD, - GPIO57_LCD_LCLK_A0, - GPIO58_LCD_PCLK_WR, - GPIO59_LCD_DENA_BIAS, - GPIO60_LCD_DD0, - GPIO61_LCD_DD1, - GPIO62_LCD_DD2, - GPIO63_LCD_DD3, - GPIO64_LCD_DD4, - GPIO65_LCD_DD5, - GPIO66_LCD_DD6, - GPIO67_LCD_DD7, - GPIO68_LCD_DD8, - GPIO69_LCD_DD9, - GPIO70_LCD_DD10, - GPIO71_LCD_DD11, - GPIO72_LCD_DD12, - GPIO73_LCD_DD13, - GPIO74_LCD_DD14, - GPIO75_LCD_DD15, - GPIO76_LCD_DD16, - GPIO77_LCD_DD17, - GPIO78_LCD_DD18, - GPIO79_LCD_DD19, - GPIO80_LCD_DD20, - GPIO81_LCD_DD21, - GPIO82_LCD_DD22, - GPIO83_LCD_DD23, - - /* GPIO */ - GPIO84_GPIO, - GPIO85_GPIO, - - /* Fast-Ethernet*/ - GPIO86_TX_CLK, - GPIO87_TX_EN, - GPIO88_TX_DQ3, - GPIO89_TX_DQ2, - GPIO90_TX_DQ1, - GPIO91_TX_DQ0, - GPIO92_MII_CRS, - GPIO93_MII_COL, - GPIO94_RX_CLK, - GPIO95_RX_ER, - GPIO96_RX_DQ3, - GPIO97_RX_DQ2, - GPIO98_RX_DQ1, - GPIO99_RX_DQ0, - GPIO100_MII_MDC, - GPIO101_MII_MDIO, - GPIO103_RX_DV, - GPIO104_GPIO, /* Reset PHY */ - - /* RTC interrupt */ - GPIO102_GPIO, - - /* I2C */ - GPIO105_CI2C_SDA, - GPIO106_CI2C_SCL, - - /* SPI NOR Flash on SSP2 */ - GPIO107_SSP2_RXD, - GPIO108_SSP2_TXD, - GPIO110_GPIO, /* SPI_CSn */ - GPIO111_SSP2_CLK, - - /* Select JTAG */ - GPIO109_GPIO, - - /* I2S */ - GPIO114_I2S_FRM, - GPIO115_I2S_BCLK, - GPIO116_I2S_TXD -}; - -static struct pxa_gpio_platform_data pxa168_gpio_pdata = { - .irq_base = MMP_GPIO_TO_IRQ(0), -}; - -static struct i2c_board_info gplugd_i2c_board_info[] = { - { - .type = "isl1208", - .addr = 0x6F, - } -}; - -/* Bring PHY out of reset by setting GPIO 104 */ -static int gplugd_eth_init(void) -{ - if (unlikely(gpio_request(104, "ETH_RESET_N"))) { - printk(KERN_ERR "Can't get hold of GPIO 104 to bring Ethernet " - "PHY out of reset\n"); - return -EIO; - } - - gpio_direction_output(104, 1); - gpio_free(104); - return 0; -} - -struct pxa168_eth_platform_data gplugd_eth_platform_data = { - .port_number = 0, - .phy_addr = 0, - .speed = 0, /* Autonagotiation */ - .intf = PHY_INTERFACE_MODE_RMII, - .init = gplugd_eth_init, -}; - -static void __init select_disp_freq(void) -{ - /* set GPIO 35 & clear GPIO 85 to set LCD External Clock to 74.25 MHz */ - if (unlikely(gpio_request(35, "DISP_FREQ_SEL"))) { - printk(KERN_ERR "Can't get hold of GPIO 35 to select display " - "frequency\n"); - } else { - gpio_direction_output(35, 1); - gpio_free(35); - } - - if (unlikely(gpio_request(85, "DISP_FREQ_SEL_2"))) { - printk(KERN_ERR "Can't get hold of GPIO 85 to select display " - "frequency\n"); - } else { - gpio_direction_output(85, 0); - gpio_free(85); - } -} - -static void __init gplugd_init(void) -{ - mfp_config(ARRAY_AND_SIZE(gplugd_pin_config)); - - select_disp_freq(); - - /* on-chip devices */ - pxa168_add_uart(3); - pxa168_add_ssp(1); - pxa168_add_twsi(0, NULL, ARRAY_AND_SIZE(gplugd_i2c_board_info)); - platform_device_add_data(&pxa168_device_gpio, &pxa168_gpio_pdata, - sizeof(struct pxa_gpio_platform_data)); - platform_device_register(&pxa168_device_gpio); - - pxa168_add_eth(&gplugd_eth_platform_data); -} - -MACHINE_START(GPLUGD, "PXA168-based GuruPlug Display (gplugD) Platform") - .map_io = mmp_map_io, - .nr_irqs = MMP_NR_IRQS, - .init_irq = pxa168_init_irq, - .init_time = pxa168_timer_init, - .init_machine = gplugd_init, - .restart = pxa168_restart, -MACHINE_END diff --git a/arch/arm/mach-mmp/irqs.h b/arch/arm/mach-mmp/irqs.h deleted file mode 100644 index 5acc4d532a43..000000000000 --- a/arch/arm/mach-mmp/irqs.h +++ /dev/null @@ -1,240 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_MACH_IRQS_H -#define __ASM_MACH_IRQS_H - -/* - * Interrupt numbers for PXA168 - */ -#define IRQ_PXA168_NONE (-1) -#define IRQ_PXA168_SSP4 0 -#define IRQ_PXA168_SSP3 1 -#define IRQ_PXA168_SSP2 2 -#define IRQ_PXA168_SSP1 3 -#define IRQ_PXA168_PMIC_INT 4 -#define IRQ_PXA168_RTC_INT 5 -#define IRQ_PXA168_RTC_ALARM 6 -#define IRQ_PXA168_TWSI0 7 -#define IRQ_PXA168_GPU 8 -#define IRQ_PXA168_KEYPAD 9 -#define IRQ_PXA168_ONEWIRE 12 -#define IRQ_PXA168_TIMER1 13 -#define IRQ_PXA168_TIMER2 14 -#define IRQ_PXA168_TIMER3 15 -#define IRQ_PXA168_CMU 16 -#define IRQ_PXA168_SSP5 17 -#define IRQ_PXA168_MSP_WAKEUP 19 -#define IRQ_PXA168_CF_WAKEUP 20 -#define IRQ_PXA168_XD_WAKEUP 21 -#define IRQ_PXA168_MFU 22 -#define IRQ_PXA168_MSP 23 -#define IRQ_PXA168_CF 24 -#define IRQ_PXA168_XD 25 -#define IRQ_PXA168_DDR_INT 26 -#define IRQ_PXA168_UART1 27 -#define IRQ_PXA168_UART2 28 -#define IRQ_PXA168_UART3 29 -#define IRQ_PXA168_WDT 35 -#define IRQ_PXA168_MAIN_PMU 36 -#define IRQ_PXA168_FRQ_CHANGE 38 -#define IRQ_PXA168_SDH1 39 -#define IRQ_PXA168_SDH2 40 -#define IRQ_PXA168_LCD 41 -#define IRQ_PXA168_CI 42 -#define IRQ_PXA168_USB1 44 -#define IRQ_PXA168_NAND 45 -#define IRQ_PXA168_HIFI_DMA 46 -#define IRQ_PXA168_DMA_INT0 47 -#define IRQ_PXA168_DMA_INT1 48 -#define IRQ_PXA168_GPIOX 49 -#define IRQ_PXA168_USB2 51 -#define IRQ_PXA168_AC97 57 -#define IRQ_PXA168_TWSI1 58 -#define IRQ_PXA168_AP_PMU 60 -#define IRQ_PXA168_SM_INT 63 - -/* - * Interrupt numbers for PXA910 - */ -#define IRQ_PXA910_NONE (-1) -#define IRQ_PXA910_AIRQ 0 -#define IRQ_PXA910_SSP3 1 -#define IRQ_PXA910_SSP2 2 -#define IRQ_PXA910_SSP1 3 -#define IRQ_PXA910_PMIC_INT 4 -#define IRQ_PXA910_RTC_INT 5 -#define IRQ_PXA910_RTC_ALARM 6 -#define IRQ_PXA910_TWSI0 7 -#define IRQ_PXA910_GPU 8 -#define IRQ_PXA910_KEYPAD 9 -#define IRQ_PXA910_ROTARY 10 -#define IRQ_PXA910_TRACKBALL 11 -#define IRQ_PXA910_ONEWIRE 12 -#define IRQ_PXA910_AP1_TIMER1 13 -#define IRQ_PXA910_AP1_TIMER2 14 -#define IRQ_PXA910_AP1_TIMER3 15 -#define IRQ_PXA910_IPC_AP0 16 -#define IRQ_PXA910_IPC_AP1 17 -#define IRQ_PXA910_IPC_AP2 18 -#define IRQ_PXA910_IPC_AP3 19 -#define IRQ_PXA910_IPC_AP4 20 -#define IRQ_PXA910_IPC_CP0 21 -#define IRQ_PXA910_IPC_CP1 22 -#define IRQ_PXA910_IPC_CP2 23 -#define IRQ_PXA910_IPC_CP3 24 -#define IRQ_PXA910_IPC_CP4 25 -#define IRQ_PXA910_L2_DDR 26 -#define IRQ_PXA910_UART2 27 -#define IRQ_PXA910_UART3 28 -#define IRQ_PXA910_AP2_TIMER1 29 -#define IRQ_PXA910_AP2_TIMER2 30 -#define IRQ_PXA910_CP2_TIMER1 31 -#define IRQ_PXA910_CP2_TIMER2 32 -#define IRQ_PXA910_CP2_TIMER3 33 -#define IRQ_PXA910_GSSP 34 -#define IRQ_PXA910_CP2_WDT 35 -#define IRQ_PXA910_MAIN_PMU 36 -#define IRQ_PXA910_CP_FREQ_CHG 37 -#define IRQ_PXA910_AP_FREQ_CHG 38 -#define IRQ_PXA910_MMC 39 -#define IRQ_PXA910_AEU 40 -#define IRQ_PXA910_LCD 41 -#define IRQ_PXA910_CCIC 42 -#define IRQ_PXA910_IRE 43 -#define IRQ_PXA910_USB1 44 -#define IRQ_PXA910_NAND 45 -#define IRQ_PXA910_HIFI_DMA 46 -#define IRQ_PXA910_DMA_INT0 47 -#define IRQ_PXA910_DMA_INT1 48 -#define IRQ_PXA910_AP_GPIO 49 -#define IRQ_PXA910_AP2_TIMER3 50 -#define IRQ_PXA910_USB2 51 -#define IRQ_PXA910_TWSI1 54 -#define IRQ_PXA910_CP_GPIO 55 -#define IRQ_PXA910_UART1 59 /* Slow UART */ -#define IRQ_PXA910_AP_PMU 60 -#define IRQ_PXA910_SM_INT 63 /* from PinMux */ - -/* - * Interrupt numbers for MMP2 - */ -#define IRQ_MMP2_NONE (-1) -#define IRQ_MMP2_SSP1 0 -#define IRQ_MMP2_SSP2 1 -#define IRQ_MMP2_SSPA1 2 -#define IRQ_MMP2_SSPA2 3 -#define IRQ_MMP2_PMIC_MUX 4 /* PMIC & Charger */ -#define IRQ_MMP2_RTC_MUX 5 -#define IRQ_MMP2_TWSI1 7 -#define IRQ_MMP2_GPU 8 -#define IRQ_MMP2_KEYPAD_MUX 9 -#define IRQ_MMP2_ROTARY 10 -#define IRQ_MMP2_TRACKBALL 11 -#define IRQ_MMP2_ONEWIRE 12 -#define IRQ_MMP2_TIMER1 13 -#define IRQ_MMP2_TIMER2 14 -#define IRQ_MMP2_TIMER3 15 -#define IRQ_MMP2_RIPC 16 -#define IRQ_MMP2_TWSI_MUX 17 /* TWSI2 ~ TWSI6 */ -#define IRQ_MMP2_HDMI 19 -#define IRQ_MMP2_SSP3 20 -#define IRQ_MMP2_SSP4 21 -#define IRQ_MMP2_USB_HS1 22 -#define IRQ_MMP2_USB_HS2 23 -#define IRQ_MMP2_UART3 24 -#define IRQ_MMP2_UART1 27 -#define IRQ_MMP2_UART2 28 -#define IRQ_MMP2_MIPI_DSI 29 -#define IRQ_MMP2_CI2 30 -#define IRQ_MMP2_PMU_TIMER1 31 -#define IRQ_MMP2_PMU_TIMER2 32 -#define IRQ_MMP2_PMU_TIMER3 33 -#define IRQ_MMP2_USB_FS 34 -#define IRQ_MMP2_MISC_MUX 35 -#define IRQ_MMP2_WDT1 36 -#define IRQ_MMP2_NAND_DMA 37 -#define IRQ_MMP2_USIM 38 -#define IRQ_MMP2_MMC 39 -#define IRQ_MMP2_WTM 40 -#define IRQ_MMP2_LCD 41 -#define IRQ_MMP2_CI 42 -#define IRQ_MMP2_IRE 43 -#define IRQ_MMP2_USB_OTG 44 -#define IRQ_MMP2_NAND 45 -#define IRQ_MMP2_UART4 46 -#define IRQ_MMP2_DMA_FIQ 47 -#define IRQ_MMP2_DMA_RIQ 48 -#define IRQ_MMP2_GPIO 49 -#define IRQ_MMP2_MIPI_HSI1_MUX 51 -#define IRQ_MMP2_MMC2 52 -#define IRQ_MMP2_MMC3 53 -#define IRQ_MMP2_MMC4 54 -#define IRQ_MMP2_MIPI_HSI0_MUX 55 -#define IRQ_MMP2_MSP 58 -#define IRQ_MMP2_MIPI_SLIM_DMA 59 -#define IRQ_MMP2_PJ4_FREQ_CHG 60 -#define IRQ_MMP2_MIPI_SLIM 62 -#define IRQ_MMP2_SM 63 - -#define IRQ_MMP2_MUX_BASE 64 - -/* secondary interrupt of INT #4 */ -#define IRQ_MMP2_PMIC_BASE (IRQ_MMP2_MUX_BASE) -#define IRQ_MMP2_CHARGER (IRQ_MMP2_PMIC_BASE + 0) -#define IRQ_MMP2_PMIC (IRQ_MMP2_PMIC_BASE + 1) - -/* secondary interrupt of INT #5 */ -#define IRQ_MMP2_RTC_BASE (IRQ_MMP2_PMIC_BASE + 2) -#define IRQ_MMP2_RTC_ALARM (IRQ_MMP2_RTC_BASE + 0) -#define IRQ_MMP2_RTC (IRQ_MMP2_RTC_BASE + 1) - -/* secondary interrupt of INT #9 */ -#define IRQ_MMP2_KEYPAD_BASE (IRQ_MMP2_RTC_BASE + 2) -#define IRQ_MMP2_KPC (IRQ_MMP2_KEYPAD_BASE + 0) -#define IRQ_MMP2_ROTORY (IRQ_MMP2_KEYPAD_BASE + 1) -#define IRQ_MMP2_TBALL (IRQ_MMP2_KEYPAD_BASE + 2) - -/* secondary interrupt of INT #17 */ -#define IRQ_MMP2_TWSI_BASE (IRQ_MMP2_KEYPAD_BASE + 3) -#define IRQ_MMP2_TWSI2 (IRQ_MMP2_TWSI_BASE + 0) -#define IRQ_MMP2_TWSI3 (IRQ_MMP2_TWSI_BASE + 1) -#define IRQ_MMP2_TWSI4 (IRQ_MMP2_TWSI_BASE + 2) -#define IRQ_MMP2_TWSI5 (IRQ_MMP2_TWSI_BASE + 3) -#define IRQ_MMP2_TWSI6 (IRQ_MMP2_TWSI_BASE + 4) - -/* secondary interrupt of INT #35 */ -#define IRQ_MMP2_MISC_BASE (IRQ_MMP2_TWSI_BASE + 5) -#define IRQ_MMP2_PERF (IRQ_MMP2_MISC_BASE + 0) -#define IRQ_MMP2_L2_PA_ECC (IRQ_MMP2_MISC_BASE + 1) -#define IRQ_MMP2_L2_ECC (IRQ_MMP2_MISC_BASE + 2) -#define IRQ_MMP2_L2_UECC (IRQ_MMP2_MISC_BASE + 3) -#define IRQ_MMP2_DDR (IRQ_MMP2_MISC_BASE + 4) -#define IRQ_MMP2_FAB0_TIMEOUT (IRQ_MMP2_MISC_BASE + 5) -#define IRQ_MMP2_FAB1_TIMEOUT (IRQ_MMP2_MISC_BASE + 6) -#define IRQ_MMP2_FAB2_TIMEOUT (IRQ_MMP2_MISC_BASE + 7) -#define IRQ_MMP2_THERMAL (IRQ_MMP2_MISC_BASE + 9) -#define IRQ_MMP2_MAIN_PMU (IRQ_MMP2_MISC_BASE + 10) -#define IRQ_MMP2_WDT2 (IRQ_MMP2_MISC_BASE + 11) -#define IRQ_MMP2_CORESIGHT (IRQ_MMP2_MISC_BASE + 12) -#define IRQ_MMP2_COMMTX (IRQ_MMP2_MISC_BASE + 13) -#define IRQ_MMP2_COMMRX (IRQ_MMP2_MISC_BASE + 14) - -/* secondary interrupt of INT #51 */ -#define IRQ_MMP2_MIPI_HSI1_BASE (IRQ_MMP2_MISC_BASE + 15) -#define IRQ_MMP2_HSI1_CAWAKE (IRQ_MMP2_MIPI_HSI1_BASE + 0) -#define IRQ_MMP2_MIPI_HSI_INT1 (IRQ_MMP2_MIPI_HSI1_BASE + 1) - -/* secondary interrupt of INT #55 */ -#define IRQ_MMP2_MIPI_HSI0_BASE (IRQ_MMP2_MIPI_HSI1_BASE + 2) -#define IRQ_MMP2_HSI0_CAWAKE (IRQ_MMP2_MIPI_HSI0_BASE + 0) -#define IRQ_MMP2_MIPI_HSI_INT0 (IRQ_MMP2_MIPI_HSI0_BASE + 1) - -#define IRQ_MMP2_MUX_END (IRQ_MMP2_MIPI_HSI0_BASE + 2) - -#define IRQ_GPIO_START 128 -#define MMP_NR_BUILTIN_GPIO 192 -#define MMP_GPIO_TO_IRQ(gpio) (IRQ_GPIO_START + (gpio)) - -#define IRQ_BOARD_START (IRQ_GPIO_START + MMP_NR_BUILTIN_GPIO) -#define MMP_NR_IRQS IRQ_BOARD_START - -#endif /* __ASM_MACH_IRQS_H */ diff --git a/arch/arm/mach-mmp/jasper.c b/arch/arm/mach-mmp/jasper.c deleted file mode 100644 index 2578e176fd48..000000000000 --- a/arch/arm/mach-mmp/jasper.c +++ /dev/null @@ -1,185 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-mmp/jasper.c - * - * Support for the Marvell Jasper Development Platform. - * - * Copyright (C) 2009-2010 Marvell International Ltd. - */ - -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/gpio-pxa.h> -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/regulator/machine.h> -#include <linux/regulator/max8649.h> -#include <linux/mfd/max8925.h> -#include <linux/interrupt.h> - -#include "irqs.h" -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include "addr-map.h" -#include "mfp-mmp2.h" -#include "mmp2.h" - -#include "common.h" - -#define JASPER_NR_IRQS (MMP_NR_IRQS + 48) - -static unsigned long jasper_pin_config[] __initdata = { - /* UART1 */ - GPIO29_UART1_RXD, - GPIO30_UART1_TXD, - - /* UART3 */ - GPIO51_UART3_RXD, - GPIO52_UART3_TXD, - - /* DFI */ - GPIO168_DFI_D0, - GPIO167_DFI_D1, - GPIO166_DFI_D2, - GPIO165_DFI_D3, - GPIO107_DFI_D4, - GPIO106_DFI_D5, - GPIO105_DFI_D6, - GPIO104_DFI_D7, - GPIO111_DFI_D8, - GPIO164_DFI_D9, - GPIO163_DFI_D10, - GPIO162_DFI_D11, - GPIO161_DFI_D12, - GPIO110_DFI_D13, - GPIO109_DFI_D14, - GPIO108_DFI_D15, - GPIO143_ND_nCS0, - GPIO144_ND_nCS1, - GPIO147_ND_nWE, - GPIO148_ND_nRE, - GPIO150_ND_ALE, - GPIO149_ND_CLE, - GPIO112_ND_RDY0, - GPIO160_ND_RDY1, - - /* PMIC */ - PMIC_PMIC_INT | MFP_LPM_EDGE_FALL, - - /* MMC1 */ - GPIO131_MMC1_DAT3, - GPIO132_MMC1_DAT2, - GPIO133_MMC1_DAT1, - GPIO134_MMC1_DAT0, - GPIO136_MMC1_CMD, - GPIO139_MMC1_CLK, - GPIO140_MMC1_CD, - GPIO141_MMC1_WP, - - /* MMC2 */ - GPIO37_MMC2_DAT3, - GPIO38_MMC2_DAT2, - GPIO39_MMC2_DAT1, - GPIO40_MMC2_DAT0, - GPIO41_MMC2_CMD, - GPIO42_MMC2_CLK, - - /* MMC3 */ - GPIO165_MMC3_DAT7, - GPIO162_MMC3_DAT6, - GPIO166_MMC3_DAT5, - GPIO163_MMC3_DAT4, - GPIO167_MMC3_DAT3, - GPIO164_MMC3_DAT2, - GPIO168_MMC3_DAT1, - GPIO111_MMC3_DAT0, - GPIO112_MMC3_CMD, - GPIO151_MMC3_CLK, -}; - -static struct pxa_gpio_platform_data mmp2_gpio_pdata = { - .irq_base = MMP_GPIO_TO_IRQ(0), -}; - -static struct regulator_consumer_supply max8649_supply[] = { - REGULATOR_SUPPLY("vcc_core", NULL), -}; - -static struct regulator_init_data max8649_init_data = { - .constraints = { - .name = "vcc_core range", - .min_uV = 1150000, - .max_uV = 1280000, - .always_on = 1, - .boot_on = 1, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - }, - .num_consumer_supplies = 1, - .consumer_supplies = &max8649_supply[0], -}; - -static struct max8649_platform_data jasper_max8649_info = { - .mode = 2, /* VID1 = 1, VID0 = 0 */ - .extclk = 0, - .ramp_timing = MAX8649_RAMP_32MV, - .regulator = &max8649_init_data, -}; - -static struct max8925_backlight_pdata jasper_backlight_data = { - .dual_string = 0, -}; - -static struct max8925_power_pdata jasper_power_data = { - .batt_detect = 0, /* can't detect battery by ID pin */ - .topoff_threshold = MAX8925_TOPOFF_THR_10PER, - .fast_charge = MAX8925_FCHG_1000MA, -}; - -static struct max8925_platform_data jasper_max8925_info = { - .backlight = &jasper_backlight_data, - .power = &jasper_power_data, - .irq_base = MMP_NR_IRQS, -}; - -static struct i2c_board_info jasper_twsi1_info[] = { - [0] = { - .type = "max8649", - .addr = 0x60, - .platform_data = &jasper_max8649_info, - }, - [1] = { - .type = "max8925", - .addr = 0x3c, - .irq = IRQ_MMP2_PMIC, - .platform_data = &jasper_max8925_info, - }, -}; - -static struct sdhci_pxa_platdata mmp2_sdh_platdata_mmc0 = { - .clk_delay_cycles = 0x1f, -}; - -static void __init jasper_init(void) -{ - mfp_config(ARRAY_AND_SIZE(jasper_pin_config)); - - /* on-chip devices */ - mmp2_add_uart(1); - mmp2_add_uart(3); - mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(jasper_twsi1_info)); - platform_device_add_data(&mmp2_device_gpio, &mmp2_gpio_pdata, - sizeof(struct pxa_gpio_platform_data)); - platform_device_register(&mmp2_device_gpio); - mmp2_add_sdhost(0, &mmp2_sdh_platdata_mmc0); /* SD/MMC */ - - regulator_has_full_constraints(); -} - -MACHINE_START(MARVELL_JASPER, "Jasper Development Platform") - .map_io = mmp_map_io, - .nr_irqs = JASPER_NR_IRQS, - .init_irq = mmp2_init_irq, - .init_time = mmp2_timer_init, - .init_machine = jasper_init, - .restart = mmp_restart, -MACHINE_END diff --git a/arch/arm/mach-mmp/mfp-mmp2.h b/arch/arm/mach-mmp/mfp-mmp2.h deleted file mode 100644 index 1620222981e3..000000000000 --- a/arch/arm/mach-mmp/mfp-mmp2.h +++ /dev/null @@ -1,396 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_MACH_MFP_MMP2_H -#define __ASM_MACH_MFP_MMP2_H - -#include "mfp.h" - -#define MFP_DRIVE_VERY_SLOW (0x0 << 13) -#define MFP_DRIVE_SLOW (0x2 << 13) -#define MFP_DRIVE_MEDIUM (0x4 << 13) -#define MFP_DRIVE_FAST (0x6 << 13) - -/* GPIO */ -#define GPIO0_GPIO MFP_CFG(GPIO0, AF0) -#define GPIO1_GPIO MFP_CFG(GPIO1, AF0) -#define GPIO2_GPIO MFP_CFG(GPIO2, AF0) -#define GPIO3_GPIO MFP_CFG(GPIO3, AF0) -#define GPIO4_GPIO MFP_CFG(GPIO4, AF0) -#define GPIO5_GPIO MFP_CFG(GPIO5, AF0) -#define GPIO6_GPIO MFP_CFG(GPIO6, AF0) -#define GPIO7_GPIO MFP_CFG(GPIO7, AF0) -#define GPIO8_GPIO MFP_CFG(GPIO8, AF0) -#define GPIO9_GPIO MFP_CFG(GPIO9, AF0) -#define GPIO10_GPIO MFP_CFG(GPIO10, AF0) -#define GPIO11_GPIO MFP_CFG(GPIO11, AF0) -#define GPIO12_GPIO MFP_CFG(GPIO12, AF0) -#define GPIO13_GPIO MFP_CFG(GPIO13, AF0) -#define GPIO14_GPIO MFP_CFG(GPIO14, AF0) -#define GPIO15_GPIO MFP_CFG(GPIO15, AF0) -#define GPIO16_GPIO MFP_CFG(GPIO16, AF0) -#define GPIO17_GPIO MFP_CFG(GPIO17, AF0) -#define GPIO18_GPIO MFP_CFG(GPIO18, AF0) -#define GPIO19_GPIO MFP_CFG(GPIO19, AF0) -#define GPIO20_GPIO MFP_CFG(GPIO20, AF0) -#define GPIO21_GPIO MFP_CFG(GPIO21, AF0) -#define GPIO22_GPIO MFP_CFG(GPIO22, AF0) -#define GPIO23_GPIO MFP_CFG(GPIO23, AF0) -#define GPIO24_GPIO MFP_CFG(GPIO24, AF0) -#define GPIO25_GPIO MFP_CFG(GPIO25, AF0) -#define GPIO26_GPIO MFP_CFG(GPIO26, AF0) -#define GPIO27_GPIO MFP_CFG(GPIO27, AF0) -#define GPIO28_GPIO MFP_CFG(GPIO28, AF0) -#define GPIO29_GPIO MFP_CFG(GPIO29, AF0) -#define GPIO30_GPIO MFP_CFG(GPIO30, AF0) -#define GPIO31_GPIO MFP_CFG(GPIO31, AF0) -#define GPIO32_GPIO MFP_CFG(GPIO32, AF0) -#define GPIO33_GPIO MFP_CFG(GPIO33, AF0) -#define GPIO34_GPIO MFP_CFG(GPIO34, AF0) -#define GPIO35_GPIO MFP_CFG(GPIO35, AF0) -#define GPIO36_GPIO MFP_CFG(GPIO36, AF0) -#define GPIO37_GPIO MFP_CFG(GPIO37, AF0) -#define GPIO38_GPIO MFP_CFG(GPIO38, AF0) -#define GPIO39_GPIO MFP_CFG(GPIO39, AF0) -#define GPIO40_GPIO MFP_CFG(GPIO40, AF0) -#define GPIO41_GPIO MFP_CFG(GPIO41, AF0) -#define GPIO42_GPIO MFP_CFG(GPIO42, AF0) -#define GPIO43_GPIO MFP_CFG(GPIO43, AF0) -#define GPIO44_GPIO MFP_CFG(GPIO44, AF0) -#define GPIO45_GPIO MFP_CFG(GPIO45, AF0) -#define GPIO46_GPIO MFP_CFG(GPIO46, AF0) -#define GPIO47_GPIO MFP_CFG(GPIO47, AF0) -#define GPIO48_GPIO MFP_CFG(GPIO48, AF0) -#define GPIO49_GPIO MFP_CFG(GPIO49, AF0) -#define GPIO50_GPIO MFP_CFG(GPIO50, AF0) -#define GPIO51_GPIO MFP_CFG(GPIO51, AF0) -#define GPIO52_GPIO MFP_CFG(GPIO52, AF0) -#define GPIO53_GPIO MFP_CFG(GPIO53, AF0) -#define GPIO54_GPIO MFP_CFG(GPIO54, AF0) -#define GPIO55_GPIO MFP_CFG(GPIO55, AF0) -#define GPIO56_GPIO MFP_CFG(GPIO56, AF0) -#define GPIO57_GPIO MFP_CFG(GPIO57, AF0) -#define GPIO58_GPIO MFP_CFG(GPIO58, AF0) -#define GPIO59_GPIO MFP_CFG(GPIO59, AF0) -#define GPIO60_GPIO MFP_CFG(GPIO60, AF0) -#define GPIO61_GPIO MFP_CFG(GPIO61, AF0) -#define GPIO62_GPIO MFP_CFG(GPIO62, AF0) -#define GPIO63_GPIO MFP_CFG(GPIO63, AF0) -#define GPIO64_GPIO MFP_CFG(GPIO64, AF0) -#define GPIO65_GPIO MFP_CFG(GPIO65, AF0) -#define GPIO66_GPIO MFP_CFG(GPIO66, AF0) -#define GPIO67_GPIO MFP_CFG(GPIO67, AF0) -#define GPIO68_GPIO MFP_CFG(GPIO68, AF0) -#define GPIO69_GPIO MFP_CFG(GPIO69, AF0) -#define GPIO70_GPIO MFP_CFG(GPIO70, AF0) -#define GPIO71_GPIO MFP_CFG(GPIO71, AF0) -#define GPIO72_GPIO MFP_CFG(GPIO72, AF0) -#define GPIO73_GPIO MFP_CFG(GPIO73, AF0) -#define GPIO74_GPIO MFP_CFG(GPIO74, AF0) -#define GPIO75_GPIO MFP_CFG(GPIO75, AF0) -#define GPIO76_GPIO MFP_CFG(GPIO76, AF0) -#define GPIO77_GPIO MFP_CFG(GPIO77, AF0) -#define GPIO78_GPIO MFP_CFG(GPIO78, AF0) -#define GPIO79_GPIO MFP_CFG(GPIO79, AF0) -#define GPIO80_GPIO MFP_CFG(GPIO80, AF0) -#define GPIO81_GPIO MFP_CFG(GPIO81, AF0) -#define GPIO82_GPIO MFP_CFG(GPIO82, AF0) -#define GPIO83_GPIO MFP_CFG(GPIO83, AF0) -#define GPIO84_GPIO MFP_CFG(GPIO84, AF0) -#define GPIO85_GPIO MFP_CFG(GPIO85, AF0) -#define GPIO86_GPIO MFP_CFG(GPIO86, AF0) -#define GPIO87_GPIO MFP_CFG(GPIO87, AF0) -#define GPIO88_GPIO MFP_CFG(GPIO88, AF0) -#define GPIO89_GPIO MFP_CFG(GPIO89, AF0) -#define GPIO90_GPIO MFP_CFG(GPIO90, AF0) -#define GPIO91_GPIO MFP_CFG(GPIO91, AF0) -#define GPIO92_GPIO MFP_CFG(GPIO92, AF0) -#define GPIO93_GPIO MFP_CFG(GPIO93, AF0) -#define GPIO94_GPIO MFP_CFG(GPIO94, AF0) -#define GPIO95_GPIO MFP_CFG(GPIO95, AF0) -#define GPIO96_GPIO MFP_CFG(GPIO96, AF0) -#define GPIO97_GPIO MFP_CFG(GPIO97, AF0) -#define GPIO98_GPIO MFP_CFG(GPIO98, AF0) -#define GPIO99_GPIO MFP_CFG(GPIO99, AF0) -#define GPIO100_GPIO MFP_CFG(GPIO100, AF0) -#define GPIO101_GPIO MFP_CFG(GPIO101, AF0) -#define GPIO102_GPIO MFP_CFG(GPIO102, AF1) -#define GPIO103_GPIO MFP_CFG(GPIO103, AF1) -#define GPIO104_GPIO MFP_CFG(GPIO104, AF1) -#define GPIO105_GPIO MFP_CFG(GPIO105, AF1) -#define GPIO106_GPIO MFP_CFG(GPIO106, AF1) -#define GPIO107_GPIO MFP_CFG(GPIO107, AF1) -#define GPIO108_GPIO MFP_CFG(GPIO108, AF1) -#define GPIO109_GPIO MFP_CFG(GPIO109, AF1) -#define GPIO110_GPIO MFP_CFG(GPIO110, AF1) -#define GPIO111_GPIO MFP_CFG(GPIO111, AF1) -#define GPIO112_GPIO MFP_CFG(GPIO112, AF1) -#define GPIO113_GPIO MFP_CFG(GPIO113, AF1) -#define GPIO114_GPIO MFP_CFG(GPIO114, AF0) -#define GPIO115_GPIO MFP_CFG(GPIO115, AF0) -#define GPIO116_GPIO MFP_CFG(GPIO116, AF0) -#define GPIO117_GPIO MFP_CFG(GPIO117, AF0) -#define GPIO118_GPIO MFP_CFG(GPIO118, AF0) -#define GPIO119_GPIO MFP_CFG(GPIO119, AF0) -#define GPIO120_GPIO MFP_CFG(GPIO120, AF0) -#define GPIO121_GPIO MFP_CFG(GPIO121, AF0) -#define GPIO122_GPIO MFP_CFG(GPIO122, AF0) -#define GPIO123_GPIO MFP_CFG(GPIO123, AF0) -#define GPIO124_GPIO MFP_CFG(GPIO124, AF0) -#define GPIO125_GPIO MFP_CFG(GPIO125, AF0) -#define GPIO126_GPIO MFP_CFG(GPIO126, AF0) -#define GPIO127_GPIO MFP_CFG(GPIO127, AF0) -#define GPIO128_GPIO MFP_CFG(GPIO128, AF0) -#define GPIO129_GPIO MFP_CFG(GPIO129, AF0) -#define GPIO130_GPIO MFP_CFG(GPIO130, AF0) -#define GPIO131_GPIO MFP_CFG(GPIO131, AF0) -#define GPIO132_GPIO MFP_CFG(GPIO132, AF0) -#define GPIO133_GPIO MFP_CFG(GPIO133, AF0) -#define GPIO134_GPIO MFP_CFG(GPIO134, AF0) -#define GPIO135_GPIO MFP_CFG(GPIO135, AF0) -#define GPIO136_GPIO MFP_CFG(GPIO136, AF0) -#define GPIO137_GPIO MFP_CFG(GPIO137, AF0) -#define GPIO138_GPIO MFP_CFG(GPIO138, AF0) -#define GPIO139_GPIO MFP_CFG(GPIO139, AF0) -#define GPIO140_GPIO MFP_CFG(GPIO140, AF0) -#define GPIO141_GPIO MFP_CFG(GPIO141, AF0) -#define GPIO142_GPIO MFP_CFG(GPIO142, AF1) -#define GPIO143_GPIO MFP_CFG(GPIO143, AF1) -#define GPIO144_GPIO MFP_CFG(GPIO144, AF1) -#define GPIO145_GPIO MFP_CFG(GPIO145, AF1) -#define GPIO146_GPIO MFP_CFG(GPIO146, AF1) -#define GPIO147_GPIO MFP_CFG(GPIO147, AF1) -#define GPIO148_GPIO MFP_CFG(GPIO148, AF1) -#define GPIO149_GPIO MFP_CFG(GPIO149, AF1) -#define GPIO150_GPIO MFP_CFG(GPIO150, AF1) -#define GPIO151_GPIO MFP_CFG(GPIO151, AF1) -#define GPIO152_GPIO MFP_CFG(GPIO152, AF1) -#define GPIO153_GPIO MFP_CFG(GPIO153, AF1) -#define GPIO154_GPIO MFP_CFG(GPIO154, AF1) -#define GPIO155_GPIO MFP_CFG(GPIO155, AF1) -#define GPIO156_GPIO MFP_CFG(GPIO156, AF1) -#define GPIO157_GPIO MFP_CFG(GPIO157, AF1) -#define GPIO158_GPIO MFP_CFG(GPIO158, AF1) -#define GPIO159_GPIO MFP_CFG(GPIO159, AF1) -#define GPIO160_GPIO MFP_CFG(GPIO160, AF1) -#define GPIO161_GPIO MFP_CFG(GPIO161, AF1) -#define GPIO162_GPIO MFP_CFG(GPIO162, AF1) -#define GPIO163_GPIO MFP_CFG(GPIO163, AF1) -#define GPIO164_GPIO MFP_CFG(GPIO164, AF1) -#define GPIO165_GPIO MFP_CFG(GPIO165, AF1) -#define GPIO166_GPIO MFP_CFG(GPIO166, AF1) -#define GPIO167_GPIO MFP_CFG(GPIO167, AF1) -#define GPIO168_GPIO MFP_CFG(GPIO168, AF1) - -/* DFI */ -#define GPIO108_DFI_D15 MFP_CFG(GPIO108, AF0) -#define GPIO109_DFI_D14 MFP_CFG(GPIO109, AF0) -#define GPIO110_DFI_D13 MFP_CFG(GPIO110, AF0) -#define GPIO161_DFI_D12 MFP_CFG(GPIO161, AF0) -#define GPIO162_DFI_D11 MFP_CFG(GPIO162, AF0) -#define GPIO163_DFI_D10 MFP_CFG(GPIO163, AF0) -#define GPIO164_DFI_D9 MFP_CFG(GPIO164, AF0) -#define GPIO111_DFI_D8 MFP_CFG(GPIO111, AF0) -#define GPIO104_DFI_D7 MFP_CFG(GPIO104, AF0) -#define GPIO105_DFI_D6 MFP_CFG(GPIO105, AF0) -#define GPIO106_DFI_D5 MFP_CFG(GPIO106, AF0) -#define GPIO107_DFI_D4 MFP_CFG(GPIO107, AF0) -#define GPIO165_DFI_D3 MFP_CFG(GPIO165, AF0) -#define GPIO166_DFI_D2 MFP_CFG(GPIO166, AF0) -#define GPIO167_DFI_D1 MFP_CFG(GPIO167, AF0) -#define GPIO168_DFI_D0 MFP_CFG(GPIO168, AF0) -#define GPIO143_ND_nCS0 MFP_CFG(GPIO143, AF0) -#define GPIO144_ND_nCS1 MFP_CFG(GPIO144, AF0) -#define GPIO147_ND_nWE MFP_CFG(GPIO147, AF0) -#define GPIO148_ND_nRE MFP_CFG(GPIO148, AF0) -#define GPIO150_ND_ALE MFP_CFG(GPIO150, AF0) -#define GPIO149_ND_CLE MFP_CFG(GPIO149, AF0) -#define GPIO112_ND_RDY0 MFP_CFG(GPIO112, AF0) -#define GPIO160_ND_RDY1 MFP_CFG(GPIO160, AF0) - -/* Static Memory Controller */ -#define GPIO145_SMC_nCS0 MFP_CFG(GPIO145, AF0) -#define GPIO146_SMC_nCS1 MFP_CFG(GPIO146, AF0) -#define GPIO152_SMC_BE0 MFP_CFG(GPIO152, AF0) -#define GPIO153_SMC_BE1 MFP_CFG(GPIO153, AF0) -#define GPIO154_SMC_IRQ MFP_CFG(GPIO154, AF0) -#define GPIO113_SMC_RDY MFP_CFG(GPIO113, AF0) -#define GPIO151_SMC_SCLK MFP_CFG(GPIO151, AF0) - -/* Ethernet */ -#define GPIO155_SM_ADVMUX MFP_CFG(GPIO155, AF2) - -/* UART1 */ -#define GPIO45_UART1_RXD MFP_CFG(GPIO45, AF1) -#define GPIO46_UART1_TXD MFP_CFG(GPIO46, AF1) -#define GPIO29_UART1_RXD MFP_CFG(GPIO29, AF1) -#define GPIO30_UART1_TXD MFP_CFG(GPIO30, AF1) -#define GPIO31_UART1_CTS MFP_CFG(GPIO31, AF1) -#define GPIO32_UART1_RTS MFP_CFG(GPIO32, AF1) - -/* UART2 */ -#define GPIO47_UART2_RXD MFP_CFG(GPIO47, AF1) -#define GPIO48_UART2_TXD MFP_CFG(GPIO48, AF1) -#define GPIO49_UART2_CTS MFP_CFG(GPIO49, AF1) -#define GPIO50_UART2_RTS MFP_CFG(GPIO50, AF1) - -/* UART3 */ -#define GPIO51_UART3_RXD MFP_CFG(GPIO51, AF1) -#define GPIO52_UART3_TXD MFP_CFG(GPIO52, AF1) -#define GPIO53_UART3_CTS MFP_CFG(GPIO53, AF1) -#define GPIO54_UART3_RTS MFP_CFG(GPIO54, AF1) - -/* MMC1 */ -#define GPIO124_MMC1_DAT7 MFP_CFG_DRV(GPIO124, AF1, FAST) -#define GPIO125_MMC1_DAT6 MFP_CFG_DRV(GPIO125, AF1, FAST) -#define GPIO129_MMC1_DAT5 MFP_CFG_DRV(GPIO129, AF1, FAST) -#define GPIO130_MMC1_DAT4 MFP_CFG_DRV(GPIO130, AF1, FAST) -#define GPIO131_MMC1_DAT3 MFP_CFG_DRV(GPIO131, AF1, FAST) -#define GPIO132_MMC1_DAT2 MFP_CFG_DRV(GPIO132, AF1, FAST) -#define GPIO133_MMC1_DAT1 MFP_CFG_DRV(GPIO133, AF1, FAST) -#define GPIO134_MMC1_DAT0 MFP_CFG_DRV(GPIO134, AF1, FAST) -#define GPIO136_MMC1_CMD MFP_CFG_DRV(GPIO136, AF1, FAST) -#define GPIO139_MMC1_CLK MFP_CFG_DRV(GPIO139, AF1, FAST) -#define GPIO140_MMC1_CD MFP_CFG_DRV(GPIO140, AF1, FAST) -#define GPIO141_MMC1_WP MFP_CFG_DRV(GPIO141, AF1, FAST) - -/*MMC2*/ -#define GPIO37_MMC2_DAT3 MFP_CFG_DRV(GPIO37, AF1, FAST) -#define GPIO38_MMC2_DAT2 MFP_CFG_DRV(GPIO38, AF1, FAST) -#define GPIO39_MMC2_DAT1 MFP_CFG_DRV(GPIO39, AF1, FAST) -#define GPIO40_MMC2_DAT0 MFP_CFG_DRV(GPIO40, AF1, FAST) -#define GPIO41_MMC2_CMD MFP_CFG_DRV(GPIO41, AF1, FAST) -#define GPIO42_MMC2_CLK MFP_CFG_DRV(GPIO42, AF1, FAST) - -/*MMC3*/ -#define GPIO165_MMC3_DAT7 MFP_CFG_DRV(GPIO165, AF2, FAST) -#define GPIO162_MMC3_DAT6 MFP_CFG_DRV(GPIO162, AF2, FAST) -#define GPIO166_MMC3_DAT5 MFP_CFG_DRV(GPIO166, AF2, FAST) -#define GPIO163_MMC3_DAT4 MFP_CFG_DRV(GPIO163, AF2, FAST) -#define GPIO167_MMC3_DAT3 MFP_CFG_DRV(GPIO167, AF2, FAST) -#define GPIO164_MMC3_DAT2 MFP_CFG_DRV(GPIO164, AF2, FAST) -#define GPIO168_MMC3_DAT1 MFP_CFG_DRV(GPIO168, AF2, FAST) -#define GPIO111_MMC3_DAT0 MFP_CFG_DRV(GPIO111, AF2, FAST) -#define GPIO112_MMC3_CMD MFP_CFG_DRV(GPIO112, AF2, FAST) -#define GPIO151_MMC3_CLK MFP_CFG_DRV(GPIO151, AF2, FAST) - -/* LCD */ -#define GPIO74_LCD_FCLK MFP_CFG_DRV(GPIO74, AF1, FAST) -#define GPIO75_LCD_LCLK MFP_CFG_DRV(GPIO75, AF1, FAST) -#define GPIO76_LCD_PCLK MFP_CFG_DRV(GPIO76, AF1, FAST) -#define GPIO77_LCD_DENA MFP_CFG_DRV(GPIO77, AF1, FAST) -#define GPIO78_LCD_DD0 MFP_CFG_DRV(GPIO78, AF1, FAST) -#define GPIO79_LCD_DD1 MFP_CFG_DRV(GPIO79, AF1, FAST) -#define GPIO80_LCD_DD2 MFP_CFG_DRV(GPIO80, AF1, FAST) -#define GPIO81_LCD_DD3 MFP_CFG_DRV(GPIO81, AF1, FAST) -#define GPIO82_LCD_DD4 MFP_CFG_DRV(GPIO82, AF1, FAST) -#define GPIO83_LCD_DD5 MFP_CFG_DRV(GPIO83, AF1, FAST) -#define GPIO84_LCD_DD6 MFP_CFG_DRV(GPIO84, AF1, FAST) -#define GPIO85_LCD_DD7 MFP_CFG_DRV(GPIO85, AF1, FAST) -#define GPIO86_LCD_DD8 MFP_CFG_DRV(GPIO86, AF1, FAST) -#define GPIO87_LCD_DD9 MFP_CFG_DRV(GPIO87, AF1, FAST) -#define GPIO88_LCD_DD10 MFP_CFG_DRV(GPIO88, AF1, FAST) -#define GPIO89_LCD_DD11 MFP_CFG_DRV(GPIO89, AF1, FAST) -#define GPIO90_LCD_DD12 MFP_CFG_DRV(GPIO90, AF1, FAST) -#define GPIO91_LCD_DD13 MFP_CFG_DRV(GPIO91, AF1, FAST) -#define GPIO92_LCD_DD14 MFP_CFG_DRV(GPIO92, AF1, FAST) -#define GPIO93_LCD_DD15 MFP_CFG_DRV(GPIO93, AF1, FAST) -#define GPIO94_LCD_DD16 MFP_CFG_DRV(GPIO94, AF1, FAST) -#define GPIO95_LCD_DD17 MFP_CFG_DRV(GPIO95, AF1, FAST) -#define GPIO96_LCD_DD18 MFP_CFG_DRV(GPIO96, AF1, FAST) -#define GPIO97_LCD_DD19 MFP_CFG_DRV(GPIO97, AF1, FAST) -#define GPIO98_LCD_DD20 MFP_CFG_DRV(GPIO98, AF1, FAST) -#define GPIO99_LCD_DD21 MFP_CFG_DRV(GPIO99, AF1, FAST) -#define GPIO100_LCD_DD22 MFP_CFG_DRV(GPIO100, AF1, FAST) -#define GPIO101_LCD_DD23 MFP_CFG_DRV(GPIO101, AF1, FAST) -#define GPIO94_SPI_DCLK MFP_CFG_DRV(GPIO94, AF3, FAST) -#define GPIO95_SPI_CS0 MFP_CFG_DRV(GPIO95, AF3, FAST) -#define GPIO96_SPI_DIN MFP_CFG_DRV(GPIO96, AF3, FAST) -#define GPIO97_SPI_DOUT MFP_CFG_DRV(GPIO97, AF3, FAST) -#define GPIO98_LCD_RST MFP_CFG_DRV(GPIO98, AF0, FAST) - -#define GPIO114_MN_CLK_OUT MFP_CFG_DRV(GPIO114, AF1, FAST) - -/*LCD TV path*/ -#define GPIO124_LCD_DD24 MFP_CFG_DRV(GPIO124, AF2, FAST) -#define GPIO125_LCD_DD25 MFP_CFG_DRV(GPIO125, AF2, FAST) -#define GPIO126_LCD_DD33 MFP_CFG_DRV(GPIO126, AF2, FAST) -#define GPIO127_LCD_DD26 MFP_CFG_DRV(GPIO127, AF2, FAST) -#define GPIO128_LCD_DD27 MFP_CFG_DRV(GPIO128, AF2, FAST) -#define GPIO129_LCD_DD28 MFP_CFG_DRV(GPIO129, AF2, FAST) -#define GPIO130_LCD_DD29 MFP_CFG_DRV(GPIO130, AF2, FAST) -#define GPIO135_LCD_DD30 MFP_CFG_DRV(GPIO135, AF2, FAST) -#define GPIO137_LCD_DD31 MFP_CFG_DRV(GPIO137, AF2, FAST) -#define GPIO138_LCD_DD32 MFP_CFG_DRV(GPIO138, AF2, FAST) -#define GPIO140_LCD_DD34 MFP_CFG_DRV(GPIO140, AF2, FAST) -#define GPIO141_LCD_DD35 MFP_CFG_DRV(GPIO141, AF2, FAST) - -/* I2C */ -#define GPIO43_TWSI2_SCL MFP_CFG_DRV(GPIO43, AF1, SLOW) -#define GPIO44_TWSI2_SDA MFP_CFG_DRV(GPIO44, AF1, SLOW) -#define GPIO71_TWSI3_SCL MFP_CFG_DRV(GPIO71, AF1, SLOW) -#define GPIO72_TWSI3_SDA MFP_CFG_DRV(GPIO72, AF1, SLOW) -#define TWSI4_SCL MFP_CFG_DRV(TWSI4_SCL, AF0, SLOW) -#define TWSI4_SDA MFP_CFG_DRV(TWSI4_SDA, AF0, SLOW) -#define GPIO99_TWSI5_SCL MFP_CFG_DRV(GPIO99, AF4, SLOW) -#define GPIO100_TWSI5_SDA MFP_CFG_DRV(GPIO100, AF4, SLOW) -#define GPIO97_TWSI6_SCL MFP_CFG_DRV(GPIO97, AF2, SLOW) -#define GPIO98_TWSI6_SDA MFP_CFG_DRV(GPIO98, AF2, SLOW) - -/* SSPA1 */ -#define GPIO24_I2S_SYSCLK MFP_CFG(GPIO24, AF1) -#define GPIO25_I2S_BITCLK MFP_CFG(GPIO25, AF1) -#define GPIO26_I2S_SYNC MFP_CFG(GPIO26, AF1) -#define GPIO27_I2S_DATA_OUT MFP_CFG(GPIO27, AF1) -#define GPIO28_I2S_SDATA_IN MFP_CFG(GPIO28, AF1) -#define GPIO114_I2S_MCLK MFP_CFG(GPIO114, AF1) - -/* SSPA2 */ -#define GPIO33_SSPA2_CLK MFP_CFG(GPIO33, AF1) -#define GPIO34_SSPA2_FRM MFP_CFG(GPIO34, AF1) -#define GPIO35_SSPA2_TXD MFP_CFG(GPIO35, AF1) -#define GPIO36_SSPA2_RXD MFP_CFG(GPIO36, AF1) - -/* Keypad */ -#define GPIO00_KP_MKIN0 MFP_CFG(GPIO0, AF1) -#define GPIO01_KP_MKOUT0 MFP_CFG(GPIO1, AF1) -#define GPIO02_KP_MKIN1 MFP_CFG(GPIO2, AF1) -#define GPIO03_KP_MKOUT1 MFP_CFG(GPIO3, AF1) -#define GPIO04_KP_MKIN2 MFP_CFG(GPIO4, AF1) -#define GPIO05_KP_MKOUT2 MFP_CFG(GPIO5, AF1) -#define GPIO06_KP_MKIN3 MFP_CFG(GPIO6, AF1) -#define GPIO07_KP_MKOUT3 MFP_CFG(GPIO7, AF1) -#define GPIO08_KP_MKIN4 MFP_CFG(GPIO8, AF1) -#define GPIO09_KP_MKOUT4 MFP_CFG(GPIO9, AF1) -#define GPIO10_KP_MKIN5 MFP_CFG(GPIO10, AF1) -#define GPIO11_KP_MKOUT5 MFP_CFG(GPIO11, AF1) -#define GPIO12_KP_MKIN6 MFP_CFG(GPIO12, AF1) -#define GPIO13_KP_MKOUT6 MFP_CFG(GPIO13, AF1) -#define GPIO14_KP_MKIN7 MFP_CFG(GPIO14, AF1) -#define GPIO15_KP_MKOUT7 MFP_CFG(GPIO15, AF1) -#define GPIO16_KP_DKIN0 MFP_CFG(GPIO16, AF1) -#define GPIO17_KP_DKIN1 MFP_CFG(GPIO17, AF1) -#define GPIO18_KP_DKIN2 MFP_CFG(GPIO18, AF1) -#define GPIO19_KP_DKIN3 MFP_CFG(GPIO19, AF1) -#define GPIO20_KP_DKIN4 MFP_CFG(GPIO20, AF1) -#define GPIO21_KP_DKIN5 MFP_CFG(GPIO21, AF1) -#define GPIO22_KP_DKIN6 MFP_CFG(GPIO22, AF1) -#define GPIO23_KP_DKIN7 MFP_CFG(GPIO23, AF1) - -/* CAMERA */ -#define GPIO59_CCIC_IN7 MFP_CFG_DRV(GPIO59, AF1, FAST) -#define GPIO60_CCIC_IN6 MFP_CFG_DRV(GPIO60, AF1, FAST) -#define GPIO61_CCIC_IN5 MFP_CFG_DRV(GPIO61, AF1, FAST) -#define GPIO62_CCIC_IN4 MFP_CFG_DRV(GPIO62, AF1, FAST) -#define GPIO63_CCIC_IN3 MFP_CFG_DRV(GPIO63, AF1, FAST) -#define GPIO64_CCIC_IN2 MFP_CFG_DRV(GPIO64, AF1, FAST) -#define GPIO65_CCIC_IN1 MFP_CFG_DRV(GPIO65, AF1, FAST) -#define GPIO66_CCIC_IN0 MFP_CFG_DRV(GPIO66, AF1, FAST) -#define GPIO67_CAM_HSYNC MFP_CFG_DRV(GPIO67, AF1, FAST) -#define GPIO68_CAM_VSYNC MFP_CFG_DRV(GPIO68, AF1, FAST) -#define GPIO69_CAM_MCLK MFP_CFG_DRV(GPIO69, AF1, FAST) -#define GPIO70_CAM_PCLK MFP_CFG_DRV(GPIO70, AF1, FAST) - -/* PMIC */ -#define PMIC_PMIC_INT MFP_CFG(PMIC_INT, AF0) - -#endif /* __ASM_MACH_MFP_MMP2_H */ - diff --git a/arch/arm/mach-mmp/mfp-pxa168.h b/arch/arm/mach-mmp/mfp-pxa168.h deleted file mode 100644 index 90d16d3419a4..000000000000 --- a/arch/arm/mach-mmp/mfp-pxa168.h +++ /dev/null @@ -1,355 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_MACH_MFP_PXA168_H -#define __ASM_MACH_MFP_PXA168_H - -#include "mfp.h" - -#define MFP_DRIVE_VERY_SLOW (0x0 << 13) -#define MFP_DRIVE_SLOW (0x1 << 13) -#define MFP_DRIVE_MEDIUM (0x2 << 13) -#define MFP_DRIVE_FAST (0x3 << 13) - -#undef MFP_CFG -#undef MFP_CFG_DRV - -#define MFP_CFG(pin, af) \ - (MFP_LPM_INPUT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_MEDIUM) - -#define MFP_CFG_DRV(pin, af, drv) \ - (MFP_LPM_INPUT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_##drv) - -/* GPIO */ -#define GPIO0_GPIO MFP_CFG(GPIO0, AF5) -#define GPIO1_GPIO MFP_CFG(GPIO1, AF5) -#define GPIO2_GPIO MFP_CFG(GPIO2, AF5) -#define GPIO3_GPIO MFP_CFG(GPIO3, AF5) -#define GPIO4_GPIO MFP_CFG(GPIO4, AF5) -#define GPIO5_GPIO MFP_CFG(GPIO5, AF5) -#define GPIO6_GPIO MFP_CFG(GPIO6, AF5) -#define GPIO7_GPIO MFP_CFG(GPIO7, AF5) -#define GPIO8_GPIO MFP_CFG(GPIO8, AF5) -#define GPIO9_GPIO MFP_CFG(GPIO9, AF5) -#define GPIO10_GPIO MFP_CFG(GPIO10, AF5) -#define GPIO11_GPIO MFP_CFG(GPIO11, AF5) -#define GPIO12_GPIO MFP_CFG(GPIO12, AF5) -#define GPIO13_GPIO MFP_CFG(GPIO13, AF5) -#define GPIO14_GPIO MFP_CFG(GPIO14, AF5) -#define GPIO15_GPIO MFP_CFG(GPIO15, AF5) -#define GPIO16_GPIO MFP_CFG(GPIO16, AF0) -#define GPIO17_GPIO MFP_CFG(GPIO17, AF5) -#define GPIO18_GPIO MFP_CFG(GPIO18, AF0) -#define GPIO19_GPIO MFP_CFG(GPIO19, AF5) -#define GPIO20_GPIO MFP_CFG(GPIO20, AF0) -#define GPIO21_GPIO MFP_CFG(GPIO21, AF5) -#define GPIO22_GPIO MFP_CFG(GPIO22, AF5) -#define GPIO23_GPIO MFP_CFG(GPIO23, AF5) -#define GPIO24_GPIO MFP_CFG(GPIO24, AF5) -#define GPIO25_GPIO MFP_CFG(GPIO25, AF5) -#define GPIO26_GPIO MFP_CFG(GPIO26, AF0) -#define GPIO27_GPIO MFP_CFG(GPIO27, AF5) -#define GPIO28_GPIO MFP_CFG(GPIO28, AF5) -#define GPIO29_GPIO MFP_CFG(GPIO29, AF5) -#define GPIO30_GPIO MFP_CFG(GPIO30, AF5) -#define GPIO31_GPIO MFP_CFG(GPIO31, AF5) -#define GPIO32_GPIO MFP_CFG(GPIO32, AF5) -#define GPIO33_GPIO MFP_CFG(GPIO33, AF5) -#define GPIO34_GPIO MFP_CFG(GPIO34, AF0) -#define GPIO35_GPIO MFP_CFG(GPIO35, AF0) -#define GPIO36_GPIO MFP_CFG(GPIO36, AF0) -#define GPIO37_GPIO MFP_CFG(GPIO37, AF0) -#define GPIO38_GPIO MFP_CFG(GPIO38, AF0) -#define GPIO39_GPIO MFP_CFG(GPIO39, AF0) -#define GPIO40_GPIO MFP_CFG(GPIO40, AF0) -#define GPIO41_GPIO MFP_CFG(GPIO41, AF0) -#define GPIO42_GPIO MFP_CFG(GPIO42, AF0) -#define GPIO43_GPIO MFP_CFG(GPIO43, AF0) -#define GPIO44_GPIO MFP_CFG(GPIO44, AF0) -#define GPIO45_GPIO MFP_CFG(GPIO45, AF0) -#define GPIO46_GPIO MFP_CFG(GPIO46, AF0) -#define GPIO47_GPIO MFP_CFG(GPIO47, AF0) -#define GPIO48_GPIO MFP_CFG(GPIO48, AF0) -#define GPIO49_GPIO MFP_CFG(GPIO49, AF0) -#define GPIO50_GPIO MFP_CFG(GPIO50, AF0) -#define GPIO51_GPIO MFP_CFG(GPIO51, AF0) -#define GPIO52_GPIO MFP_CFG(GPIO52, AF0) -#define GPIO53_GPIO MFP_CFG(GPIO53, AF0) -#define GPIO54_GPIO MFP_CFG(GPIO54, AF0) -#define GPIO55_GPIO MFP_CFG(GPIO55, AF0) -#define GPIO56_GPIO MFP_CFG(GPIO56, AF0) -#define GPIO57_GPIO MFP_CFG(GPIO57, AF0) -#define GPIO58_GPIO MFP_CFG(GPIO58, AF0) -#define GPIO59_GPIO MFP_CFG(GPIO59, AF0) -#define GPIO60_GPIO MFP_CFG(GPIO60, AF0) -#define GPIO61_GPIO MFP_CFG(GPIO61, AF0) -#define GPIO62_GPIO MFP_CFG(GPIO62, AF0) -#define GPIO63_GPIO MFP_CFG(GPIO63, AF0) -#define GPIO64_GPIO MFP_CFG(GPIO64, AF0) -#define GPIO65_GPIO MFP_CFG(GPIO65, AF0) -#define GPIO66_GPIO MFP_CFG(GPIO66, AF0) -#define GPIO67_GPIO MFP_CFG(GPIO67, AF0) -#define GPIO68_GPIO MFP_CFG(GPIO68, AF0) -#define GPIO69_GPIO MFP_CFG(GPIO69, AF0) -#define GPIO70_GPIO MFP_CFG(GPIO70, AF0) -#define GPIO71_GPIO MFP_CFG(GPIO71, AF0) -#define GPIO72_GPIO MFP_CFG(GPIO72, AF0) -#define GPIO73_GPIO MFP_CFG(GPIO73, AF0) -#define GPIO74_GPIO MFP_CFG(GPIO74, AF0) -#define GPIO75_GPIO MFP_CFG(GPIO75, AF0) -#define GPIO76_GPIO MFP_CFG(GPIO76, AF0) -#define GPIO77_GPIO MFP_CFG(GPIO77, AF0) -#define GPIO78_GPIO MFP_CFG(GPIO78, AF0) -#define GPIO79_GPIO MFP_CFG(GPIO79, AF0) -#define GPIO80_GPIO MFP_CFG(GPIO80, AF0) -#define GPIO81_GPIO MFP_CFG(GPIO81, AF0) -#define GPIO82_GPIO MFP_CFG(GPIO82, AF0) -#define GPIO83_GPIO MFP_CFG(GPIO83, AF0) -#define GPIO84_GPIO MFP_CFG(GPIO84, AF0) -#define GPIO85_GPIO MFP_CFG(GPIO85, AF0) -#define GPIO86_GPIO MFP_CFG(GPIO86, AF0) -#define GPIO87_GPIO MFP_CFG(GPIO87, AF0) -#define GPIO88_GPIO MFP_CFG(GPIO88, AF0) -#define GPIO89_GPIO MFP_CFG(GPIO89, AF0) -#define GPIO90_GPIO MFP_CFG(GPIO90, AF0) -#define GPIO91_GPIO MFP_CFG(GPIO91, AF0) -#define GPIO92_GPIO MFP_CFG(GPIO92, AF0) -#define GPIO93_GPIO MFP_CFG(GPIO93, AF0) -#define GPIO94_GPIO MFP_CFG(GPIO94, AF0) -#define GPIO95_GPIO MFP_CFG(GPIO95, AF0) -#define GPIO96_GPIO MFP_CFG(GPIO96, AF0) -#define GPIO97_GPIO MFP_CFG(GPIO97, AF0) -#define GPIO98_GPIO MFP_CFG(GPIO98, AF0) -#define GPIO99_GPIO MFP_CFG(GPIO99, AF0) -#define GPIO100_GPIO MFP_CFG(GPIO100, AF0) -#define GPIO101_GPIO MFP_CFG(GPIO101, AF0) -#define GPIO102_GPIO MFP_CFG(GPIO102, AF0) -#define GPIO103_GPIO MFP_CFG(GPIO103, AF0) -#define GPIO104_GPIO MFP_CFG(GPIO104, AF0) -#define GPIO105_GPIO MFP_CFG(GPIO105, AF0) -#define GPIO106_GPIO MFP_CFG(GPIO106, AF0) -#define GPIO107_GPIO MFP_CFG(GPIO107, AF0) -#define GPIO108_GPIO MFP_CFG(GPIO108, AF0) -#define GPIO109_GPIO MFP_CFG(GPIO109, AF0) -#define GPIO110_GPIO MFP_CFG(GPIO110, AF0) -#define GPIO111_GPIO MFP_CFG(GPIO111, AF0) -#define GPIO112_GPIO MFP_CFG(GPIO112, AF0) -#define GPIO113_GPIO MFP_CFG(GPIO113, AF0) -#define GPIO114_GPIO MFP_CFG(GPIO114, AF0) -#define GPIO115_GPIO MFP_CFG(GPIO115, AF0) -#define GPIO116_GPIO MFP_CFG(GPIO116, AF0) -#define GPIO117_GPIO MFP_CFG(GPIO117, AF0) -#define GPIO118_GPIO MFP_CFG(GPIO118, AF0) -#define GPIO119_GPIO MFP_CFG(GPIO119, AF0) -#define GPIO120_GPIO MFP_CFG(GPIO120, AF0) -#define GPIO121_GPIO MFP_CFG(GPIO121, AF0) -#define GPIO122_GPIO MFP_CFG(GPIO122, AF0) - -/* DFI */ -#define GPIO0_DFI_D15 MFP_CFG(GPIO0, AF0) -#define GPIO1_DFI_D14 MFP_CFG(GPIO1, AF0) -#define GPIO2_DFI_D13 MFP_CFG(GPIO2, AF0) -#define GPIO3_DFI_D12 MFP_CFG(GPIO3, AF0) -#define GPIO4_DFI_D11 MFP_CFG(GPIO4, AF0) -#define GPIO5_DFI_D10 MFP_CFG(GPIO5, AF0) -#define GPIO6_DFI_D9 MFP_CFG(GPIO6, AF0) -#define GPIO7_DFI_D8 MFP_CFG(GPIO7, AF0) -#define GPIO8_DFI_D7 MFP_CFG(GPIO8, AF0) -#define GPIO9_DFI_D6 MFP_CFG(GPIO9, AF0) -#define GPIO10_DFI_D5 MFP_CFG(GPIO10, AF0) -#define GPIO11_DFI_D4 MFP_CFG(GPIO11, AF0) -#define GPIO12_DFI_D3 MFP_CFG(GPIO12, AF0) -#define GPIO13_DFI_D2 MFP_CFG(GPIO13, AF0) -#define GPIO14_DFI_D1 MFP_CFG(GPIO14, AF0) -#define GPIO15_DFI_D0 MFP_CFG(GPIO15, AF0) - -#define GPIO30_DFI_ADDR0 MFP_CFG(GPIO30, AF0) -#define GPIO31_DFI_ADDR1 MFP_CFG(GPIO31, AF0) -#define GPIO32_DFI_ADDR2 MFP_CFG(GPIO32, AF0) -#define GPIO33_DFI_ADDR3 MFP_CFG(GPIO33, AF0) - -/* NAND */ -#define GPIO16_ND_nCS0 MFP_CFG(GPIO16, AF1) -#define GPIO17_ND_nWE MFP_CFG(GPIO17, AF0) -#define GPIO21_ND_ALE MFP_CFG(GPIO21, AF0) -#define GPIO22_ND_CLE MFP_CFG(GPIO22, AF0) -#define GPIO24_ND_nRE MFP_CFG(GPIO24, AF0) -#define GPIO26_ND_RnB1 MFP_CFG(GPIO26, AF1) -#define GPIO27_ND_RnB2 MFP_CFG(GPIO27, AF1) - -/* Static Memory Controller */ -#define GPIO18_SMC_nCS0 MFP_CFG(GPIO18, AF3) -#define GPIO18_SMC_nCS1 MFP_CFG(GPIO18, AF2) -#define GPIO16_SMC_nCS0 MFP_CFG(GPIO16, AF2) -#define GPIO16_SMC_nCS1 MFP_CFG(GPIO16, AF3) -#define GPIO19_SMC_nCS0 MFP_CFG(GPIO19, AF0) -#define GPIO20_SMC_nCS1 MFP_CFG(GPIO20, AF2) -#define GPIO23_SMC_nLUA MFP_CFG(GPIO23, AF0) -#define GPIO25_SMC_nLLA MFP_CFG(GPIO25, AF0) -#define GPIO27_SMC_IRQ MFP_CFG(GPIO27, AF0) -#define GPIO28_SMC_RDY MFP_CFG(GPIO28, AF0) -#define GPIO29_SMC_SCLK MFP_CFG(GPIO29, AF0) -#define GPIO34_SMC_nCS1 MFP_CFG(GPIO34, AF2) -#define GPIO35_SMC_BE1 MFP_CFG(GPIO35, AF2) -#define GPIO36_SMC_BE2 MFP_CFG(GPIO36, AF2) - -/* Compact Flash */ -#define GPIO19_CF_nCE1 MFP_CFG(GPIO19, AF3) -#define GPIO20_CF_nCE2 MFP_CFG(GPIO20, AF3) -#define GPIO23_CF_nALE MFP_CFG(GPIO23, AF3) -#define GPIO25_CF_nRESET MFP_CFG(GPIO25, AF3) -#define GPIO28_CF_RDY MFP_CFG(GPIO28, AF3) -#define GPIO29_CF_STSCH MFP_CFG(GPIO29, AF3) -#define GPIO30_CF_nREG MFP_CFG(GPIO30, AF3) -#define GPIO31_CF_nIOIS16 MFP_CFG(GPIO31, AF3) -#define GPIO32_CF_nCD1 MFP_CFG(GPIO32, AF3) -#define GPIO33_CF_nCD2 MFP_CFG(GPIO33, AF3) - -/* UART */ -#define GPIO8_UART3_TXD MFP_CFG(GPIO8, AF2) -#define GPIO9_UART3_RXD MFP_CFG(GPIO9, AF2) -#define GPIO1O_UART3_CTS MFP_CFG(GPIO10, AF2) -#define GPIO11_UART3_RTS MFP_CFG(GPIO11, AF2) -#define GPIO88_UART2_TXD MFP_CFG(GPIO88, AF2) -#define GPIO89_UART2_RXD MFP_CFG(GPIO89, AF2) -#define GPIO107_UART1_TXD MFP_CFG_DRV(GPIO107, AF1, FAST) -#define GPIO107_UART1_RXD MFP_CFG_DRV(GPIO107, AF2, FAST) -#define GPIO108_UART1_RXD MFP_CFG_DRV(GPIO108, AF1, FAST) -#define GPIO108_UART1_TXD MFP_CFG_DRV(GPIO108, AF2, FAST) -#define GPIO109_UART1_CTS MFP_CFG(GPIO109, AF1) -#define GPIO109_UART1_RTS MFP_CFG(GPIO109, AF2) -#define GPIO110_UART1_RTS MFP_CFG(GPIO110, AF1) -#define GPIO110_UART1_CTS MFP_CFG(GPIO110, AF2) -#define GPIO111_UART1_RI MFP_CFG(GPIO111, AF1) -#define GPIO111_UART1_DSR MFP_CFG(GPIO111, AF2) -#define GPIO112_UART1_DTR MFP_CFG(GPIO111, AF1) -#define GPIO112_UART1_DCD MFP_CFG(GPIO112, AF2) - -/* MMC1 */ -#define GPIO37_MMC1_DAT7 MFP_CFG(GPIO37, AF1) -#define GPIO38_MMC1_DAT6 MFP_CFG(GPIO38, AF1) -#define GPIO54_MMC1_DAT5 MFP_CFG(GPIO54, AF1) -#define GPIO48_MMC1_DAT4 MFP_CFG(GPIO48, AF1) -#define GPIO51_MMC1_DAT3 MFP_CFG(GPIO51, AF1) -#define GPIO52_MMC1_DAT2 MFP_CFG(GPIO52, AF1) -#define GPIO40_MMC1_DAT1 MFP_CFG(GPIO40, AF1) -#define GPIO41_MMC1_DAT0 MFP_CFG(GPIO41, AF1) -#define GPIO49_MMC1_CMD MFP_CFG(GPIO49, AF1) -#define GPIO43_MMC1_CLK MFP_CFG(GPIO43, AF1) -#define GPIO53_MMC1_CD MFP_CFG(GPIO53, AF1) -#define GPIO46_MMC1_WP MFP_CFG(GPIO46, AF1) - -/* MMC2 */ -#define GPIO28_MMC2_CMD MFP_CFG_DRV(GPIO28, AF6, FAST) -#define GPIO29_MMC2_CLK MFP_CFG_DRV(GPIO29, AF6, FAST) -#define GPIO30_MMC2_DAT0 MFP_CFG_DRV(GPIO30, AF6, FAST) -#define GPIO31_MMC2_DAT1 MFP_CFG_DRV(GPIO31, AF6, FAST) -#define GPIO32_MMC2_DAT2 MFP_CFG_DRV(GPIO32, AF6, FAST) -#define GPIO33_MMC2_DAT3 MFP_CFG_DRV(GPIO33, AF6, FAST) - -/* MMC4 */ -#define GPIO125_MMC4_DAT3 MFP_CFG_DRV(GPIO125, AF7, FAST) -#define GPIO126_MMC4_DAT2 MFP_CFG_DRV(GPIO126, AF7, FAST) -#define GPIO127_MMC4_DAT1 MFP_CFG_DRV(GPIO127, AF7, FAST) -#define GPIO0_2_MMC4_DAT0 MFP_CFG_DRV(GPIO0_2, AF7, FAST) -#define GPIO1_2_MMC4_CMD MFP_CFG_DRV(GPIO1_2, AF7, FAST) -#define GPIO2_2_MMC4_CLK MFP_CFG_DRV(GPIO2_2, AF7, FAST) - -/* LCD */ -#define GPIO84_LCD_CS MFP_CFG(GPIO84, AF1) -#define GPIO60_LCD_DD0 MFP_CFG(GPIO60, AF1) -#define GPIO61_LCD_DD1 MFP_CFG(GPIO61, AF1) -#define GPIO70_LCD_DD10 MFP_CFG(GPIO70, AF1) -#define GPIO71_LCD_DD11 MFP_CFG(GPIO71, AF1) -#define GPIO72_LCD_DD12 MFP_CFG(GPIO72, AF1) -#define GPIO73_LCD_DD13 MFP_CFG(GPIO73, AF1) -#define GPIO74_LCD_DD14 MFP_CFG(GPIO74, AF1) -#define GPIO75_LCD_DD15 MFP_CFG(GPIO75, AF1) -#define GPIO76_LCD_DD16 MFP_CFG(GPIO76, AF1) -#define GPIO77_LCD_DD17 MFP_CFG(GPIO77, AF1) -#define GPIO78_LCD_DD18 MFP_CFG(GPIO78, AF1) -#define GPIO79_LCD_DD19 MFP_CFG(GPIO79, AF1) -#define GPIO62_LCD_DD2 MFP_CFG(GPIO62, AF1) -#define GPIO80_LCD_DD20 MFP_CFG(GPIO80, AF1) -#define GPIO81_LCD_DD21 MFP_CFG(GPIO81, AF1) -#define GPIO82_LCD_DD22 MFP_CFG(GPIO82, AF1) -#define GPIO83_LCD_DD23 MFP_CFG(GPIO83, AF1) -#define GPIO63_LCD_DD3 MFP_CFG(GPIO63, AF1) -#define GPIO64_LCD_DD4 MFP_CFG(GPIO64, AF1) -#define GPIO65_LCD_DD5 MFP_CFG(GPIO65, AF1) -#define GPIO66_LCD_DD6 MFP_CFG(GPIO66, AF1) -#define GPIO67_LCD_DD7 MFP_CFG(GPIO67, AF1) -#define GPIO68_LCD_DD8 MFP_CFG(GPIO68, AF1) -#define GPIO69_LCD_DD9 MFP_CFG(GPIO69, AF1) -#define GPIO59_LCD_DENA_BIAS MFP_CFG(GPIO59, AF1) -#define GPIO56_LCD_FCLK_RD MFP_CFG(GPIO56, AF1) -#define GPIO57_LCD_LCLK_A0 MFP_CFG(GPIO57, AF1) -#define GPIO58_LCD_PCLK_WR MFP_CFG(GPIO58, AF1) -#define GPIO85_LCD_VSYNC MFP_CFG(GPIO85, AF1) - -/* I2C */ -#define GPIO105_CI2C_SDA MFP_CFG(GPIO105, AF1) -#define GPIO106_CI2C_SCL MFP_CFG(GPIO106, AF1) - -/* I2S */ -#define GPIO113_I2S_MCLK MFP_CFG(GPIO113, AF6) -#define GPIO114_I2S_FRM MFP_CFG(GPIO114, AF1) -#define GPIO115_I2S_BCLK MFP_CFG(GPIO115, AF1) -#define GPIO116_I2S_RXD MFP_CFG(GPIO116, AF2) -#define GPIO116_I2S_TXD MFP_CFG(GPIO116, AF1) -#define GPIO117_I2S_TXD MFP_CFG(GPIO117, AF2) - -/* PWM */ -#define GPIO96_PWM3_OUT MFP_CFG(GPIO96, AF1) -#define GPIO97_PWM2_OUT MFP_CFG(GPIO97, AF1) -#define GPIO98_PWM1_OUT MFP_CFG(GPIO98, AF1) -#define GPIO104_PWM4_OUT MFP_CFG(GPIO104, AF1) -#define GPIO106_PWM2_OUT MFP_CFG(GPIO106, AF2) -#define GPIO74_PWM4_OUT MFP_CFG(GPIO74, AF2) -#define GPIO75_PWM3_OUT MFP_CFG(GPIO75, AF2) -#define GPIO76_PWM2_OUT MFP_CFG(GPIO76, AF2) -#define GPIO77_PWM1_OUT MFP_CFG(GPIO77, AF2) -#define GPIO82_PWM4_OUT MFP_CFG(GPIO82, AF2) -#define GPIO83_PWM3_OUT MFP_CFG(GPIO83, AF2) -#define GPIO84_PWM2_OUT MFP_CFG(GPIO84, AF2) -#define GPIO85_PWM1_OUT MFP_CFG(GPIO85, AF2) -#define GPIO84_PWM1_OUT MFP_CFG(GPIO84, AF4) -#define GPIO122_PWM3_OUT MFP_CFG(GPIO122, AF3) -#define GPIO123_PWM1_OUT MFP_CFG(GPIO123, AF1) -#define GPIO124_PWM2_OUT MFP_CFG(GPIO124, AF1) -#define GPIO125_PWM3_OUT MFP_CFG(GPIO125, AF1) -#define GPIO126_PWM4_OUT MFP_CFG(GPIO126, AF1) -#define GPIO86_PWM1_OUT MFP_CFG(GPIO86, AF2) -#define GPIO86_PWM2_OUT MFP_CFG(GPIO86, AF3) - -/* Keypad */ -#define GPIO109_KP_MKIN1 MFP_CFG(GPIO109, AF7) -#define GPIO110_KP_MKIN0 MFP_CFG(GPIO110, AF7) -#define GPIO111_KP_MKOUT7 MFP_CFG(GPIO111, AF7) -#define GPIO112_KP_MKOUT6 MFP_CFG(GPIO112, AF7) -#define GPIO121_KP_MKIN4 MFP_CFG(GPIO121, AF7) - -/* Fast Ethernet */ -#define GPIO86_TX_CLK MFP_CFG(GPIO86, AF5) -#define GPIO87_TX_EN MFP_CFG(GPIO87, AF5) -#define GPIO88_TX_DQ3 MFP_CFG(GPIO88, AF5) -#define GPIO89_TX_DQ2 MFP_CFG(GPIO89, AF5) -#define GPIO90_TX_DQ1 MFP_CFG(GPIO90, AF5) -#define GPIO91_TX_DQ0 MFP_CFG(GPIO91, AF5) -#define GPIO92_MII_CRS MFP_CFG(GPIO92, AF5) -#define GPIO93_MII_COL MFP_CFG(GPIO93, AF5) -#define GPIO94_RX_CLK MFP_CFG(GPIO94, AF5) -#define GPIO95_RX_ER MFP_CFG(GPIO95, AF5) -#define GPIO96_RX_DQ3 MFP_CFG(GPIO96, AF5) -#define GPIO97_RX_DQ2 MFP_CFG(GPIO97, AF5) -#define GPIO98_RX_DQ1 MFP_CFG(GPIO98, AF5) -#define GPIO99_RX_DQ0 MFP_CFG(GPIO99, AF5) -#define GPIO100_MII_MDC MFP_CFG(GPIO100, AF5) -#define GPIO101_MII_MDIO MFP_CFG(GPIO101, AF5) -#define GPIO103_RX_DV MFP_CFG(GPIO103, AF5) - -/* SSP2 */ -#define GPIO107_SSP2_RXD MFP_CFG(GPIO107, AF4) -#define GPIO108_SSP2_TXD MFP_CFG(GPIO108, AF4) -#define GPIO111_SSP2_CLK MFP_CFG(GPIO111, AF4) -#define GPIO112_SSP2_FRM MFP_CFG(GPIO112, AF4) - -#endif /* __ASM_MACH_MFP_PXA168_H */ diff --git a/arch/arm/mach-mmp/mfp-pxa910.h b/arch/arm/mach-mmp/mfp-pxa910.h deleted file mode 100644 index 6f900cade631..000000000000 --- a/arch/arm/mach-mmp/mfp-pxa910.h +++ /dev/null @@ -1,170 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_MACH_MFP_PXA910_H -#define __ASM_MACH_MFP_PXA910_H - -#include "mfp.h" - -#define MFP_DRIVE_VERY_SLOW (0x0 << 13) -#define MFP_DRIVE_SLOW (0x2 << 13) -#define MFP_DRIVE_MEDIUM (0x4 << 13) -#define MFP_DRIVE_FAST (0x6 << 13) - -/* UART2 */ -#define GPIO47_UART2_RXD MFP_CFG(GPIO47, AF6) -#define GPIO48_UART2_TXD MFP_CFG(GPIO48, AF6) - -/* UART3 */ -#define GPIO31_UART3_RXD MFP_CFG(GPIO31, AF4) -#define GPIO32_UART3_TXD MFP_CFG(GPIO32, AF4) - -/*IRDA*/ -#define GPIO51_IRDA_SHDN MFP_CFG(GPIO51, AF0) - -/* SMC */ -#define SM_nCS0_nCS0 MFP_CFG(SM_nCS0, AF0) -#define SM_ADV_SM_ADV MFP_CFG(SM_ADV, AF0) -#define SM_SCLK_SM_SCLK MFP_CFG(SM_SCLK, AF0) -#define SM_BE0_SM_BE0 MFP_CFG(SM_BE0, AF1) -#define SM_BE1_SM_BE1 MFP_CFG(SM_BE1, AF1) - -/* I2C */ -#define GPIO53_CI2C_SCL MFP_CFG(GPIO53, AF2) -#define GPIO54_CI2C_SDA MFP_CFG(GPIO54, AF2) - -/* SSP1 (I2S) */ -#define GPIO24_SSP1_SDATA_IN MFP_CFG_DRV(GPIO24, AF1, MEDIUM) -#define GPIO21_SSP1_BITCLK MFP_CFG_DRV(GPIO21, AF1, MEDIUM) -#define GPIO20_SSP1_SYSCLK MFP_CFG_DRV(GPIO20, AF1, MEDIUM) -#define GPIO22_SSP1_SYNC MFP_CFG_DRV(GPIO22, AF1, MEDIUM) -#define GPIO23_SSP1_DATA_OUT MFP_CFG_DRV(GPIO23, AF1, MEDIUM) -#define GPIO124_MN_CLK_OUT MFP_CFG_DRV(GPIO124, AF1, MEDIUM) -#define GPIO123_CLK_REQ MFP_CFG_DRV(GPIO123, AF0, MEDIUM) - -/* DFI */ -#define DF_IO0_ND_IO0 MFP_CFG(DF_IO0, AF0) -#define DF_IO1_ND_IO1 MFP_CFG(DF_IO1, AF0) -#define DF_IO2_ND_IO2 MFP_CFG(DF_IO2, AF0) -#define DF_IO3_ND_IO3 MFP_CFG(DF_IO3, AF0) -#define DF_IO4_ND_IO4 MFP_CFG(DF_IO4, AF0) -#define DF_IO5_ND_IO5 MFP_CFG(DF_IO5, AF0) -#define DF_IO6_ND_IO6 MFP_CFG(DF_IO6, AF0) -#define DF_IO7_ND_IO7 MFP_CFG(DF_IO7, AF0) -#define DF_IO8_ND_IO8 MFP_CFG(DF_IO8, AF0) -#define DF_IO9_ND_IO9 MFP_CFG(DF_IO9, AF0) -#define DF_IO10_ND_IO10 MFP_CFG(DF_IO10, AF0) -#define DF_IO11_ND_IO11 MFP_CFG(DF_IO11, AF0) -#define DF_IO12_ND_IO12 MFP_CFG(DF_IO12, AF0) -#define DF_IO13_ND_IO13 MFP_CFG(DF_IO13, AF0) -#define DF_IO14_ND_IO14 MFP_CFG(DF_IO14, AF0) -#define DF_IO15_ND_IO15 MFP_CFG(DF_IO15, AF0) -#define DF_nCS0_SM_nCS2_nCS0 MFP_CFG(DF_nCS0_SM_nCS2, AF0) -#define DF_ALE_SM_WEn_ND_ALE MFP_CFG(DF_ALE_SM_WEn, AF1) -#define DF_CLE_SM_OEn_ND_CLE MFP_CFG(DF_CLE_SM_OEn, AF0) -#define DF_WEn_DF_WEn MFP_CFG(DF_WEn, AF1) -#define DF_REn_DF_REn MFP_CFG(DF_REn, AF1) -#define DF_RDY0_DF_RDY0 MFP_CFG(DF_RDY0, AF0) - -/*keypad*/ -#define GPIO00_KP_MKIN0 MFP_CFG(GPIO0, AF1) -#define GPIO01_KP_MKOUT0 MFP_CFG(GPIO1, AF1) -#define GPIO02_KP_MKIN1 MFP_CFG(GPIO2, AF1) -#define GPIO03_KP_MKOUT1 MFP_CFG(GPIO3, AF1) -#define GPIO04_KP_MKIN2 MFP_CFG(GPIO4, AF1) -#define GPIO05_KP_MKOUT2 MFP_CFG(GPIO5, AF1) -#define GPIO06_KP_MKIN3 MFP_CFG(GPIO6, AF1) -#define GPIO07_KP_MKOUT3 MFP_CFG(GPIO7, AF1) -#define GPIO08_KP_MKIN4 MFP_CFG(GPIO8, AF1) -#define GPIO09_KP_MKOUT4 MFP_CFG(GPIO9, AF1) -#define GPIO10_KP_MKIN5 MFP_CFG(GPIO10, AF1) -#define GPIO11_KP_MKOUT5 MFP_CFG(GPIO11, AF1) -#define GPIO12_KP_MKIN6 MFP_CFG(GPIO12, AF1) -#define GPIO13_KP_MKOUT6 MFP_CFG(GPIO13, AF1) -#define GPIO14_KP_MKIN7 MFP_CFG(GPIO14, AF1) -#define GPIO15_KP_MKOUT7 MFP_CFG(GPIO15, AF1) -#define GPIO16_KP_DKIN0 MFP_CFG(GPIO16, AF1) -#define GPIO17_KP_DKIN1 MFP_CFG(GPIO17, AF1) -#define GPIO18_KP_DKIN2 MFP_CFG(GPIO18, AF1) -#define GPIO19_KP_DKIN3 MFP_CFG(GPIO19, AF1) - -/* LCD */ -#define GPIO81_LCD_FCLK MFP_CFG(GPIO81, AF1) -#define GPIO82_LCD_LCLK MFP_CFG(GPIO82, AF1) -#define GPIO83_LCD_PCLK MFP_CFG(GPIO83, AF1) -#define GPIO84_LCD_DENA MFP_CFG(GPIO84, AF1) -#define GPIO85_LCD_DD0 MFP_CFG(GPIO85, AF1) -#define GPIO86_LCD_DD1 MFP_CFG(GPIO86, AF1) -#define GPIO87_LCD_DD2 MFP_CFG(GPIO87, AF1) -#define GPIO88_LCD_DD3 MFP_CFG(GPIO88, AF1) -#define GPIO89_LCD_DD4 MFP_CFG(GPIO89, AF1) -#define GPIO90_LCD_DD5 MFP_CFG(GPIO90, AF1) -#define GPIO91_LCD_DD6 MFP_CFG(GPIO91, AF1) -#define GPIO92_LCD_DD7 MFP_CFG(GPIO92, AF1) -#define GPIO93_LCD_DD8 MFP_CFG(GPIO93, AF1) -#define GPIO94_LCD_DD9 MFP_CFG(GPIO94, AF1) -#define GPIO95_LCD_DD10 MFP_CFG(GPIO95, AF1) -#define GPIO96_LCD_DD11 MFP_CFG(GPIO96, AF1) -#define GPIO97_LCD_DD12 MFP_CFG(GPIO97, AF1) -#define GPIO98_LCD_DD13 MFP_CFG(GPIO98, AF1) -#define GPIO100_LCD_DD14 MFP_CFG(GPIO100, AF1) -#define GPIO101_LCD_DD15 MFP_CFG(GPIO101, AF1) -#define GPIO102_LCD_DD16 MFP_CFG(GPIO102, AF1) -#define GPIO103_LCD_DD17 MFP_CFG(GPIO103, AF1) -#define GPIO104_LCD_DD18 MFP_CFG(GPIO104, AF1) -#define GPIO105_LCD_DD19 MFP_CFG(GPIO105, AF1) -#define GPIO106_LCD_DD20 MFP_CFG(GPIO106, AF1) -#define GPIO107_LCD_DD21 MFP_CFG(GPIO107, AF1) -#define GPIO108_LCD_DD22 MFP_CFG(GPIO108, AF1) -#define GPIO109_LCD_DD23 MFP_CFG(GPIO109, AF1) - -#define GPIO104_LCD_SPIDOUT MFP_CFG(GPIO104, AF3) -#define GPIO105_LCD_SPIDIN MFP_CFG(GPIO105, AF3) -#define GPIO107_LCD_CS1 MFP_CFG(GPIO107, AF3) -#define GPIO108_LCD_DCLK MFP_CFG(GPIO108, AF3) - -#define GPIO106_LCD_RESET MFP_CFG(GPIO106, AF0) - -/*smart panel*/ -#define GPIO82_LCD_A0 MFP_CFG(GPIO82, AF0) -#define GPIO83_LCD_WR MFP_CFG(GPIO83, AF0) -#define GPIO103_LCD_CS MFP_CFG(GPIO103, AF0) - -/*1wire*/ -#define GPIO106_1WIRE MFP_CFG(GPIO106, AF3) - -/*CCIC*/ -#define GPIO67_CCIC_IN7 MFP_CFG_DRV(GPIO67, AF1, MEDIUM) -#define GPIO68_CCIC_IN6 MFP_CFG_DRV(GPIO68, AF1, MEDIUM) -#define GPIO69_CCIC_IN5 MFP_CFG_DRV(GPIO69, AF1, MEDIUM) -#define GPIO70_CCIC_IN4 MFP_CFG_DRV(GPIO70, AF1, MEDIUM) -#define GPIO71_CCIC_IN3 MFP_CFG_DRV(GPIO71, AF1, MEDIUM) -#define GPIO72_CCIC_IN2 MFP_CFG_DRV(GPIO72, AF1, MEDIUM) -#define GPIO73_CCIC_IN1 MFP_CFG_DRV(GPIO73, AF1, MEDIUM) -#define GPIO74_CCIC_IN0 MFP_CFG_DRV(GPIO74, AF1, MEDIUM) -#define GPIO75_CAM_HSYNC MFP_CFG_DRV(GPIO75, AF1, MEDIUM) -#define GPIO76_CAM_VSYNC MFP_CFG_DRV(GPIO76, AF1, MEDIUM) -#define GPIO77_CAM_MCLK MFP_CFG_DRV(GPIO77, AF1, MEDIUM) -#define GPIO78_CAM_PCLK MFP_CFG_DRV(GPIO78, AF1, MEDIUM) - -/* MMC1 */ -#define MMC1_DAT7_MMC1_DAT7 MFP_CFG_DRV(MMC1_DAT7, AF0, MEDIUM) -#define MMC1_DAT6_MMC1_DAT6 MFP_CFG_DRV(MMC1_DAT6, AF0, MEDIUM) -#define MMC1_DAT5_MMC1_DAT5 MFP_CFG_DRV(MMC1_DAT5, AF0, MEDIUM) -#define MMC1_DAT4_MMC1_DAT4 MFP_CFG_DRV(MMC1_DAT4, AF0, MEDIUM) -#define MMC1_DAT3_MMC1_DAT3 MFP_CFG_DRV(MMC1_DAT3, AF0, MEDIUM) -#define MMC1_DAT2_MMC1_DAT2 MFP_CFG_DRV(MMC1_DAT2, AF0, MEDIUM) -#define MMC1_DAT1_MMC1_DAT1 MFP_CFG_DRV(MMC1_DAT1, AF0, MEDIUM) -#define MMC1_DAT0_MMC1_DAT0 MFP_CFG_DRV(MMC1_DAT0, AF0, MEDIUM) -#define MMC1_CMD_MMC1_CMD MFP_CFG_DRV(MMC1_CMD, AF0, MEDIUM) -#define MMC1_CLK_MMC1_CLK MFP_CFG_DRV(MMC1_CLK, AF0, MEDIUM) -#define MMC1_CD_MMC1_CD MFP_CFG_DRV(MMC1_CD, AF0, MEDIUM) -#define MMC1_WP_MMC1_WP MFP_CFG_DRV(MMC1_WP, AF0, MEDIUM) - -/* PWM */ -#define GPIO27_PWM3_AF2 MFP_CFG(GPIO27, AF2) -#define GPIO51_PWM2_OUT MFP_CFG(GPIO51, AF2) -#define GPIO117_PWM1_OUT MFP_CFG(GPIO117, AF2) -#define GPIO118_PWM2_OUT MFP_CFG(GPIO118, AF2) -#define GPIO119_PWM3_OUT MFP_CFG(GPIO119, AF2) -#define GPIO120_PWM4_OUT MFP_CFG(GPIO120, AF2) - -#endif /* __ASM_MACH MFP_PXA910_H */ diff --git a/arch/arm/mach-mmp/mfp.h b/arch/arm/mach-mmp/mfp.h deleted file mode 100644 index 6f3057987756..000000000000 --- a/arch/arm/mach-mmp/mfp.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_MACH_MFP_H -#define __ASM_MACH_MFP_H - -#include <linux/soc/pxa/mfp.h> - -/* - * NOTE: the MFPR register bit definitions on PXA168 processor lines are a - * bit different from those on PXA3xx. Bit [7:10] are now reserved, which - * were SLEEP_OE_N, SLEEP_DATA, SLEEP_SEL and the LSB of DRIVE bits. - * - * To cope with this difference and re-use the pxa3xx mfp code as much as - * possible, we make the following compromise: - * - * 1. SLEEP_OE_N will always be programmed to '1' (by MFP_LPM_FLOAT) - * 2. DRIVE strength definitions redefined to include the reserved bit - * - the reserved bit differs between pxa168 and pxa910, and the - * MFP_DRIVE_* macros are individually defined in mfp-pxa{168,910}.h - * 3. Override MFP_CFG() and MFP_CFG_DRV() - * 4. Drop the use of MFP_CFG_LPM() and MFP_CFG_X() - */ - -#undef MFP_CFG -#undef MFP_CFG_DRV -#undef MFP_CFG_LPM -#undef MFP_CFG_X -#undef MFP_CFG_DEFAULT - -#define MFP_CFG(pin, af) \ - (MFP_LPM_FLOAT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_MEDIUM) - -#define MFP_CFG_DRV(pin, af, drv) \ - (MFP_LPM_FLOAT | MFP_PIN(MFP_PIN_##pin) | MFP_##af | MFP_DRIVE_##drv) - -#endif /* __ASM_MACH_MFP_H */ diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c deleted file mode 100644 index bbc4c2274de3..000000000000 --- a/arch/arm/mach-mmp/mmp2.c +++ /dev/null @@ -1,175 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-mmp/mmp2.c - * - * code name MMP2 - * - * Copyright (C) 2009 Marvell International Ltd. - */ -#include <linux/clk/mmp.h> -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/io.h> -#include <linux/irq.h> -#include <linux/irqchip/mmp.h> -#include <linux/platform_device.h> - -#include <asm/hardware/cache-tauros2.h> - -#include <asm/mach/time.h> -#include "addr-map.h" -#include "regs-apbc.h" -#include <linux/soc/mmp/cputype.h> -#include "irqs.h" -#include "mfp.h" -#include "devices.h" -#include "mmp2.h" -#include "pm-mmp2.h" - -#include "common.h" - -#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) - -static struct mfp_addr_map mmp2_addr_map[] __initdata = { - - MFP_ADDR_X(GPIO0, GPIO58, 0x54), - MFP_ADDR_X(GPIO59, GPIO73, 0x280), - MFP_ADDR_X(GPIO74, GPIO101, 0x170), - - MFP_ADDR(GPIO102, 0x0), - MFP_ADDR(GPIO103, 0x4), - MFP_ADDR(GPIO104, 0x1fc), - MFP_ADDR(GPIO105, 0x1f8), - MFP_ADDR(GPIO106, 0x1f4), - MFP_ADDR(GPIO107, 0x1f0), - MFP_ADDR(GPIO108, 0x21c), - MFP_ADDR(GPIO109, 0x218), - MFP_ADDR(GPIO110, 0x214), - MFP_ADDR(GPIO111, 0x200), - MFP_ADDR(GPIO112, 0x244), - MFP_ADDR(GPIO113, 0x25c), - MFP_ADDR(GPIO114, 0x164), - MFP_ADDR_X(GPIO115, GPIO122, 0x260), - - MFP_ADDR(GPIO123, 0x148), - MFP_ADDR_X(GPIO124, GPIO141, 0xc), - - MFP_ADDR(GPIO142, 0x8), - MFP_ADDR_X(GPIO143, GPIO151, 0x220), - MFP_ADDR_X(GPIO152, GPIO153, 0x248), - MFP_ADDR_X(GPIO154, GPIO155, 0x254), - MFP_ADDR_X(GPIO156, GPIO159, 0x14c), - - MFP_ADDR(GPIO160, 0x250), - MFP_ADDR(GPIO161, 0x210), - MFP_ADDR(GPIO162, 0x20c), - MFP_ADDR(GPIO163, 0x208), - MFP_ADDR(GPIO164, 0x204), - MFP_ADDR(GPIO165, 0x1ec), - MFP_ADDR(GPIO166, 0x1e8), - MFP_ADDR(GPIO167, 0x1e4), - MFP_ADDR(GPIO168, 0x1e0), - - MFP_ADDR_X(TWSI1_SCL, TWSI1_SDA, 0x140), - MFP_ADDR_X(TWSI4_SCL, TWSI4_SDA, 0x2bc), - - MFP_ADDR(PMIC_INT, 0x2c4), - MFP_ADDR(CLK_REQ, 0x160), - - MFP_ADDR_END, -}; - -void mmp2_clear_pmic_int(void) -{ - void __iomem *mfpr_pmic; - unsigned long data; - - mfpr_pmic = APB_VIRT_BASE + 0x1e000 + 0x2c4; - data = __raw_readl(mfpr_pmic); - __raw_writel(data | (1 << 6), mfpr_pmic); - __raw_writel(data, mfpr_pmic); -} - -void __init mmp2_init_irq(void) -{ - mmp2_init_icu(); -#ifdef CONFIG_PM - icu_irq_chip.irq_set_wake = mmp2_set_wake; -#endif -} - -static int __init mmp2_init(void) -{ - if (cpu_is_mmp2()) { -#ifdef CONFIG_CACHE_TAUROS2 - tauros2_init(0); -#endif - mfp_init_base(MFPR_VIRT_BASE); - mfp_init_addr(mmp2_addr_map); - mmp2_clk_init(APB_PHYS_BASE + 0x50000, - AXI_PHYS_BASE + 0x82800, - APB_PHYS_BASE + 0x15000); - } - - return 0; -} -postcore_initcall(mmp2_init); - -#define APBC_TIMERS APBC_REG(0x024) - -void __init mmp2_timer_init(void) -{ - unsigned long clk_rst; - - __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS); - - /* - * enable bus/functional clock, enable 6.5MHz (divider 4), - * release reset - */ - clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1); - __raw_writel(clk_rst, APBC_TIMERS); - - mmp_timer_init(IRQ_MMP2_TIMER1, 6500000); -} - -/* on-chip devices */ -MMP2_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4030000, 0x30, 4, 5); -MMP2_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4017000, 0x30, 20, 21); -MMP2_DEVICE(uart3, "pxa2xx-uart", 2, UART3, 0xd4018000, 0x30, 22, 23); -MMP2_DEVICE(uart4, "pxa2xx-uart", 3, UART4, 0xd4016000, 0x30, 18, 19); -MMP2_DEVICE(twsi1, "pxa2xx-i2c", 0, TWSI1, 0xd4011000, 0x70); -MMP2_DEVICE(twsi2, "pxa2xx-i2c", 1, TWSI2, 0xd4031000, 0x70); -MMP2_DEVICE(twsi3, "pxa2xx-i2c", 2, TWSI3, 0xd4032000, 0x70); -MMP2_DEVICE(twsi4, "pxa2xx-i2c", 3, TWSI4, 0xd4033000, 0x70); -MMP2_DEVICE(twsi5, "pxa2xx-i2c", 4, TWSI5, 0xd4033800, 0x70); -MMP2_DEVICE(twsi6, "pxa2xx-i2c", 5, TWSI6, 0xd4034000, 0x70); -MMP2_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x100, 28, 29); -MMP2_DEVICE(sdh0, "sdhci-pxav3", 0, MMC, 0xd4280000, 0x120); -MMP2_DEVICE(sdh1, "sdhci-pxav3", 1, MMC2, 0xd4280800, 0x120); -MMP2_DEVICE(sdh2, "sdhci-pxav3", 2, MMC3, 0xd4281000, 0x120); -MMP2_DEVICE(sdh3, "sdhci-pxav3", 3, MMC4, 0xd4281800, 0x120); -MMP2_DEVICE(asram, "asram", -1, NONE, 0xe0000000, 0x4000); -/* 0xd1000000 ~ 0xd101ffff is reserved for secure processor */ -MMP2_DEVICE(isram, "isram", -1, NONE, 0xd1020000, 0x18000); - -struct resource mmp2_resource_gpio[] = { - { - .start = 0xd4019000, - .end = 0xd4019fff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_MMP2_GPIO, - .end = IRQ_MMP2_GPIO, - .name = "gpio_mux", - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device mmp2_device_gpio = { - .name = "mmp2-gpio", - .id = -1, - .num_resources = ARRAY_SIZE(mmp2_resource_gpio), - .resource = mmp2_resource_gpio, -}; diff --git a/arch/arm/mach-mmp/mmp2.h b/arch/arm/mach-mmp/mmp2.h deleted file mode 100644 index 7f80b90248fb..000000000000 --- a/arch/arm/mach-mmp/mmp2.h +++ /dev/null @@ -1,104 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_MACH_MMP2_H -#define __ASM_MACH_MMP2_H - -#include <linux/platform_data/pxa_sdhci.h> - -extern void mmp2_timer_init(void); -extern void __init mmp2_init_irq(void); -extern void mmp2_clear_pmic_int(void); - -#include <linux/i2c.h> -#include <linux/platform_data/i2c-pxa.h> -#include <linux/platform_data/dma-mmp_tdma.h> -#include <linux/irqchip/mmp.h> - -#include "devices.h" - -extern struct mmp_device_desc mmp2_device_uart1; -extern struct mmp_device_desc mmp2_device_uart2; -extern struct mmp_device_desc mmp2_device_uart3; -extern struct mmp_device_desc mmp2_device_uart4; -extern struct mmp_device_desc mmp2_device_twsi1; -extern struct mmp_device_desc mmp2_device_twsi2; -extern struct mmp_device_desc mmp2_device_twsi3; -extern struct mmp_device_desc mmp2_device_twsi4; -extern struct mmp_device_desc mmp2_device_twsi5; -extern struct mmp_device_desc mmp2_device_twsi6; -extern struct mmp_device_desc mmp2_device_sdh0; -extern struct mmp_device_desc mmp2_device_sdh1; -extern struct mmp_device_desc mmp2_device_sdh2; -extern struct mmp_device_desc mmp2_device_sdh3; -extern struct mmp_device_desc mmp2_device_asram; -extern struct mmp_device_desc mmp2_device_isram; - -extern struct platform_device mmp2_device_gpio; - -static inline int mmp2_add_uart(int id) -{ - struct mmp_device_desc *d = NULL; - - switch (id) { - case 1: d = &mmp2_device_uart1; break; - case 2: d = &mmp2_device_uart2; break; - case 3: d = &mmp2_device_uart3; break; - case 4: d = &mmp2_device_uart4; break; - default: - return -EINVAL; - } - - return mmp_register_device(d, NULL, 0); -} - -static inline int mmp2_add_twsi(int id, struct i2c_pxa_platform_data *data, - struct i2c_board_info *info, unsigned size) -{ - struct mmp_device_desc *d = NULL; - int ret; - - switch (id) { - case 1: d = &mmp2_device_twsi1; break; - case 2: d = &mmp2_device_twsi2; break; - case 3: d = &mmp2_device_twsi3; break; - case 4: d = &mmp2_device_twsi4; break; - case 5: d = &mmp2_device_twsi5; break; - case 6: d = &mmp2_device_twsi6; break; - default: - return -EINVAL; - } - - ret = i2c_register_board_info(id - 1, info, size); - if (ret) - return ret; - - return mmp_register_device(d, data, sizeof(*data)); -} - -static inline int mmp2_add_sdhost(int id, struct sdhci_pxa_platdata *data) -{ - struct mmp_device_desc *d = NULL; - - switch (id) { - case 0: d = &mmp2_device_sdh0; break; - case 1: d = &mmp2_device_sdh1; break; - case 2: d = &mmp2_device_sdh2; break; - case 3: d = &mmp2_device_sdh3; break; - default: - return -EINVAL; - } - - return mmp_register_device(d, data, sizeof(*data)); -} - -static inline int mmp2_add_asram(struct sram_platdata *data) -{ - return mmp_register_device(&mmp2_device_asram, data, sizeof(*data)); -} - -static inline int mmp2_add_isram(struct sram_platdata *data) -{ - return mmp_register_device(&mmp2_device_isram, data, sizeof(*data)); -} - -#endif /* __ASM_MACH_MMP2_H */ - diff --git a/arch/arm/mach-mmp/pm-mmp2.c b/arch/arm/mach-mmp/pm-mmp2.c deleted file mode 100644 index 7a6f74c32d42..000000000000 --- a/arch/arm/mach-mmp/pm-mmp2.c +++ /dev/null @@ -1,248 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * MMP2 Power Management Routines - * - * (C) Copyright 2012 Marvell International Ltd. - * All Rights Reserved - */ - -#include <linux/kernel.h> -#include <linux/errno.h> -#include <linux/err.h> -#include <linux/time.h> -#include <linux/delay.h> -#include <linux/suspend.h> -#include <linux/irq.h> -#include <linux/io.h> -#include <linux/interrupt.h> -#include <asm/mach-types.h> - -#include <linux/soc/mmp/cputype.h> -#include "addr-map.h" -#include "pm-mmp2.h" -#include "regs-icu.h" -#include "irqs.h" - -int mmp2_set_wake(struct irq_data *d, unsigned int on) -{ - unsigned long data = 0; - int irq = d->irq; - - /* enable wakeup sources */ - switch (irq) { - case IRQ_MMP2_RTC: - case IRQ_MMP2_RTC_ALARM: - data = MPMU_WUCRM_PJ_WAKEUP(4) | MPMU_WUCRM_PJ_RTC_ALARM; - break; - case IRQ_MMP2_PMIC: - data = MPMU_WUCRM_PJ_WAKEUP(7); - break; - case IRQ_MMP2_MMC2: - /* mmc use WAKEUP2, same as GPIO wakeup source */ - data = MPMU_WUCRM_PJ_WAKEUP(2); - break; - } - if (on) { - if (data) { - data |= __raw_readl(MPMU_WUCRM_PJ); - __raw_writel(data, MPMU_WUCRM_PJ); - } - } else { - if (data) { - data = ~data & __raw_readl(MPMU_WUCRM_PJ); - __raw_writel(data, MPMU_WUCRM_PJ); - } - } - return 0; -} - -static void pm_scu_clk_disable(void) -{ - unsigned int val; - - /* close AXI fabric clock gate */ - __raw_writel(0x0, CIU_REG(0x64)); - __raw_writel(0x0, CIU_REG(0x68)); - - /* close MCB master clock gate */ - val = __raw_readl(CIU_REG(0x1c)); - val |= 0xf0; - __raw_writel(val, CIU_REG(0x1c)); - - return ; -} - -static void pm_scu_clk_enable(void) -{ - unsigned int val; - - /* open AXI fabric clock gate */ - __raw_writel(0x03003003, CIU_REG(0x64)); - __raw_writel(0x00303030, CIU_REG(0x68)); - - /* open MCB master clock gate */ - val = __raw_readl(CIU_REG(0x1c)); - val &= ~(0xf0); - __raw_writel(val, CIU_REG(0x1c)); - - return ; -} - -static void pm_mpmu_clk_disable(void) -{ - /* - * disable clocks in MPMU_CGR_PJ register - * except clock for APMU_PLL1, APMU_PLL1_2 and AP_26M - */ - __raw_writel(0x0000a010, MPMU_CGR_PJ); -} - -static void pm_mpmu_clk_enable(void) -{ - unsigned int val; - - __raw_writel(0xdffefffe, MPMU_CGR_PJ); - val = __raw_readl(MPMU_PLL2_CTRL1); - val |= (1 << 29); - __raw_writel(val, MPMU_PLL2_CTRL1); - - return ; -} - -void mmp2_pm_enter_lowpower_mode(int state) -{ - uint32_t idle_cfg, apcr; - - idle_cfg = __raw_readl(APMU_PJ_IDLE_CFG); - apcr = __raw_readl(MPMU_PCR_PJ); - apcr &= ~(MPMU_PCR_PJ_SLPEN | MPMU_PCR_PJ_DDRCORSD | MPMU_PCR_PJ_APBSD - | MPMU_PCR_PJ_AXISD | MPMU_PCR_PJ_VCTCXOSD | (1 << 13)); - idle_cfg &= ~APMU_PJ_IDLE_CFG_PJ_IDLE; - - switch (state) { - case POWER_MODE_SYS_SLEEP: - apcr |= MPMU_PCR_PJ_SLPEN; /* set the SLPEN bit */ - apcr |= MPMU_PCR_PJ_VCTCXOSD; /* set VCTCXOSD */ - fallthrough; - case POWER_MODE_CHIP_SLEEP: - apcr |= MPMU_PCR_PJ_SLPEN; - fallthrough; - case POWER_MODE_APPS_SLEEP: - apcr |= MPMU_PCR_PJ_APBSD; /* set APBSD */ - fallthrough; - case POWER_MODE_APPS_IDLE: - apcr |= MPMU_PCR_PJ_AXISD; /* set AXISDD bit */ - apcr |= MPMU_PCR_PJ_DDRCORSD; /* set DDRCORSD bit */ - idle_cfg |= APMU_PJ_IDLE_CFG_PJ_PWRDWN; /* PJ power down */ - apcr |= MPMU_PCR_PJ_SPSD; - fallthrough; - case POWER_MODE_CORE_EXTIDLE: - idle_cfg |= APMU_PJ_IDLE_CFG_PJ_IDLE; /* set the IDLE bit */ - idle_cfg &= ~APMU_PJ_IDLE_CFG_ISO_MODE_CNTRL_MASK; - idle_cfg |= APMU_PJ_IDLE_CFG_PWR_SW(3) - | APMU_PJ_IDLE_CFG_L2_PWR_SW; - break; - case POWER_MODE_CORE_INTIDLE: - apcr &= ~MPMU_PCR_PJ_SPSD; - break; - } - - /* set reserve bits */ - apcr |= (1 << 30) | (1 << 25); - - /* finally write the registers back */ - __raw_writel(idle_cfg, APMU_PJ_IDLE_CFG); - __raw_writel(apcr, MPMU_PCR_PJ); /* 0xfe086000 */ -} - -static int mmp2_pm_enter(suspend_state_t state) -{ - int temp; - - temp = __raw_readl(MMP2_ICU_INT4_MASK); - if (temp & (1 << 1)) { - printk(KERN_ERR "%s: PMIC interrupt is handling\n", __func__); - return -EAGAIN; - } - - temp = __raw_readl(APMU_SRAM_PWR_DWN); - temp |= ((1 << 19) | (1 << 18)); - __raw_writel(temp, APMU_SRAM_PWR_DWN); - pm_mpmu_clk_disable(); - pm_scu_clk_disable(); - - printk(KERN_INFO "%s: before suspend\n", __func__); - cpu_do_idle(); - printk(KERN_INFO "%s: after suspend\n", __func__); - - pm_mpmu_clk_enable(); /* enable clocks in MPMU */ - pm_scu_clk_enable(); /* enable clocks in SCU */ - - return 0; -} - -/* - * Called after processes are frozen, but before we shut down devices. - */ -static int mmp2_pm_prepare(void) -{ - mmp2_pm_enter_lowpower_mode(POWER_MODE_SYS_SLEEP); - - return 0; -} - -/* - * Called after devices are re-setup, but before processes are thawed. - */ -static void mmp2_pm_finish(void) -{ - mmp2_pm_enter_lowpower_mode(POWER_MODE_CORE_INTIDLE); -} - -static int mmp2_pm_valid(suspend_state_t state) -{ - return ((state == PM_SUSPEND_STANDBY) || (state == PM_SUSPEND_MEM)); -} - -/* - * Set to PM_DISK_FIRMWARE so we can quickly veto suspend-to-disk. - */ -static const struct platform_suspend_ops mmp2_pm_ops = { - .valid = mmp2_pm_valid, - .prepare = mmp2_pm_prepare, - .enter = mmp2_pm_enter, - .finish = mmp2_pm_finish, -}; - -static int __init mmp2_pm_init(void) -{ - uint32_t apcr; - - if (!cpu_is_mmp2()) - return -EIO; - - suspend_set_ops(&mmp2_pm_ops); - - /* - * Set bit 0, Slow clock Select 32K clock input instead of VCXO - * VCXO is chosen by default, which would be disabled in suspend - */ - __raw_writel(0x5, MPMU_SCCR); - - /* - * Clear bit 23 of CIU_CPU_CONF - * direct PJ4 to DDR access through Memory Controller slow queue - * fast queue has issue and cause lcd will flick - */ - __raw_writel(__raw_readl(CIU_REG(0x8)) & ~(0x1 << 23), CIU_REG(0x8)); - - /* Clear default low power control bit */ - apcr = __raw_readl(MPMU_PCR_PJ); - apcr &= ~(MPMU_PCR_PJ_SLPEN | MPMU_PCR_PJ_DDRCORSD - | MPMU_PCR_PJ_APBSD | MPMU_PCR_PJ_AXISD | 1 << 13); - __raw_writel(apcr, MPMU_PCR_PJ); - - return 0; -} - -late_initcall(mmp2_pm_init); diff --git a/arch/arm/mach-mmp/pm-mmp2.h b/arch/arm/mach-mmp/pm-mmp2.h deleted file mode 100644 index 70299a9450d3..000000000000 --- a/arch/arm/mach-mmp/pm-mmp2.h +++ /dev/null @@ -1,59 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * MMP2 Power Management Routines - * - * (C) Copyright 2010 Marvell International Ltd. - * All Rights Reserved - */ - -#ifndef __MMP2_PM_H__ -#define __MMP2_PM_H__ - -#include "addr-map.h" - -#define APMU_PJ_IDLE_CFG APMU_REG(0x018) -#define APMU_PJ_IDLE_CFG_PJ_IDLE (1 << 1) -#define APMU_PJ_IDLE_CFG_PJ_PWRDWN (1 << 5) -#define APMU_PJ_IDLE_CFG_PWR_SW(x) ((x) << 16) -#define APMU_PJ_IDLE_CFG_L2_PWR_SW (1 << 19) -#define APMU_PJ_IDLE_CFG_ISO_MODE_CNTRL_MASK (3 << 28) - -#define APMU_SRAM_PWR_DWN APMU_REG(0x08c) - -#define MPMU_SCCR MPMU_REG(0x038) -#define MPMU_PCR_PJ MPMU_REG(0x1000) -#define MPMU_PCR_PJ_AXISD (1 << 31) -#define MPMU_PCR_PJ_SLPEN (1 << 29) -#define MPMU_PCR_PJ_SPSD (1 << 28) -#define MPMU_PCR_PJ_DDRCORSD (1 << 27) -#define MPMU_PCR_PJ_APBSD (1 << 26) -#define MPMU_PCR_PJ_INTCLR (1 << 24) -#define MPMU_PCR_PJ_SLPWP0 (1 << 23) -#define MPMU_PCR_PJ_SLPWP1 (1 << 22) -#define MPMU_PCR_PJ_SLPWP2 (1 << 21) -#define MPMU_PCR_PJ_SLPWP3 (1 << 20) -#define MPMU_PCR_PJ_VCTCXOSD (1 << 19) -#define MPMU_PCR_PJ_SLPWP4 (1 << 18) -#define MPMU_PCR_PJ_SLPWP5 (1 << 17) -#define MPMU_PCR_PJ_SLPWP6 (1 << 16) -#define MPMU_PCR_PJ_SLPWP7 (1 << 15) - -#define MPMU_PLL2_CTRL1 MPMU_REG(0x0414) -#define MPMU_CGR_PJ MPMU_REG(0x1024) -#define MPMU_WUCRM_PJ MPMU_REG(0x104c) -#define MPMU_WUCRM_PJ_WAKEUP(x) (1 << (x)) -#define MPMU_WUCRM_PJ_RTC_ALARM (1 << 17) - -enum { - POWER_MODE_ACTIVE = 0, - POWER_MODE_CORE_INTIDLE, - POWER_MODE_CORE_EXTIDLE, - POWER_MODE_APPS_IDLE, - POWER_MODE_APPS_SLEEP, - POWER_MODE_CHIP_SLEEP, - POWER_MODE_SYS_SLEEP, -}; - -extern void mmp2_pm_enter_lowpower_mode(int state); -extern int mmp2_set_wake(struct irq_data *d, unsigned int on); -#endif diff --git a/arch/arm/mach-mmp/pm-pxa910.c b/arch/arm/mach-mmp/pm-pxa910.c deleted file mode 100644 index 1d71d73c1862..000000000000 --- a/arch/arm/mach-mmp/pm-pxa910.c +++ /dev/null @@ -1,272 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * PXA910 Power Management Routines - * - * (C) Copyright 2009 Marvell International Ltd. - * All Rights Reserved - */ - -#include <linux/kernel.h> -#include <linux/errno.h> -#include <linux/err.h> -#include <linux/time.h> -#include <linux/delay.h> -#include <linux/suspend.h> -#include <linux/interrupt.h> -#include <linux/io.h> -#include <linux/irq.h> -#include <asm/mach-types.h> -#include <asm/outercache.h> - -#include <linux/soc/mmp/cputype.h> -#include "addr-map.h" -#include "pm-pxa910.h" -#include "regs-icu.h" -#include "irqs.h" - -int pxa910_set_wake(struct irq_data *data, unsigned int on) -{ - uint32_t awucrm = 0, apcr = 0; - int irq = data->irq; - - /* setting wakeup sources */ - switch (irq) { - /* wakeup line 2 */ - case IRQ_PXA910_AP_GPIO: - awucrm = MPMU_AWUCRM_WAKEUP(2); - apcr |= MPMU_APCR_SLPWP2; - break; - /* wakeup line 3 */ - case IRQ_PXA910_KEYPAD: - awucrm = MPMU_AWUCRM_WAKEUP(3) | MPMU_AWUCRM_KEYPRESS; - apcr |= MPMU_APCR_SLPWP3; - break; - case IRQ_PXA910_ROTARY: - awucrm = MPMU_AWUCRM_WAKEUP(3) | MPMU_AWUCRM_NEWROTARY; - apcr |= MPMU_APCR_SLPWP3; - break; - case IRQ_PXA910_TRACKBALL: - awucrm = MPMU_AWUCRM_WAKEUP(3) | MPMU_AWUCRM_TRACKBALL; - apcr |= MPMU_APCR_SLPWP3; - break; - /* wakeup line 4 */ - case IRQ_PXA910_AP1_TIMER1: - awucrm = MPMU_AWUCRM_WAKEUP(4) | MPMU_AWUCRM_AP1_TIMER_1; - apcr |= MPMU_APCR_SLPWP4; - break; - case IRQ_PXA910_AP1_TIMER2: - awucrm = MPMU_AWUCRM_WAKEUP(4) | MPMU_AWUCRM_AP1_TIMER_2; - apcr |= MPMU_APCR_SLPWP4; - break; - case IRQ_PXA910_AP1_TIMER3: - awucrm = MPMU_AWUCRM_WAKEUP(4) | MPMU_AWUCRM_AP1_TIMER_3; - apcr |= MPMU_APCR_SLPWP4; - break; - case IRQ_PXA910_AP2_TIMER1: - awucrm = MPMU_AWUCRM_WAKEUP(4) | MPMU_AWUCRM_AP2_TIMER_1; - apcr |= MPMU_APCR_SLPWP4; - break; - case IRQ_PXA910_AP2_TIMER2: - awucrm = MPMU_AWUCRM_WAKEUP(4) | MPMU_AWUCRM_AP2_TIMER_2; - apcr |= MPMU_APCR_SLPWP4; - break; - case IRQ_PXA910_AP2_TIMER3: - awucrm = MPMU_AWUCRM_WAKEUP(4) | MPMU_AWUCRM_AP2_TIMER_3; - apcr |= MPMU_APCR_SLPWP4; - break; - case IRQ_PXA910_RTC_ALARM: - awucrm = MPMU_AWUCRM_WAKEUP(4) | MPMU_AWUCRM_RTC_ALARM; - apcr |= MPMU_APCR_SLPWP4; - break; - /* wakeup line 5 */ - case IRQ_PXA910_USB1: - case IRQ_PXA910_USB2: - awucrm = MPMU_AWUCRM_WAKEUP(5); - apcr |= MPMU_APCR_SLPWP5; - break; - /* wakeup line 6 */ - case IRQ_PXA910_MMC: - awucrm = MPMU_AWUCRM_WAKEUP(6) - | MPMU_AWUCRM_SDH1 - | MPMU_AWUCRM_SDH2; - apcr |= MPMU_APCR_SLPWP6; - break; - /* wakeup line 7 */ - case IRQ_PXA910_PMIC_INT: - awucrm = MPMU_AWUCRM_WAKEUP(7); - apcr |= MPMU_APCR_SLPWP7; - break; - default: - if (irq >= IRQ_GPIO_START && irq < IRQ_BOARD_START) { - awucrm = MPMU_AWUCRM_WAKEUP(2); - apcr |= MPMU_APCR_SLPWP2; - } else { - /* FIXME: This should return a proper error code ! */ - printk(KERN_ERR "Error: no defined wake up source irq: %d\n", - irq); - } - } - - if (on) { - if (awucrm) { - awucrm |= __raw_readl(MPMU_AWUCRM); - __raw_writel(awucrm, MPMU_AWUCRM); - } - if (apcr) { - apcr = ~apcr & __raw_readl(MPMU_APCR); - __raw_writel(apcr, MPMU_APCR); - } - } else { - if (awucrm) { - awucrm = ~awucrm & __raw_readl(MPMU_AWUCRM); - __raw_writel(awucrm, MPMU_AWUCRM); - } - if (apcr) { - apcr |= __raw_readl(MPMU_APCR); - __raw_writel(apcr, MPMU_APCR); - } - } - return 0; -} - -void pxa910_pm_enter_lowpower_mode(int state) -{ - uint32_t idle_cfg, apcr; - - idle_cfg = __raw_readl(APMU_MOH_IDLE_CFG); - apcr = __raw_readl(MPMU_APCR); - - apcr &= ~(MPMU_APCR_DDRCORSD | MPMU_APCR_APBSD | MPMU_APCR_AXISD - | MPMU_APCR_VCTCXOSD | MPMU_APCR_STBYEN); - idle_cfg &= ~(APMU_MOH_IDLE_CFG_MOH_IDLE - | APMU_MOH_IDLE_CFG_MOH_PWRDWN); - - switch (state) { - case POWER_MODE_UDR: - /* only shutdown APB in UDR */ - apcr |= MPMU_APCR_STBYEN | MPMU_APCR_APBSD; - fallthrough; - case POWER_MODE_SYS_SLEEP: - apcr |= MPMU_APCR_SLPEN; /* set the SLPEN bit */ - apcr |= MPMU_APCR_VCTCXOSD; /* set VCTCXOSD */ - fallthrough; - case POWER_MODE_APPS_SLEEP: - apcr |= MPMU_APCR_DDRCORSD; /* set DDRCORSD */ - fallthrough; - case POWER_MODE_APPS_IDLE: - apcr |= MPMU_APCR_AXISD; /* set AXISDD bit */ - fallthrough; - case POWER_MODE_CORE_EXTIDLE: - idle_cfg |= APMU_MOH_IDLE_CFG_MOH_IDLE; - idle_cfg |= APMU_MOH_IDLE_CFG_MOH_PWRDWN; - idle_cfg |= APMU_MOH_IDLE_CFG_MOH_PWR_SW(3) - | APMU_MOH_IDLE_CFG_MOH_L2_PWR_SW(3); - fallthrough; - case POWER_MODE_CORE_INTIDLE: - break; - } - - /* program the memory controller hardware sleep type and auto wakeup */ - idle_cfg |= APMU_MOH_IDLE_CFG_MOH_DIS_MC_SW_REQ; - idle_cfg |= APMU_MOH_IDLE_CFG_MOH_MC_WAKE_EN; - __raw_writel(0x0, APMU_MC_HW_SLP_TYPE); /* auto refresh */ - - /* set DSPSD, DTCMSD, BBSD, MSASLPEN */ - apcr |= MPMU_APCR_DSPSD | MPMU_APCR_DTCMSD | MPMU_APCR_BBSD - | MPMU_APCR_MSASLPEN; - - /*always set SLEPEN bit mainly for MSA*/ - apcr |= MPMU_APCR_SLPEN; - - /* finally write the registers back */ - __raw_writel(idle_cfg, APMU_MOH_IDLE_CFG); - __raw_writel(apcr, MPMU_APCR); - -} - -static int pxa910_pm_enter(suspend_state_t state) -{ - unsigned int idle_cfg, reg = 0; - - /*pmic thread not completed,exit;otherwise system can't be waked up*/ - reg = __raw_readl(ICU_INT_CONF(IRQ_PXA910_PMIC_INT)); - if ((reg & 0x3) == 0) - return -EAGAIN; - - idle_cfg = __raw_readl(APMU_MOH_IDLE_CFG); - idle_cfg |= APMU_MOH_IDLE_CFG_MOH_PWRDWN - | APMU_MOH_IDLE_CFG_MOH_SRAM_PWRDWN; - __raw_writel(idle_cfg, APMU_MOH_IDLE_CFG); - - /* disable L2 */ - outer_disable(); - /* wait for l2 idle */ - while (!(readl(CIU_REG(0x8)) & (1 << 16))) - udelay(1); - - cpu_do_idle(); - - /* enable L2 */ - outer_resume(); - /* wait for l2 idle */ - while (!(readl(CIU_REG(0x8)) & (1 << 16))) - udelay(1); - - idle_cfg = __raw_readl(APMU_MOH_IDLE_CFG); - idle_cfg &= ~(APMU_MOH_IDLE_CFG_MOH_PWRDWN - | APMU_MOH_IDLE_CFG_MOH_SRAM_PWRDWN); - __raw_writel(idle_cfg, APMU_MOH_IDLE_CFG); - - return 0; -} - -/* - * Called after processes are frozen, but before we shut down devices. - */ -static int pxa910_pm_prepare(void) -{ - pxa910_pm_enter_lowpower_mode(POWER_MODE_UDR); - return 0; -} - -/* - * Called after devices are re-setup, but before processes are thawed. - */ -static void pxa910_pm_finish(void) -{ - pxa910_pm_enter_lowpower_mode(POWER_MODE_CORE_INTIDLE); -} - -static int pxa910_pm_valid(suspend_state_t state) -{ - return ((state == PM_SUSPEND_STANDBY) || (state == PM_SUSPEND_MEM)); -} - -static const struct platform_suspend_ops pxa910_pm_ops = { - .valid = pxa910_pm_valid, - .prepare = pxa910_pm_prepare, - .enter = pxa910_pm_enter, - .finish = pxa910_pm_finish, -}; - -static int __init pxa910_pm_init(void) -{ - uint32_t awucrm = 0; - - if (!cpu_is_pxa910()) - return -EIO; - - suspend_set_ops(&pxa910_pm_ops); - - /* Set the following bits for MMP3 playback with VCTXO on */ - __raw_writel(__raw_readl(APMU_SQU_CLK_GATE_CTRL) | (1 << 30), - APMU_SQU_CLK_GATE_CTRL); - __raw_writel(__raw_readl(MPMU_FCCR) | (1 << 28), MPMU_FCCR); - - awucrm |= MPMU_AWUCRM_AP_ASYNC_INT | MPMU_AWUCRM_AP_FULL_IDLE; - __raw_writel(awucrm, MPMU_AWUCRM); - - return 0; -} - -late_initcall(pxa910_pm_init); diff --git a/arch/arm/mach-mmp/pm-pxa910.h b/arch/arm/mach-mmp/pm-pxa910.h deleted file mode 100644 index 8e6344adaf51..000000000000 --- a/arch/arm/mach-mmp/pm-pxa910.h +++ /dev/null @@ -1,75 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * PXA910 Power Management Routines - * - * (C) Copyright 2009 Marvell International Ltd. - * All Rights Reserved - */ - -#ifndef __PXA910_PM_H__ -#define __PXA910_PM_H__ - -#define APMU_MOH_IDLE_CFG APMU_REG(0x0018) -#define APMU_MOH_IDLE_CFG_MOH_IDLE (1 << 1) -#define APMU_MOH_IDLE_CFG_MOH_PWRDWN (1 << 5) -#define APMU_MOH_IDLE_CFG_MOH_SRAM_PWRDWN (1 << 6) -#define APMU_MOH_IDLE_CFG_MOH_PWR_SW(x) (((x) & 0x3) << 16) -#define APMU_MOH_IDLE_CFG_MOH_L2_PWR_SW(x) (((x) & 0x3) << 18) -#define APMU_MOH_IDLE_CFG_MOH_DIS_MC_SW_REQ (1 << 21) -#define APMU_MOH_IDLE_CFG_MOH_MC_WAKE_EN (1 << 20) - -#define APMU_SQU_CLK_GATE_CTRL APMU_REG(0x001c) -#define APMU_MC_HW_SLP_TYPE APMU_REG(0x00b0) - -#define MPMU_FCCR MPMU_REG(0x0008) -#define MPMU_APCR MPMU_REG(0x1000) -#define MPMU_APCR_AXISD (1 << 31) -#define MPMU_APCR_DSPSD (1 << 30) -#define MPMU_APCR_SLPEN (1 << 29) -#define MPMU_APCR_DTCMSD (1 << 28) -#define MPMU_APCR_DDRCORSD (1 << 27) -#define MPMU_APCR_APBSD (1 << 26) -#define MPMU_APCR_BBSD (1 << 25) -#define MPMU_APCR_SLPWP0 (1 << 23) -#define MPMU_APCR_SLPWP1 (1 << 22) -#define MPMU_APCR_SLPWP2 (1 << 21) -#define MPMU_APCR_SLPWP3 (1 << 20) -#define MPMU_APCR_VCTCXOSD (1 << 19) -#define MPMU_APCR_SLPWP4 (1 << 18) -#define MPMU_APCR_SLPWP5 (1 << 17) -#define MPMU_APCR_SLPWP6 (1 << 16) -#define MPMU_APCR_SLPWP7 (1 << 15) -#define MPMU_APCR_MSASLPEN (1 << 14) -#define MPMU_APCR_STBYEN (1 << 13) - -#define MPMU_AWUCRM MPMU_REG(0x104c) -#define MPMU_AWUCRM_AP_ASYNC_INT (1 << 25) -#define MPMU_AWUCRM_AP_FULL_IDLE (1 << 24) -#define MPMU_AWUCRM_SDH1 (1 << 23) -#define MPMU_AWUCRM_SDH2 (1 << 22) -#define MPMU_AWUCRM_KEYPRESS (1 << 21) -#define MPMU_AWUCRM_TRACKBALL (1 << 20) -#define MPMU_AWUCRM_NEWROTARY (1 << 19) -#define MPMU_AWUCRM_RTC_ALARM (1 << 17) -#define MPMU_AWUCRM_AP2_TIMER_3 (1 << 13) -#define MPMU_AWUCRM_AP2_TIMER_2 (1 << 12) -#define MPMU_AWUCRM_AP2_TIMER_1 (1 << 11) -#define MPMU_AWUCRM_AP1_TIMER_3 (1 << 10) -#define MPMU_AWUCRM_AP1_TIMER_2 (1 << 9) -#define MPMU_AWUCRM_AP1_TIMER_1 (1 << 8) -#define MPMU_AWUCRM_WAKEUP(x) (1 << ((x) & 0x7)) - -enum { - POWER_MODE_ACTIVE = 0, - POWER_MODE_CORE_INTIDLE, - POWER_MODE_CORE_EXTIDLE, - POWER_MODE_APPS_IDLE, - POWER_MODE_APPS_SLEEP, - POWER_MODE_SYS_SLEEP, - POWER_MODE_HIBERNATE, - POWER_MODE_UDR, -}; - -extern int pxa910_set_wake(struct irq_data *data, unsigned int on); - -#endif diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c deleted file mode 100644 index 1e9389245d0e..000000000000 --- a/arch/arm/mach-mmp/pxa168.c +++ /dev/null @@ -1,175 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-mmp/pxa168.c - * - * Code specific to PXA168 - */ -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/list.h> -#include <linux/io.h> -#include <linux/clk.h> -#include <linux/clk/mmp.h> -#include <linux/platform_device.h> -#include <linux/platform_data/mv_usb.h> -#include <linux/dma-mapping.h> - -#include <asm/mach/time.h> -#include <asm/system_misc.h> - -#include "addr-map.h" -#include "common.h" -#include <linux/soc/mmp/cputype.h> -#include "devices.h" -#include "irqs.h" -#include "mfp.h" -#include "pxa168.h" -#include "regs-apbc.h" -#include "regs-apmu.h" -#include "regs-usb.h" - -#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) - -static struct mfp_addr_map pxa168_mfp_addr_map[] __initdata = -{ - MFP_ADDR_X(GPIO0, GPIO36, 0x04c), - MFP_ADDR_X(GPIO37, GPIO55, 0x000), - MFP_ADDR_X(GPIO56, GPIO123, 0x0e0), - MFP_ADDR_X(GPIO124, GPIO127, 0x0f4), - - MFP_ADDR_END, -}; - -void __init pxa168_init_irq(void) -{ - icu_init_irq(); -} - -static int __init pxa168_init(void) -{ - if (cpu_is_pxa168()) { - mfp_init_base(MFPR_VIRT_BASE); - mfp_init_addr(pxa168_mfp_addr_map); - pxa168_clk_init(APB_PHYS_BASE + 0x50000, - AXI_PHYS_BASE + 0x82800, - APB_PHYS_BASE + 0x15000); - } - - return 0; -} -postcore_initcall(pxa168_init); - -/* system timer - clock enabled, 3.25MHz */ -#define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3)) -#define APBC_TIMERS APBC_REG(0x34) - -void __init pxa168_timer_init(void) -{ - /* this is early, we have to initialize the CCU registers by - * ourselves instead of using clk_* API. Clock rate is defined - * by APBC_TIMERS_CLK_RST (3.25MHz) and enabled free-running - */ - __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS); - - /* 3.25MHz, bus/functional clock enabled, release reset */ - __raw_writel(TIMER_CLK_RST, APBC_TIMERS); - - mmp_timer_init(IRQ_PXA168_TIMER1, 3250000); -} - -void pxa168_clear_keypad_wakeup(void) -{ - uint32_t val; - uint32_t mask = APMU_PXA168_KP_WAKE_CLR; - - /* wake event clear is needed in order to clear keypad interrupt */ - val = __raw_readl(APMU_WAKE_CLR); - __raw_writel(val | mask, APMU_WAKE_CLR); -} - -/* on-chip devices */ -PXA168_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4017000, 0x30, 21, 22); -PXA168_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4018000, 0x30, 23, 24); -PXA168_DEVICE(uart3, "pxa2xx-uart", 2, UART3, 0xd4026000, 0x30, 23, 24); -PXA168_DEVICE(twsi0, "pxa2xx-i2c", 0, TWSI0, 0xd4011000, 0x28); -PXA168_DEVICE(twsi1, "pxa2xx-i2c", 1, TWSI1, 0xd4025000, 0x28); -PXA168_DEVICE(pwm1, "pxa168-pwm", 0, NONE, 0xd401a000, 0x10); -PXA168_DEVICE(pwm2, "pxa168-pwm", 1, NONE, 0xd401a400, 0x10); -PXA168_DEVICE(pwm3, "pxa168-pwm", 2, NONE, 0xd401a800, 0x10); -PXA168_DEVICE(pwm4, "pxa168-pwm", 3, NONE, 0xd401ac00, 0x10); -PXA168_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x80, 97, 99); -PXA168_DEVICE(ssp1, "pxa168-ssp", 0, SSP1, 0xd401b000, 0x40, 52, 53); -PXA168_DEVICE(ssp2, "pxa168-ssp", 1, SSP2, 0xd401c000, 0x40, 54, 55); -PXA168_DEVICE(ssp3, "pxa168-ssp", 2, SSP3, 0xd401f000, 0x40, 56, 57); -PXA168_DEVICE(ssp4, "pxa168-ssp", 3, SSP4, 0xd4020000, 0x40, 58, 59); -PXA168_DEVICE(ssp5, "pxa168-ssp", 4, SSP5, 0xd4021000, 0x40, 60, 61); -PXA168_DEVICE(fb, "pxa168-fb", -1, LCD, 0xd420b000, 0x1c8); -PXA168_DEVICE(keypad, "pxa27x-keypad", -1, KEYPAD, 0xd4012000, 0x4c); -PXA168_DEVICE(eth, "pxa168-eth", -1, MFU, 0xc0800000, 0x0fff); - -struct resource pxa168_resource_gpio[] = { - { - .start = 0xd4019000, - .end = 0xd4019fff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PXA168_GPIOX, - .end = IRQ_PXA168_GPIOX, - .name = "gpio_mux", - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device pxa168_device_gpio = { - .name = "mmp-gpio", - .id = -1, - .num_resources = ARRAY_SIZE(pxa168_resource_gpio), - .resource = pxa168_resource_gpio, -}; - -struct resource pxa168_usb_host_resources[] = { - /* USB Host conroller register base */ - [0] = { - .start = PXA168_U2H_REGBASE + U2x_CAPREGS_OFFSET, - .end = PXA168_U2H_REGBASE + USB_REG_RANGE, - .flags = IORESOURCE_MEM, - .name = "capregs", - }, - /* USB PHY register base */ - [1] = { - .start = PXA168_U2H_PHYBASE, - .end = PXA168_U2H_PHYBASE + USB_PHY_RANGE, - .flags = IORESOURCE_MEM, - .name = "phyregs", - }, - [2] = { - .start = IRQ_PXA168_USB2, - .end = IRQ_PXA168_USB2, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 pxa168_usb_host_dmamask = DMA_BIT_MASK(32); -struct platform_device pxa168_device_usb_host = { - .name = "pxa-sph", - .id = -1, - .dev = { - .dma_mask = &pxa168_usb_host_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - - .num_resources = ARRAY_SIZE(pxa168_usb_host_resources), - .resource = pxa168_usb_host_resources, -}; - -int __init pxa168_add_usb_host(struct mv_usb_platform_data *pdata) -{ - pxa168_device_usb_host.dev.platform_data = pdata; - return platform_device_register(&pxa168_device_usb_host); -} - -void pxa168_restart(enum reboot_mode mode, const char *cmd) -{ - soft_restart(0xffff0000); -} diff --git a/arch/arm/mach-mmp/pxa168.h b/arch/arm/mach-mmp/pxa168.h deleted file mode 100644 index c1547e098f09..000000000000 --- a/arch/arm/mach-mmp/pxa168.h +++ /dev/null @@ -1,139 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_MACH_PXA168_H -#define __ASM_MACH_PXA168_H - -#include <linux/reboot.h> - -extern void pxa168_timer_init(void); -extern void __init pxa168_init_irq(void); -extern void pxa168_restart(enum reboot_mode, const char *); -extern void pxa168_clear_keypad_wakeup(void); - -#include <linux/i2c.h> -#include <linux/platform_data/i2c-pxa.h> -#include <linux/platform_data/mtd-nand-pxa3xx.h> -#include <video/pxa168fb.h> -#include <linux/platform_data/keypad-pxa27x.h> -#include <linux/pxa168_eth.h> -#include <linux/platform_data/mv_usb.h> -#include <linux/soc/mmp/cputype.h> -#include <linux/irqchip/mmp.h> - -#include "devices.h" - -extern struct mmp_device_desc pxa168_device_uart1; -extern struct mmp_device_desc pxa168_device_uart2; -extern struct mmp_device_desc pxa168_device_uart3; -extern struct mmp_device_desc pxa168_device_twsi0; -extern struct mmp_device_desc pxa168_device_twsi1; -extern struct mmp_device_desc pxa168_device_pwm1; -extern struct mmp_device_desc pxa168_device_pwm2; -extern struct mmp_device_desc pxa168_device_pwm3; -extern struct mmp_device_desc pxa168_device_pwm4; -extern struct mmp_device_desc pxa168_device_ssp1; -extern struct mmp_device_desc pxa168_device_ssp2; -extern struct mmp_device_desc pxa168_device_ssp3; -extern struct mmp_device_desc pxa168_device_ssp4; -extern struct mmp_device_desc pxa168_device_ssp5; -extern struct mmp_device_desc pxa168_device_nand; -extern struct mmp_device_desc pxa168_device_fb; -extern struct mmp_device_desc pxa168_device_keypad; -extern struct mmp_device_desc pxa168_device_eth; - -/* pdata can be NULL */ -extern int __init pxa168_add_usb_host(struct mv_usb_platform_data *pdata); - - -extern struct platform_device pxa168_device_gpio; - -static inline int pxa168_add_uart(int id) -{ - struct mmp_device_desc *d = NULL; - - switch (id) { - case 1: d = &pxa168_device_uart1; break; - case 2: d = &pxa168_device_uart2; break; - case 3: d = &pxa168_device_uart3; break; - } - - if (d == NULL) - return -EINVAL; - - return mmp_register_device(d, NULL, 0); -} - -static inline int pxa168_add_twsi(int id, struct i2c_pxa_platform_data *data, - struct i2c_board_info *info, unsigned size) -{ - struct mmp_device_desc *d = NULL; - int ret; - - switch (id) { - case 0: d = &pxa168_device_twsi0; break; - case 1: d = &pxa168_device_twsi1; break; - default: - return -EINVAL; - } - - ret = i2c_register_board_info(id, info, size); - if (ret) - return ret; - - return mmp_register_device(d, data, sizeof(*data)); -} - -static inline int pxa168_add_pwm(int id) -{ - struct mmp_device_desc *d = NULL; - - switch (id) { - case 1: d = &pxa168_device_pwm1; break; - case 2: d = &pxa168_device_pwm2; break; - case 3: d = &pxa168_device_pwm3; break; - case 4: d = &pxa168_device_pwm4; break; - default: - return -EINVAL; - } - - return mmp_register_device(d, NULL, 0); -} - -static inline int pxa168_add_ssp(int id) -{ - struct mmp_device_desc *d = NULL; - - switch (id) { - case 1: d = &pxa168_device_ssp1; break; - case 2: d = &pxa168_device_ssp2; break; - case 3: d = &pxa168_device_ssp3; break; - case 4: d = &pxa168_device_ssp4; break; - case 5: d = &pxa168_device_ssp5; break; - default: - return -EINVAL; - } - return mmp_register_device(d, NULL, 0); -} - -static inline int pxa168_add_nand(struct pxa3xx_nand_platform_data *info) -{ - return mmp_register_device(&pxa168_device_nand, info, sizeof(*info)); -} - -static inline int pxa168_add_fb(struct pxa168fb_mach_info *mi) -{ - return mmp_register_device(&pxa168_device_fb, mi, sizeof(*mi)); -} - -static inline int pxa168_add_keypad(struct pxa27x_keypad_platform_data *data) -{ - if (cpu_is_pxa168()) - data->clear_wakeup_event = pxa168_clear_keypad_wakeup; - - return mmp_register_device(&pxa168_device_keypad, data, sizeof(*data)); -} - -static inline int pxa168_add_eth(struct pxa168_eth_platform_data *data) -{ - return mmp_register_device(&pxa168_device_eth, data, sizeof(*data)); -} -#endif /* __ASM_MACH_PXA168_H */ diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c deleted file mode 100644 index b19a069d9fab..000000000000 --- a/arch/arm/mach-mmp/pxa910.c +++ /dev/null @@ -1,190 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-mmp/pxa910.c - * - * Code specific to PXA910 - */ -#include <linux/clk/mmp.h> -#include <linux/module.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/list.h> -#include <linux/io.h> -#include <linux/irq.h> -#include <linux/irqchip/mmp.h> -#include <linux/platform_device.h> - -#include <asm/hardware/cache-tauros2.h> -#include <asm/mach/time.h> -#include "addr-map.h" -#include "regs-apbc.h" -#include <linux/soc/mmp/cputype.h> -#include "irqs.h" -#include "mfp.h" -#include "devices.h" -#include "pm-pxa910.h" -#include "pxa910.h" - -#include "common.h" - -#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000) - -static struct mfp_addr_map pxa910_mfp_addr_map[] __initdata = -{ - MFP_ADDR_X(GPIO0, GPIO54, 0xdc), - MFP_ADDR_X(GPIO67, GPIO98, 0x1b8), - MFP_ADDR_X(GPIO100, GPIO109, 0x238), - - MFP_ADDR(GPIO123, 0xcc), - MFP_ADDR(GPIO124, 0xd0), - - MFP_ADDR(DF_IO0, 0x40), - MFP_ADDR(DF_IO1, 0x3c), - MFP_ADDR(DF_IO2, 0x38), - MFP_ADDR(DF_IO3, 0x34), - MFP_ADDR(DF_IO4, 0x30), - MFP_ADDR(DF_IO5, 0x2c), - MFP_ADDR(DF_IO6, 0x28), - MFP_ADDR(DF_IO7, 0x24), - MFP_ADDR(DF_IO8, 0x20), - MFP_ADDR(DF_IO9, 0x1c), - MFP_ADDR(DF_IO10, 0x18), - MFP_ADDR(DF_IO11, 0x14), - MFP_ADDR(DF_IO12, 0x10), - MFP_ADDR(DF_IO13, 0xc), - MFP_ADDR(DF_IO14, 0x8), - MFP_ADDR(DF_IO15, 0x4), - - MFP_ADDR(DF_nCS0_SM_nCS2, 0x44), - MFP_ADDR(DF_nCS1_SM_nCS3, 0x48), - MFP_ADDR(SM_nCS0, 0x4c), - MFP_ADDR(SM_nCS1, 0x50), - MFP_ADDR(DF_WEn, 0x54), - MFP_ADDR(DF_REn, 0x58), - MFP_ADDR(DF_CLE_SM_OEn, 0x5c), - MFP_ADDR(DF_ALE_SM_WEn, 0x60), - MFP_ADDR(SM_SCLK, 0x64), - MFP_ADDR(DF_RDY0, 0x68), - MFP_ADDR(SM_BE0, 0x6c), - MFP_ADDR(SM_BE1, 0x70), - MFP_ADDR(SM_ADV, 0x74), - MFP_ADDR(DF_RDY1, 0x78), - MFP_ADDR(SM_ADVMUX, 0x7c), - MFP_ADDR(SM_RDY, 0x80), - - MFP_ADDR_X(MMC1_DAT7, MMC1_WP, 0x84), - - MFP_ADDR_END, -}; - -void __init pxa910_init_irq(void) -{ - icu_init_irq(); -#ifdef CONFIG_PM - icu_irq_chip.irq_set_wake = pxa910_set_wake; -#endif -} - -static int __init pxa910_init(void) -{ - if (cpu_is_pxa910()) { -#ifdef CONFIG_CACHE_TAUROS2 - tauros2_init(0); -#endif - mfp_init_base(MFPR_VIRT_BASE); - mfp_init_addr(pxa910_mfp_addr_map); - pxa910_clk_init(APB_PHYS_BASE + 0x50000, - AXI_PHYS_BASE + 0x82800, - APB_PHYS_BASE + 0x15000, - APB_PHYS_BASE + 0x3b000); - } - - return 0; -} -postcore_initcall(pxa910_init); - -/* system timer - clock enabled, 3.25MHz */ -#define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3)) -#define APBC_TIMERS APBC_REG(0x34) - -void __init pxa910_timer_init(void) -{ - /* reset and configure */ - __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS); - __raw_writel(TIMER_CLK_RST, APBC_TIMERS); - - mmp_timer_init(IRQ_PXA910_AP1_TIMER1, 3250000); -} - -/* on-chip devices */ - -/* NOTE: there are totally 3 UARTs on PXA910: - * - * UART1 - Slow UART (can be used both by AP and CP) - * UART2/3 - Fast UART - * - * To be backward compatible with the legacy FFUART/BTUART/STUART sequence, - * they are re-ordered as: - * - * pxa910_device_uart1 - UART2 as FFUART - * pxa910_device_uart2 - UART3 as BTUART - * - * UART1 is not used by AP for the moment. - */ -PXA910_DEVICE(uart1, "pxa2xx-uart", 0, UART2, 0xd4017000, 0x30, 21, 22); -PXA910_DEVICE(uart2, "pxa2xx-uart", 1, UART3, 0xd4018000, 0x30, 23, 24); -PXA910_DEVICE(twsi0, "pxa2xx-i2c", 0, TWSI0, 0xd4011000, 0x28); -PXA910_DEVICE(twsi1, "pxa2xx-i2c", 1, TWSI1, 0xd4025000, 0x28); -PXA910_DEVICE(pwm1, "pxa910-pwm", 0, NONE, 0xd401a000, 0x10); -PXA910_DEVICE(pwm2, "pxa910-pwm", 1, NONE, 0xd401a400, 0x10); -PXA910_DEVICE(pwm3, "pxa910-pwm", 2, NONE, 0xd401a800, 0x10); -PXA910_DEVICE(pwm4, "pxa910-pwm", 3, NONE, 0xd401ac00, 0x10); -PXA910_DEVICE(nand, "pxa3xx-nand", -1, NAND, 0xd4283000, 0x80, 97, 99); -PXA910_DEVICE(disp, "mmp-disp", 0, LCD, 0xd420b000, 0x1ec); -PXA910_DEVICE(fb, "mmp-fb", -1, NONE, 0, 0); -PXA910_DEVICE(panel, "tpo-hvga", -1, NONE, 0, 0); - -struct resource pxa910_resource_gpio[] = { - { - .start = 0xd4019000, - .end = 0xd4019fff, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PXA910_AP_GPIO, - .end = IRQ_PXA910_AP_GPIO, - .name = "gpio_mux", - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device pxa910_device_gpio = { - .name = "mmp-gpio", - .id = -1, - .num_resources = ARRAY_SIZE(pxa910_resource_gpio), - .resource = pxa910_resource_gpio, -}; - -static struct resource pxa910_resource_rtc[] = { - { - .start = 0xd4010000, - .end = 0xd401003f, - .flags = IORESOURCE_MEM, - }, { - .start = IRQ_PXA910_RTC_INT, - .end = IRQ_PXA910_RTC_INT, - .name = "rtc 1Hz", - .flags = IORESOURCE_IRQ, - }, { - .start = IRQ_PXA910_RTC_ALARM, - .end = IRQ_PXA910_RTC_ALARM, - .name = "rtc alarm", - .flags = IORESOURCE_IRQ, - }, -}; - -struct platform_device pxa910_device_rtc = { - .name = "sa1100-rtc", - .id = -1, - .num_resources = ARRAY_SIZE(pxa910_resource_rtc), - .resource = pxa910_resource_rtc, -}; diff --git a/arch/arm/mach-mmp/pxa910.h b/arch/arm/mach-mmp/pxa910.h deleted file mode 100644 index 7d229214065a..000000000000 --- a/arch/arm/mach-mmp/pxa910.h +++ /dev/null @@ -1,90 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __ASM_MACH_PXA910_H -#define __ASM_MACH_PXA910_H - -extern void pxa910_timer_init(void); -extern void __init pxa910_init_irq(void); - -#include <linux/i2c.h> -#include <linux/platform_data/i2c-pxa.h> -#include <linux/platform_data/mtd-nand-pxa3xx.h> -#include <video/mmp_disp.h> -#include <linux/irqchip/mmp.h> - -#include "devices.h" - -extern struct mmp_device_desc pxa910_device_uart1; -extern struct mmp_device_desc pxa910_device_uart2; -extern struct mmp_device_desc pxa910_device_twsi0; -extern struct mmp_device_desc pxa910_device_twsi1; -extern struct mmp_device_desc pxa910_device_pwm1; -extern struct mmp_device_desc pxa910_device_pwm2; -extern struct mmp_device_desc pxa910_device_pwm3; -extern struct mmp_device_desc pxa910_device_pwm4; -extern struct mmp_device_desc pxa910_device_nand; -extern struct platform_device pxa168_device_usb_phy; -extern struct platform_device pxa168_device_u2o; -extern struct platform_device pxa168_device_u2ootg; -extern struct platform_device pxa168_device_u2oehci; -extern struct mmp_device_desc pxa910_device_disp; -extern struct mmp_device_desc pxa910_device_fb; -extern struct mmp_device_desc pxa910_device_panel; -extern struct platform_device pxa910_device_gpio; -extern struct platform_device pxa910_device_rtc; - -static inline int pxa910_add_uart(int id) -{ - struct mmp_device_desc *d = NULL; - - switch (id) { - case 1: d = &pxa910_device_uart1; break; - case 2: d = &pxa910_device_uart2; break; - } - - if (d == NULL) - return -EINVAL; - - return mmp_register_device(d, NULL, 0); -} - -static inline int pxa910_add_twsi(int id, struct i2c_pxa_platform_data *data, - struct i2c_board_info *info, unsigned size) -{ - struct mmp_device_desc *d = NULL; - int ret; - - switch (id) { - case 0: d = &pxa910_device_twsi0; break; - case 1: d = &pxa910_device_twsi1; break; - default: - return -EINVAL; - } - - ret = i2c_register_board_info(id, info, size); - if (ret) - return ret; - - return mmp_register_device(d, data, sizeof(*data)); -} - -static inline int pxa910_add_pwm(int id) -{ - struct mmp_device_desc *d = NULL; - - switch (id) { - case 1: d = &pxa910_device_pwm1; break; - case 2: d = &pxa910_device_pwm2; break; - case 3: d = &pxa910_device_pwm3; break; - case 4: d = &pxa910_device_pwm4; break; - default: - return -EINVAL; - } - - return mmp_register_device(d, NULL, 0); -} - -static inline int pxa910_add_nand(struct pxa3xx_nand_platform_data *info) -{ - return mmp_register_device(&pxa910_device_nand, info, sizeof(*info)); -} -#endif /* __ASM_MACH_PXA910_H */ diff --git a/arch/arm/mach-mmp/regs-apbc.h b/arch/arm/mach-mmp/regs-apbc.h deleted file mode 100644 index d0d00c2cce38..000000000000 --- a/arch/arm/mach-mmp/regs-apbc.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Application Peripheral Bus Clock Unit - */ - -#ifndef __ASM_MACH_REGS_APBC_H -#define __ASM_MACH_REGS_APBC_H - -#include "addr-map.h" - -/* Common APB clock register bit definitions */ -#define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */ -#define APBC_FNCLK (1 << 1) /* Functional Clock Enable */ -#define APBC_RST (1 << 2) /* Reset Generation */ - -/* Functional Clock Selection Mask */ -#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4) - -#endif /* __ASM_MACH_REGS_APBC_H */ diff --git a/arch/arm/mach-mmp/regs-apmu.h b/arch/arm/mach-mmp/regs-apmu.h deleted file mode 100644 index e36f6503adfb..000000000000 --- a/arch/arm/mach-mmp/regs-apmu.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Application Subsystem Power Management Unit - */ - -#ifndef __ASM_MACH_REGS_APMU_H -#define __ASM_MACH_REGS_APMU_H - -#include "addr-map.h" - -#define APMU_FNCLK_EN (1 << 4) -#define APMU_AXICLK_EN (1 << 3) -#define APMU_FNRST_DIS (1 << 1) -#define APMU_AXIRST_DIS (1 << 0) - -/* Wake Clear Register */ -#define APMU_WAKE_CLR APMU_REG(0x07c) - -#define APMU_PXA168_KP_WAKE_CLR (1 << 7) -#define APMU_PXA168_CFI_WAKE_CLR (1 << 6) -#define APMU_PXA168_XD_WAKE_CLR (1 << 5) -#define APMU_PXA168_MSP_WAKE_CLR (1 << 4) -#define APMU_PXA168_SD4_WAKE_CLR (1 << 3) -#define APMU_PXA168_SD3_WAKE_CLR (1 << 2) -#define APMU_PXA168_SD2_WAKE_CLR (1 << 1) -#define APMU_PXA168_SD1_WAKE_CLR (1 << 0) - -#endif /* __ASM_MACH_REGS_APMU_H */ diff --git a/arch/arm/mach-mmp/regs-icu.h b/arch/arm/mach-mmp/regs-icu.h deleted file mode 100644 index 410743d2b402..000000000000 --- a/arch/arm/mach-mmp/regs-icu.h +++ /dev/null @@ -1,69 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Interrupt Control Unit - */ - -#ifndef __ASM_MACH_ICU_H -#define __ASM_MACH_ICU_H - -#include "addr-map.h" - -#define ICU_VIRT_BASE (AXI_VIRT_BASE + 0x82000) -#define ICU_REG(x) (ICU_VIRT_BASE + (x)) - -#define ICU2_VIRT_BASE (AXI_VIRT_BASE + 0x84000) -#define ICU2_REG(x) (ICU2_VIRT_BASE + (x)) - -#define ICU_INT_CONF(n) ICU_REG((n) << 2) -#define ICU_INT_CONF_MASK (0xf) - -/************ PXA168/PXA910 (MMP) *********************/ -#define ICU_INT_CONF_AP_INT (1 << 6) -#define ICU_INT_CONF_CP_INT (1 << 5) -#define ICU_INT_CONF_IRQ (1 << 4) - -#define ICU_AP_FIQ_SEL_INT_NUM ICU_REG(0x108) /* AP FIQ Selected Interrupt */ -#define ICU_AP_IRQ_SEL_INT_NUM ICU_REG(0x10C) /* AP IRQ Selected Interrupt */ -#define ICU_AP_GBL_IRQ_MSK ICU_REG(0x114) /* AP Global Interrupt Mask */ -#define ICU_INT_STATUS_0 ICU_REG(0x128) /* Interrupt Stuats 0 */ -#define ICU_INT_STATUS_1 ICU_REG(0x12C) /* Interrupt Status 1 */ - -/************************** MMP2 ***********************/ - -/* - * IRQ0/FIQ0 is routed to SP IRQ/FIQ. - * IRQ1 is routed to PJ4 IRQ, and IRQ2 is routes to PJ4 FIQ. - */ -#define ICU_INT_ROUTE_SP_IRQ (1 << 4) -#define ICU_INT_ROUTE_PJ4_IRQ (1 << 5) -#define ICU_INT_ROUTE_PJ4_FIQ (1 << 6) - -#define MMP2_ICU_PJ4_IRQ_STATUS0 ICU_REG(0x138) -#define MMP2_ICU_PJ4_IRQ_STATUS1 ICU_REG(0x13c) -#define MMP2_ICU_PJ4_FIQ_STATUS0 ICU_REG(0x140) -#define MMP2_ICU_PJ4_FIQ_STATUS1 ICU_REG(0x144) - -#define MMP2_ICU_INT4_STATUS ICU_REG(0x150) -#define MMP2_ICU_INT5_STATUS ICU_REG(0x154) -#define MMP2_ICU_INT17_STATUS ICU_REG(0x158) -#define MMP2_ICU_INT35_STATUS ICU_REG(0x15c) -#define MMP2_ICU_INT51_STATUS ICU_REG(0x160) - -#define MMP2_ICU_INT4_MASK ICU_REG(0x168) -#define MMP2_ICU_INT5_MASK ICU_REG(0x16C) -#define MMP2_ICU_INT17_MASK ICU_REG(0x170) -#define MMP2_ICU_INT35_MASK ICU_REG(0x174) -#define MMP2_ICU_INT51_MASK ICU_REG(0x178) - -#define MMP2_ICU_SP_IRQ_SEL ICU_REG(0x100) -#define MMP2_ICU_PJ4_IRQ_SEL ICU_REG(0x104) -#define MMP2_ICU_PJ4_FIQ_SEL ICU_REG(0x108) - -#define MMP2_ICU_INVERT ICU_REG(0x164) - -#define MMP2_ICU_INV_PMIC (1 << 0) -#define MMP2_ICU_INV_PERF (1 << 1) -#define MMP2_ICU_INV_COMMTX (1 << 2) -#define MMP2_ICU_INV_COMMRX (1 << 3) - -#endif /* __ASM_MACH_ICU_H */ diff --git a/arch/arm/mach-mmp/regs-timers.h b/arch/arm/mach-mmp/regs-timers.h index a69f4d7e3443..0cc4aca40e2c 100644 --- a/arch/arm/mach-mmp/regs-timers.h +++ b/arch/arm/mach-mmp/regs-timers.h @@ -6,11 +6,6 @@ #ifndef __ASM_MACH_REGS_TIMERS_H #define __ASM_MACH_REGS_TIMERS_H -#include "addr-map.h" - -#define TIMERS1_VIRT_BASE (APB_VIRT_BASE + 0x14000) -#define TIMERS2_VIRT_BASE (APB_VIRT_BASE + 0x16000) - #define TMR_CCR (0x0000) #define TMR_TN_MM(n, m) (0x0004 + ((n) << 3) + (((n) + (m)) << 2)) #define TMR_CR(n) (0x0028 + ((n) << 2)) diff --git a/arch/arm/mach-mmp/regs-usb.h b/arch/arm/mach-mmp/regs-usb.h deleted file mode 100644 index ed0d1aa0ad6c..000000000000 --- a/arch/arm/mach-mmp/regs-usb.h +++ /dev/null @@ -1,155 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (C) 2011 Marvell International Ltd. All rights reserved. - */ - -#ifndef __ASM_ARCH_REGS_USB_H -#define __ASM_ARCH_REGS_USB_H - -#define PXA168_U2O_REGBASE (0xd4208000) -#define PXA168_U2O_PHYBASE (0xd4207000) - -#define PXA168_U2H_REGBASE (0xd4209000) -#define PXA168_U2H_PHYBASE (0xd4206000) - -#define MMP3_HSIC1_REGBASE (0xf0001000) -#define MMP3_HSIC1_PHYBASE (0xf0001800) - -#define MMP3_HSIC2_REGBASE (0xf0002000) -#define MMP3_HSIC2_PHYBASE (0xf0002800) - -#define MMP3_FSIC_REGBASE (0xf0003000) -#define MMP3_FSIC_PHYBASE (0xf0003800) - - -#define USB_REG_RANGE (0x1ff) -#define USB_PHY_RANGE (0xff) - -/* registers */ -#define U2x_CAPREGS_OFFSET 0x100 - -/* phy regs */ -#define UTMI_REVISION 0x0 -#define UTMI_CTRL 0x4 -#define UTMI_PLL 0x8 -#define UTMI_TX 0xc -#define UTMI_RX 0x10 -#define UTMI_IVREF 0x14 -#define UTMI_T0 0x18 -#define UTMI_T1 0x1c -#define UTMI_T2 0x20 -#define UTMI_T3 0x24 -#define UTMI_T4 0x28 -#define UTMI_T5 0x2c -#define UTMI_RESERVE 0x30 -#define UTMI_USB_INT 0x34 -#define UTMI_DBG_CTL 0x38 -#define UTMI_OTG_ADDON 0x3c - -/* For UTMICTRL Register */ -#define UTMI_CTRL_USB_CLK_EN (1 << 31) -/* pxa168 */ -#define UTMI_CTRL_SUSPEND_SET1 (1 << 30) -#define UTMI_CTRL_SUSPEND_SET2 (1 << 29) -#define UTMI_CTRL_RXBUF_PDWN (1 << 24) -#define UTMI_CTRL_TXBUF_PDWN (1 << 11) - -#define UTMI_CTRL_INPKT_DELAY_SHIFT 30 -#define UTMI_CTRL_INPKT_DELAY_SOF_SHIFT 28 -#define UTMI_CTRL_PU_REF_SHIFT 20 -#define UTMI_CTRL_ARC_PULLDN_SHIFT 12 -#define UTMI_CTRL_PLL_PWR_UP_SHIFT 1 -#define UTMI_CTRL_PWR_UP_SHIFT 0 - -/* For UTMI_PLL Register */ -#define UTMI_PLL_PLLCALI12_SHIFT 29 -#define UTMI_PLL_PLLCALI12_MASK (0x3 << 29) - -#define UTMI_PLL_PLLVDD18_SHIFT 27 -#define UTMI_PLL_PLLVDD18_MASK (0x3 << 27) - -#define UTMI_PLL_PLLVDD12_SHIFT 25 -#define UTMI_PLL_PLLVDD12_MASK (0x3 << 25) - -#define UTMI_PLL_CLK_BLK_EN_SHIFT 24 -#define CLK_BLK_EN (0x1 << 24) -#define PLL_READY (0x1 << 23) -#define KVCO_EXT (0x1 << 22) -#define VCOCAL_START (0x1 << 21) - -#define UTMI_PLL_KVCO_SHIFT 15 -#define UTMI_PLL_KVCO_MASK (0x7 << 15) - -#define UTMI_PLL_ICP_SHIFT 12 -#define UTMI_PLL_ICP_MASK (0x7 << 12) - -#define UTMI_PLL_FBDIV_SHIFT 4 -#define UTMI_PLL_FBDIV_MASK (0xFF << 4) - -#define UTMI_PLL_REFDIV_SHIFT 0 -#define UTMI_PLL_REFDIV_MASK (0xF << 0) - -/* For UTMI_TX Register */ -#define UTMI_TX_REG_EXT_FS_RCAL_SHIFT 27 -#define UTMI_TX_REG_EXT_FS_RCAL_MASK (0xf << 27) - -#define UTMI_TX_REG_EXT_FS_RCAL_EN_SHIFT 26 -#define UTMI_TX_REG_EXT_FS_RCAL_EN_MASK (0x1 << 26) - -#define UTMI_TX_TXVDD12_SHIFT 22 -#define UTMI_TX_TXVDD12_MASK (0x3 << 22) - -#define UTMI_TX_CK60_PHSEL_SHIFT 17 -#define UTMI_TX_CK60_PHSEL_MASK (0xf << 17) - -#define UTMI_TX_IMPCAL_VTH_SHIFT 14 -#define UTMI_TX_IMPCAL_VTH_MASK (0x7 << 14) - -#define REG_RCAL_START (0x1 << 12) - -#define UTMI_TX_LOW_VDD_EN_SHIFT 11 - -#define UTMI_TX_AMP_SHIFT 0 -#define UTMI_TX_AMP_MASK (0x7 << 0) - -/* For UTMI_RX Register */ -#define UTMI_REG_SQ_LENGTH_SHIFT 15 -#define UTMI_REG_SQ_LENGTH_MASK (0x3 << 15) - -#define UTMI_RX_SQ_THRESH_SHIFT 4 -#define UTMI_RX_SQ_THRESH_MASK (0xf << 4) - -#define UTMI_OTG_ADDON_OTG_ON (1 << 0) - -/* fsic registers */ -#define FSIC_MISC 0x4 -#define FSIC_INT 0x28 -#define FSIC_CTRL 0x30 - -/* HSIC registers */ -#define HSIC_PAD_CTRL 0x4 - -#define HSIC_CTRL 0x8 -#define HSIC_CTRL_HSIC_ENABLE (1<<7) -#define HSIC_CTRL_PLL_BYPASS (1<<4) - -#define TEST_GRP_0 0xc -#define TEST_GRP_1 0x10 - -#define HSIC_INT 0x14 -#define HSIC_INT_READY_INT_EN (1<<10) -#define HSIC_INT_CONNECT_INT_EN (1<<9) -#define HSIC_INT_CORE_INT_EN (1<<8) -#define HSIC_INT_HS_READY (1<<2) -#define HSIC_INT_CONNECT (1<<1) -#define HSIC_INT_CORE (1<<0) - -#define HSIC_CONFIG 0x18 -#define USBHSIC_CTRL 0x20 - -#define HSIC_USB_CTRL 0x28 -#define HSIC_USB_CTRL_CLKEN 1 -#define HSIC_USB_CLK_PHY 0x0 -#define HSIC_USB_CLK_PMU 0x1 - -#endif /* __ASM_ARCH_PXA_U2O_H */ diff --git a/arch/arm/mach-mmp/sram.c b/arch/arm/mach-mmp/sram.c deleted file mode 100644 index ecc46c31004f..000000000000 --- a/arch/arm/mach-mmp/sram.c +++ /dev/null @@ -1,167 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-mmp/sram.c - * - * based on mach-davinci/sram.c - DaVinci simple SRAM allocator - * - * Copyright (c) 2011 Marvell Semiconductors Inc. - * All Rights Reserved - * - * Add for mmp sram support - Leo Yan <leoy@marvell.com> - */ - -#include <linux/module.h> -#include <linux/mod_devicetable.h> -#include <linux/init.h> -#include <linux/platform_device.h> -#include <linux/io.h> -#include <linux/err.h> -#include <linux/slab.h> -#include <linux/genalloc.h> - -#include <linux/platform_data/dma-mmp_tdma.h> - -struct sram_bank_info { - char *pool_name; - struct gen_pool *gpool; - int granularity; - - phys_addr_t sram_phys; - void __iomem *sram_virt; - u32 sram_size; - - struct list_head node; -}; - -static DEFINE_MUTEX(sram_lock); -static LIST_HEAD(sram_bank_list); - -struct gen_pool *sram_get_gpool(char *pool_name) -{ - struct sram_bank_info *info = NULL; - - if (!pool_name) - return NULL; - - mutex_lock(&sram_lock); - - list_for_each_entry(info, &sram_bank_list, node) - if (!strcmp(pool_name, info->pool_name)) - break; - - mutex_unlock(&sram_lock); - - if (&info->node == &sram_bank_list) - return NULL; - - return info->gpool; -} -EXPORT_SYMBOL(sram_get_gpool); - -static int sram_probe(struct platform_device *pdev) -{ - struct sram_platdata *pdata = pdev->dev.platform_data; - struct sram_bank_info *info; - struct resource *res; - int ret = 0; - - if (!pdata || !pdata->pool_name) - return -ENODEV; - - info = kzalloc(sizeof(*info), GFP_KERNEL); - if (!info) - return -ENOMEM; - - platform_set_drvdata(pdev, info); - - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (res == NULL) { - dev_err(&pdev->dev, "no memory resource defined\n"); - ret = -ENODEV; - goto out; - } - - if (!resource_size(res)) - return 0; - - info->sram_phys = (phys_addr_t)res->start; - info->sram_size = resource_size(res); - info->sram_virt = ioremap(info->sram_phys, info->sram_size); - info->pool_name = kstrdup(pdata->pool_name, GFP_KERNEL); - info->granularity = pdata->granularity; - - info->gpool = gen_pool_create(ilog2(info->granularity), -1); - if (!info->gpool) { - dev_err(&pdev->dev, "create pool failed\n"); - ret = -ENOMEM; - goto create_pool_err; - } - - ret = gen_pool_add_virt(info->gpool, (unsigned long)info->sram_virt, - info->sram_phys, info->sram_size, -1); - if (ret < 0) { - dev_err(&pdev->dev, "add new chunk failed\n"); - ret = -ENOMEM; - goto add_chunk_err; - } - - mutex_lock(&sram_lock); - list_add(&info->node, &sram_bank_list); - mutex_unlock(&sram_lock); - - dev_info(&pdev->dev, "initialized\n"); - return 0; - -add_chunk_err: - gen_pool_destroy(info->gpool); -create_pool_err: - iounmap(info->sram_virt); - kfree(info->pool_name); -out: - kfree(info); - return ret; -} - -static int sram_remove(struct platform_device *pdev) -{ - struct sram_bank_info *info; - - info = platform_get_drvdata(pdev); - - if (info->sram_size) { - mutex_lock(&sram_lock); - list_del(&info->node); - mutex_unlock(&sram_lock); - - gen_pool_destroy(info->gpool); - iounmap(info->sram_virt); - kfree(info->pool_name); - } - - kfree(info); - - return 0; -} - -static const struct platform_device_id sram_id_table[] = { - { "asram", MMP_ASRAM }, - { "isram", MMP_ISRAM }, - { } -}; - -static struct platform_driver sram_driver = { - .probe = sram_probe, - .remove = sram_remove, - .driver = { - .name = "mmp-sram", - }, - .id_table = sram_id_table, -}; - -static int __init sram_init(void) -{ - return platform_driver_register(&sram_driver); -} -core_initcall(sram_init); - -MODULE_LICENSE("GPL"); diff --git a/arch/arm/mach-mmp/teton_bga.c b/arch/arm/mach-mmp/teton_bga.c deleted file mode 100644 index 7111535f325f..000000000000 --- a/arch/arm/mach-mmp/teton_bga.c +++ /dev/null @@ -1,100 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-mmp/teton_bga.c - * - * Support for the Marvell PXA168 Teton BGA Development Platform. - * - * Author: Mark F. Brown <mark.brown314@gmail.com> - * - * This code is based on aspenite.c - */ - -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/gpio.h> -#include <linux/gpio-pxa.h> -#include <linux/input.h> -#include <linux/platform_data/keypad-pxa27x.h> -#include <linux/i2c.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include "addr-map.h" -#include "mfp-pxa168.h" -#include "pxa168.h" -#include "teton_bga.h" -#include "irqs.h" - -#include "common.h" - -static unsigned long teton_bga_pin_config[] __initdata = { - /* UART1 */ - GPIO107_UART1_TXD, - GPIO108_UART1_RXD, - - /* Keypad */ - GPIO109_KP_MKIN1, - GPIO110_KP_MKIN0, - GPIO111_KP_MKOUT7, - GPIO112_KP_MKOUT6, - - /* I2C Bus */ - GPIO105_CI2C_SDA, - GPIO106_CI2C_SCL, - - /* RTC */ - GPIO78_GPIO, -}; - -static struct pxa_gpio_platform_data pxa168_gpio_pdata = { - .irq_base = MMP_GPIO_TO_IRQ(0), -}; - -static unsigned int teton_bga_matrix_key_map[] = { - KEY(0, 6, KEY_ESC), - KEY(0, 7, KEY_ENTER), - KEY(1, 6, KEY_LEFT), - KEY(1, 7, KEY_RIGHT), -}; - -static struct matrix_keymap_data teton_bga_matrix_keymap_data = { - .keymap = teton_bga_matrix_key_map, - .keymap_size = ARRAY_SIZE(teton_bga_matrix_key_map), -}; - -static struct pxa27x_keypad_platform_data teton_bga_keypad_info __initdata = { - .matrix_key_rows = 2, - .matrix_key_cols = 8, - .matrix_keymap_data = &teton_bga_matrix_keymap_data, - .debounce_interval = 30, -}; - -static struct i2c_board_info teton_bga_i2c_info[] __initdata = { - { - I2C_BOARD_INFO("ds1337", 0x68), - .irq = MMP_GPIO_TO_IRQ(RTC_INT_GPIO) - }, -}; - -static void __init teton_bga_init(void) -{ - mfp_config(ARRAY_AND_SIZE(teton_bga_pin_config)); - - /* on-chip devices */ - pxa168_add_uart(1); - pxa168_add_keypad(&teton_bga_keypad_info); - pxa168_add_twsi(0, NULL, ARRAY_AND_SIZE(teton_bga_i2c_info)); - platform_device_add_data(&pxa168_device_gpio, &pxa168_gpio_pdata, - sizeof(struct pxa_gpio_platform_data)); - platform_device_register(&pxa168_device_gpio); -} - -MACHINE_START(TETON_BGA, "PXA168-based Teton BGA Development Platform") - .map_io = mmp_map_io, - .nr_irqs = MMP_NR_IRQS, - .init_irq = pxa168_init_irq, - .init_time = pxa168_timer_init, - .init_machine = teton_bga_init, - .restart = pxa168_restart, -MACHINE_END diff --git a/arch/arm/mach-mmp/teton_bga.h b/arch/arm/mach-mmp/teton_bga.h deleted file mode 100644 index 73050096f0bd..000000000000 --- a/arch/arm/mach-mmp/teton_bga.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Support for the Marvell PXA168 Teton BGA Development Platform. - */ -#ifndef __ASM_MACH_TETON_BGA_H -#define __ASM_MACH_TETON_BGA_H - -/* GPIOs */ -#define MMC_PWENA_GPIO 27 -#define USBHPENB_GPIO 55 -#define RTC_INT_GPIO 78 -#define LCD_VBLK_EN_GPIO 79 -#define LCD_DVDD_EN_GPIO 80 -#define RST_WIFI_GPIO 81 -#define CF_PWEN_GPIO 82 -#define USB_OC_GPIO 83 -#define PWM_GPIO 84 -#define USBHPENA_GPIO 85 -#define TS_INT_GPIO 86 -#define CIR_GPIO 108 - -#endif /* __ASM_MACH_TETON_BGA_H */ diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c index 708816caf859..fcb190826dd1 100644 --- a/arch/arm/mach-mmp/time.c +++ b/arch/arm/mach-mmp/time.c @@ -29,18 +29,13 @@ #include <linux/sched_clock.h> #include <asm/mach/time.h> -#include "addr-map.h" #include "regs-timers.h" -#include "regs-apbc.h" -#include "irqs.h" #include <linux/soc/mmp/cputype.h> -#define TIMERS_VIRT_BASE TIMERS1_VIRT_BASE - #define MAX_DELTA (0xfffffffe) #define MIN_DELTA (16) -static void __iomem *mmp_timer_base = TIMERS_VIRT_BASE; +static void __iomem *mmp_timer_base; /* * Read the timer through the CVWR register. Delay is required after requesting @@ -177,7 +172,7 @@ static void __init timer_config(void) __raw_writel(0x2, mmp_timer_base + TMR_CER); } -void __init mmp_timer_init(int irq, unsigned long rate) +static void __init mmp_timer_init(int irq, unsigned long rate) { timer_config(); diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c deleted file mode 100644 index 345b2e6d5c7e..000000000000 --- a/arch/arm/mach-mmp/ttc_dkb.c +++ /dev/null @@ -1,315 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * linux/arch/arm/mach-mmp/ttc_dkb.c - * - * Support for the Marvell PXA910-based TTC_DKB Development Platform. - */ - -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/platform_device.h> -#include <linux/mtd/mtd.h> -#include <linux/mtd/partitions.h> -#include <linux/mtd/onenand.h> -#include <linux/interrupt.h> -#include <linux/platform_data/pca953x.h> -#include <linux/gpio.h> -#include <linux/gpio-pxa.h> -#include <linux/mfd/88pm860x.h> -#include <linux/platform_data/mv_usb.h> -#include <linux/spi/spi.h> -#include <linux/delay.h> - -#include <asm/mach-types.h> -#include <asm/mach/arch.h> -#include <asm/mach/flash.h> -#include "addr-map.h" -#include "mfp-pxa910.h" -#include "pxa910.h" -#include "irqs.h" -#include "regs-usb.h" - -#include "common.h" - -#define TTCDKB_GPIO_EXT0(x) (MMP_NR_BUILTIN_GPIO + ((x < 0) ? 0 : \ - ((x < 16) ? x : 15))) -#define TTCDKB_GPIO_EXT1(x) (MMP_NR_BUILTIN_GPIO + 16 + ((x < 0) ? 0 : \ - ((x < 16) ? x : 15))) - -/* - * 16 board interrupts -- MAX7312 GPIO expander - * 16 board interrupts -- PCA9575 GPIO expander - * 24 board interrupts -- 88PM860x PMIC - */ -#define TTCDKB_NR_IRQS (MMP_NR_IRQS + 16 + 16 + 24) - -static unsigned long ttc_dkb_pin_config[] __initdata = { - /* UART2 */ - GPIO47_UART2_RXD, - GPIO48_UART2_TXD, - - /* DFI */ - DF_IO0_ND_IO0, - DF_IO1_ND_IO1, - DF_IO2_ND_IO2, - DF_IO3_ND_IO3, - DF_IO4_ND_IO4, - DF_IO5_ND_IO5, - DF_IO6_ND_IO6, - DF_IO7_ND_IO7, - DF_IO8_ND_IO8, - DF_IO9_ND_IO9, - DF_IO10_ND_IO10, - DF_IO11_ND_IO11, - DF_IO12_ND_IO12, - DF_IO13_ND_IO13, - DF_IO14_ND_IO14, - DF_IO15_ND_IO15, - DF_nCS0_SM_nCS2_nCS0, - DF_ALE_SM_WEn_ND_ALE, - DF_CLE_SM_OEn_ND_CLE, - DF_WEn_DF_WEn, - DF_REn_DF_REn, - DF_RDY0_DF_RDY0, -}; - -static struct pxa_gpio_platform_data pxa910_gpio_pdata = { - .irq_base = MMP_GPIO_TO_IRQ(0), -}; - -static struct mtd_partition ttc_dkb_onenand_partitions[] = { - { - .name = "bootloader", - .offset = 0, - .size = SZ_1M, - .mask_flags = MTD_WRITEABLE, - }, { - .name = "reserved", - .offset = MTDPART_OFS_APPEND, - .size = SZ_128K, - .mask_flags = MTD_WRITEABLE, - }, { - .name = "reserved", - .offset = MTDPART_OFS_APPEND, - .size = SZ_8M, - .mask_flags = MTD_WRITEABLE, - }, { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = (SZ_2M + SZ_1M), - .mask_flags = 0, - }, { - .name = "filesystem", - .offset = MTDPART_OFS_APPEND, - .size = SZ_32M + SZ_16M, - .mask_flags = 0, - } -}; - -static struct onenand_platform_data ttc_dkb_onenand_info = { - .parts = ttc_dkb_onenand_partitions, - .nr_parts = ARRAY_SIZE(ttc_dkb_onenand_partitions), -}; - -static struct resource ttc_dkb_resource_onenand[] = { - [0] = { - .start = SMC_CS0_PHYS_BASE, - .end = SMC_CS0_PHYS_BASE + SZ_1M, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device ttc_dkb_device_onenand = { - .name = "onenand-flash", - .id = -1, - .resource = ttc_dkb_resource_onenand, - .num_resources = ARRAY_SIZE(ttc_dkb_resource_onenand), - .dev = { - .platform_data = &ttc_dkb_onenand_info, - }, -}; - -static struct platform_device *ttc_dkb_devices[] = { - &pxa910_device_gpio, - &pxa910_device_rtc, - &ttc_dkb_device_onenand, -}; - -static struct pca953x_platform_data max7312_data[] = { - { - .gpio_base = TTCDKB_GPIO_EXT0(0), - .irq_base = MMP_NR_IRQS, - }, -}; - -static struct pm860x_platform_data ttc_dkb_pm8607_info = { - .irq_base = IRQ_BOARD_START, -}; - -static struct i2c_board_info ttc_dkb_i2c_info[] = { - { - .type = "88PM860x", - .addr = 0x34, - .platform_data = &ttc_dkb_pm8607_info, - .irq = IRQ_PXA910_PMIC_INT, - }, - { - .type = "max7312", - .addr = 0x23, - .irq = MMP_GPIO_TO_IRQ(80), - .platform_data = &max7312_data, - }, -}; - -#if IS_ENABLED(CONFIG_USB_SUPPORT) -#if IS_ENABLED(CONFIG_USB_MV_UDC) || IS_ENABLED(CONFIG_USB_EHCI_MV_U2O) - -static struct mv_usb_platform_data ttc_usb_pdata = { - .vbus = NULL, - .mode = MV_USB_MODE_OTG, - .otg_force_a_bus_req = 1, - .phy_init = pxa_usb_phy_init, - .phy_deinit = pxa_usb_phy_deinit, - .set_vbus = NULL, -}; -#endif -#endif - -#if IS_ENABLED(CONFIG_MTD_NAND_MARVELL) -static struct pxa3xx_nand_platform_data dkb_nand_info = {}; -#endif - -#if IS_ENABLED(CONFIG_MMP_DISP) -/* path config */ -#define CFG_IOPADMODE(iopad) (iopad) /* 0x0 ~ 0xd */ -#define SCLK_SOURCE_SELECT(x) (x << 30) /* 0x0 ~ 0x3 */ -/* link config */ -#define CFG_DUMBMODE(mode) (mode << 28) /* 0x0 ~ 0x6*/ -static struct mmp_mach_path_config dkb_disp_config[] = { - [0] = { - .name = "mmp-parallel", - .overlay_num = 2, - .output_type = PATH_OUT_PARALLEL, - .path_config = CFG_IOPADMODE(0x1) - | SCLK_SOURCE_SELECT(0x1), - .link_config = CFG_DUMBMODE(0x2), - }, -}; - -static struct mmp_mach_plat_info dkb_disp_info = { - .name = "mmp-disp", - .clk_name = "disp0", - .path_num = 1, - .paths = dkb_disp_config, -}; - -static struct mmp_buffer_driver_mach_info dkb_fb_info = { - .name = "mmp-fb", - .path_name = "mmp-parallel", - .overlay_id = 0, - .dmafetch_id = 1, - .default_pixfmt = PIXFMT_RGB565, -}; - -static void dkb_tpo_panel_power(int on) -{ - int err; - u32 spi_reset = mfp_to_gpio(MFP_PIN_GPIO106); - - if (on) { - err = gpio_request(spi_reset, "TPO_LCD_SPI_RESET"); - if (err) { - pr_err("failed to request GPIO for TPO LCD RESET\n"); - return; - } - gpio_direction_output(spi_reset, 0); - udelay(100); - gpio_set_value(spi_reset, 1); - gpio_free(spi_reset); - } else { - err = gpio_request(spi_reset, "TPO_LCD_SPI_RESET"); - if (err) { - pr_err("failed to request LCD RESET gpio\n"); - return; - } - gpio_set_value(spi_reset, 0); - gpio_free(spi_reset); - } -} - -static struct mmp_mach_panel_info dkb_tpo_panel_info = { - .name = "tpo-hvga", - .plat_path_name = "mmp-parallel", - .plat_set_onoff = dkb_tpo_panel_power, -}; - -static struct spi_board_info spi_board_info[] __initdata = { - { - .modalias = "tpo-hvga", - .platform_data = &dkb_tpo_panel_info, - .bus_num = 5, - } -}; - -static void __init add_disp(void) -{ - mmp_register_device(&pxa910_device_disp, - &dkb_disp_info, sizeof(dkb_disp_info)); - spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); - mmp_register_device(&pxa910_device_fb, - &dkb_fb_info, sizeof(dkb_fb_info)); - mmp_register_device(&pxa910_device_panel, - &dkb_tpo_panel_info, sizeof(dkb_tpo_panel_info)); -} -#endif - -static void __init ttc_dkb_init(void) -{ - mfp_config(ARRAY_AND_SIZE(ttc_dkb_pin_config)); - - /* on-chip devices */ - pxa910_add_uart(1); -#if IS_ENABLED(CONFIG_MTD_NAND_MARVELL) - pxa910_add_nand(&dkb_nand_info); -#endif - - /* off-chip devices */ - pxa910_add_twsi(0, NULL, ARRAY_AND_SIZE(ttc_dkb_i2c_info)); - platform_device_add_data(&pxa910_device_gpio, &pxa910_gpio_pdata, - sizeof(struct pxa_gpio_platform_data)); - platform_add_devices(ARRAY_AND_SIZE(ttc_dkb_devices)); - -#if IS_ENABLED(CONFIG_USB_SUPPORT) -#if IS_ENABLED(CONFIG_PHY_PXA_USB) - platform_device_register(&pxa168_device_usb_phy); -#endif - -#if IS_ENABLED(CONFIG_USB_MV_UDC) - pxa168_device_u2o.dev.platform_data = &ttc_usb_pdata; - platform_device_register(&pxa168_device_u2o); -#endif - -#if IS_ENABLED(CONFIG_USB_EHCI_MV_U2O) - pxa168_device_u2oehci.dev.platform_data = &ttc_usb_pdata; - platform_device_register(&pxa168_device_u2oehci); -#endif - -#if IS_ENABLED(CONFIG_USB_MV_OTG) - pxa168_device_u2ootg.dev.platform_data = &ttc_usb_pdata; - platform_device_register(&pxa168_device_u2ootg); -#endif -#endif - -#if IS_ENABLED(CONFIG_MMP_DISP) - add_disp(); -#endif -} - -MACHINE_START(TTC_DKB, "PXA910-based TTC_DKB Development Platform") - .map_io = mmp_map_io, - .nr_irqs = TTCDKB_NR_IRQS, - .init_irq = pxa910_init_irq, - .init_time = pxa910_timer_init, - .init_machine = ttc_dkb_init, - .restart = mmp_restart, -MACHINE_END |