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authorAthira Rajeev <atrajeev@linux.vnet.ibm.com>2020-11-26 11:54:40 -0500
committerMichael Ellerman <mpe@ellerman.id.au>2020-12-04 01:01:28 +1100
commit0263bbb377af0c2d38bc8b2ad2ff147e240094de (patch)
tree44bdc6518ad724cf08b36d2dc8ef0eeea53fa5d1 /arch/arm/mach-mstar
parente924be7b0b0d1f37d0509c854a92c7a71e3cdfe7 (diff)
powerpc/perf: Fix the PMU group constraints for threshold events in power10
The PMU group constraints mask for threshold events covers all thresholding bits which includes threshold control value (start/stop), select value as well as thresh_cmp value (MMCRA[9:18]. In power9, thresh_cmp bits were part of the event code. But in case of power10, thresh_cmp bits are not part of event code due to inclusion of MMCR3 bits. Hence thresh_cmp is not valid for group constraints for power10. Fix the PMU group constraints checking for threshold events in power10 by using constraint mask and value for only threshold control and select bits. Fixes: a64e697cef23 ("powerpc/perf: power10 Performance Monitoring support") Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/1606409684-1589-4-git-send-email-atrajeev@linux.vnet.ibm.com
Diffstat (limited to 'arch/arm/mach-mstar')
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