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| author | Kim Phillips <kim.phillips@amd.com> | 2022-08-08 09:32:33 -0500 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2022-08-08 19:12:17 +0200 |
| commit | e6cfcdda8cbe81eaf821c897369a65fec987b404 (patch) | |
| tree | 8e6b4e846ddbf6f7d0919a3a210042df92984865 /arch/arm/mach-mvebu/platsmp.c | |
| parent | de979c83574abf6e78f3fa65b716515c91b2613d (diff) | |
x86/bugs: Enable STIBP for IBPB mitigated RETBleed
AMD's "Technical Guidance for Mitigating Branch Type Confusion,
Rev. 1.0 2022-07-12" whitepaper, under section 6.1.2 "IBPB On
Privileged Mode Entry / SMT Safety" says:
Similar to the Jmp2Ret mitigation, if the code on the sibling thread
cannot be trusted, software should set STIBP to 1 or disable SMT to
ensure SMT safety when using this mitigation.
So, like already being done for retbleed=unret, and now also for
retbleed=ibpb, force STIBP on machines that have it, and report its SMT
vulnerability status accordingly.
[ bp: Remove the "we" and remove "[AMD]" applicability parameter which
doesn't work here. ]
Fixes: 3ebc17006888 ("x86/bugs: Add retbleed=ibpb")
Signed-off-by: Kim Phillips <kim.phillips@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: stable@vger.kernel.org # 5.10, 5.15, 5.19
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
Link: https://lore.kernel.org/r/20220804192201.439596-1-kim.phillips@amd.com
Diffstat (limited to 'arch/arm/mach-mvebu/platsmp.c')
0 files changed, 0 insertions, 0 deletions