diff options
| author | Arnd Bergmann <arnd@arndb.de> | 2023-01-04 13:56:57 +0100 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2023-01-12 10:53:11 +0100 |
| commit | 76873bb5b89792c9dd6873c1b5567d3787d59b68 (patch) | |
| tree | 148080d4b1ff3a3b422bf3ceb0c211157b5c6ef5 /arch/arm/mach-omap1/hardware.h | |
| parent | 9a99b142f7ef23bc3cb4cb82bf7f5abc173b11ca (diff) | |
ARM: omap1: remove unused omapxxxx.h headers
The only bit that is still in use is the OMAP_IH2_*_*
macros, so move them into the existing hardware.h file.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-omap1/hardware.h')
| -rw-r--r-- | arch/arm/mach-omap1/hardware.h | 48 |
1 files changed, 44 insertions, 4 deletions
diff --git a/arch/arm/mach-omap1/hardware.h b/arch/arm/mach-omap1/hardware.h index c228234a1ed4..0aa571c9e0eb 100644 --- a/arch/arm/mach-omap1/hardware.h +++ b/arch/arm/mach-omap1/hardware.h @@ -114,6 +114,10 @@ static inline u32 omap_cs3_phys(void) #define OMAP_IH1_BASE 0xfffecb00 #define OMAP_IH2_BASE 0xfffe0000 +#define OMAP_IH2_0_BASE (0xfffe0000) +#define OMAP_IH2_1_BASE (0xfffe0100) +#define OMAP_IH2_2_BASE (0xfffe0200) +#define OMAP_IH2_3_BASE (0xfffe0300) #define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00) #define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04) @@ -131,6 +135,38 @@ static inline u32 omap_cs3_phys(void) #define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c) #define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c) +#define OMAP_IH2_0_ITR (OMAP_IH2_0_BASE + 0x00) +#define OMAP_IH2_0_MIR (OMAP_IH2_0_BASE + 0x04) +#define OMAP_IH2_0_SIR_IRQ (OMAP_IH2_0_BASE + 0x10) +#define OMAP_IH2_0_SIR_FIQ (OMAP_IH2_0_BASE + 0x14) +#define OMAP_IH2_0_CONTROL (OMAP_IH2_0_BASE + 0x18) +#define OMAP_IH2_0_ILR0 (OMAP_IH2_0_BASE + 0x1c) +#define OMAP_IH2_0_ISR (OMAP_IH2_0_BASE + 0x9c) + +#define OMAP_IH2_1_ITR (OMAP_IH2_1_BASE + 0x00) +#define OMAP_IH2_1_MIR (OMAP_IH2_1_BASE + 0x04) +#define OMAP_IH2_1_SIR_IRQ (OMAP_IH2_1_BASE + 0x10) +#define OMAP_IH2_1_SIR_FIQ (OMAP_IH2_1_BASE + 0x14) +#define OMAP_IH2_1_CONTROL (OMAP_IH2_1_BASE + 0x18) +#define OMAP_IH2_1_ILR1 (OMAP_IH2_1_BASE + 0x1c) +#define OMAP_IH2_1_ISR (OMAP_IH2_1_BASE + 0x9c) + +#define OMAP_IH2_2_ITR (OMAP_IH2_2_BASE + 0x00) +#define OMAP_IH2_2_MIR (OMAP_IH2_2_BASE + 0x04) +#define OMAP_IH2_2_SIR_IRQ (OMAP_IH2_2_BASE + 0x10) +#define OMAP_IH2_2_SIR_FIQ (OMAP_IH2_2_BASE + 0x14) +#define OMAP_IH2_2_CONTROL (OMAP_IH2_2_BASE + 0x18) +#define OMAP_IH2_2_ILR2 (OMAP_IH2_2_BASE + 0x1c) +#define OMAP_IH2_2_ISR (OMAP_IH2_2_BASE + 0x9c) + +#define OMAP_IH2_3_ITR (OMAP_IH2_3_BASE + 0x00) +#define OMAP_IH2_3_MIR (OMAP_IH2_3_BASE + 0x04) +#define OMAP_IH2_3_SIR_IRQ (OMAP_IH2_3_BASE + 0x10) +#define OMAP_IH2_3_SIR_FIQ (OMAP_IH2_3_BASE + 0x14) +#define OMAP_IH2_3_CONTROL (OMAP_IH2_3_BASE + 0x18) +#define OMAP_IH2_3_ILR3 (OMAP_IH2_3_BASE + 0x1c) +#define OMAP_IH2_3_ISR (OMAP_IH2_3_BASE + 0x9c) + #define IRQ_ITR_REG_OFFSET 0x00 #define IRQ_MIR_REG_OFFSET 0x04 #define IRQ_SIR_IRQ_REG_OFFSET 0x10 @@ -184,12 +220,16 @@ static inline u32 omap_cs3_phys(void) /* * --------------------------------------------------------------------------- - * Processor specific defines + * DSP * --------------------------------------------------------------------------- */ -#include "omap7xx.h" -#include "omap1510.h" -#include "omap16xx.h" +#define OMAP1_DSP_BASE 0xE0000000 +#define OMAP1_DSP_SIZE 0x28000 +#define OMAP1_DSP_START 0xE0000000 + +#define OMAP1_DSPREG_BASE 0xE1000000 +#define OMAP1_DSPREG_SIZE SZ_128K +#define OMAP1_DSPREG_START 0xE1000000 #endif /* __ASM_ARCH_OMAP_HARDWARE_H */ |