diff options
| author | Olof Johansson <olof@lixom.net> | 2012-12-12 16:09:22 -0800 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2012-12-12 16:10:00 -0800 |
| commit | 4a76411ea3f1da9032e031f8fff8894b97d141b2 (patch) | |
| tree | 59976175d70b6e08aacd4abf7090919d3b78fc29 /arch/arm/mach-omap2/prm-regbits-34xx.h | |
| parent | 5c1af2a7011bf719807de360cb64c2f610269a38 (diff) | |
| parent | fb6842a7bc44bf719bfe85d5819a153d7c215510 (diff) | |
ARM: arm-soc: Merge branch 'next/clk' into next/pm
Merge together a couple of the smaller pm/clock branches into one.
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/mach-omap2/prm-regbits-34xx.h')
| -rw-r--r-- | arch/arm/mach-omap2/prm-regbits-34xx.h | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h index 64c087af6a8b..b0a2142eeb91 100644 --- a/arch/arm/mach-omap2/prm-regbits-34xx.h +++ b/arch/arm/mach-omap2/prm-regbits-34xx.h @@ -14,7 +14,7 @@ #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H -#include "prm2xxx_3xxx.h" +#include "prm3xxx.h" /* Shared register bits */ @@ -384,6 +384,7 @@ /* PRM_CLKSEL */ #define OMAP3430_SYS_CLKIN_SEL_SHIFT 0 #define OMAP3430_SYS_CLKIN_SEL_MASK (0x7 << 0) +#define OMAP3430_SYS_CLKIN_SEL_WIDTH 3 /* PRM_CLKOUT_CTRL */ #define OMAP3430_CLKOUT_EN_MASK (1 << 7) @@ -509,15 +510,25 @@ #define OMAP3430_RSTTIME1_MASK (0xff << 0) /* PRM_RSTST */ +#define OMAP3430_ICECRUSHER_RST_SHIFT 10 #define OMAP3430_ICECRUSHER_RST_MASK (1 << 10) +#define OMAP3430_ICEPICK_RST_SHIFT 9 #define OMAP3430_ICEPICK_RST_MASK (1 << 9) +#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_SHIFT 8 #define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_MASK (1 << 8) +#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_SHIFT 7 #define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_MASK (1 << 7) +#define OMAP3430_EXTERNAL_WARM_RST_SHIFT 6 #define OMAP3430_EXTERNAL_WARM_RST_MASK (1 << 6) +#define OMAP3430_SECURE_WD_RST_SHIFT 5 #define OMAP3430_SECURE_WD_RST_MASK (1 << 5) +#define OMAP3430_MPU_WD_RST_SHIFT 4 #define OMAP3430_MPU_WD_RST_MASK (1 << 4) +#define OMAP3430_SECURITY_VIOL_RST_SHIFT 3 #define OMAP3430_SECURITY_VIOL_RST_MASK (1 << 3) +#define OMAP3430_GLOBAL_SW_RST_SHIFT 1 #define OMAP3430_GLOBAL_SW_RST_MASK (1 << 1) +#define OMAP3430_GLOBAL_COLD_RST_SHIFT 0 #define OMAP3430_GLOBAL_COLD_RST_MASK (1 << 0) /* PRM_VOLTCTRL */ |