diff options
| author | Kever Yang <kever.yang@rock-chips.com> | 2014-10-15 10:23:03 -0700 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2014-11-05 22:18:40 +0100 |
| commit | 3ee851e212d0bb6be8c462059fba74ce2e3f6064 (patch) | |
| tree | abf38ddb77760e6390ed3982f4067500cfd75a37 /arch/arm/mach-rockchip/headsmp.S | |
| parent | 6de2d21adaf05b7a456077625b6e311feabd3718 (diff) | |
ARM: rockchip: add basic smp support for rk3288
This patch add basic rk3288 smp support.
Only cortex-A9 need invalid L1, A7/A12/A15/A17 should not invalid L1, since
for A7/A12/A15, the invalidation would be taken as clean and invalidate.
If you use the software manual invalidation instead of hardware invalidation
(assert l1/l2rstdisable during reset) after reset, there is tiny change that
some cachelines would be in dirty and valid state after reset(since the ram
content would be random value after reset), then the unexpected clean might
lead to system crash.
It is a known issue for the A12/A17 MPCore multiprocessor that the active
processors might be stalled when the individual processor is powered down,
we can avoid this prolbem by softreset the processor before power it down.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm/mach-rockchip/headsmp.S')
| -rw-r--r-- | arch/arm/mach-rockchip/headsmp.S | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/mach-rockchip/headsmp.S b/arch/arm/mach-rockchip/headsmp.S index 73206e360e31..46c22dedf632 100644 --- a/arch/arm/mach-rockchip/headsmp.S +++ b/arch/arm/mach-rockchip/headsmp.S @@ -16,7 +16,10 @@ #include <linux/init.h> ENTRY(rockchip_secondary_startup) - bl v7_invalidate_l1 + mrc p15, 0, r0, c0, c0, 0 @ read main ID register + ldr r1, =0x00000c09 @ Cortex-A9 primary part number + teq r0, r1 + beq v7_invalidate_l1 b secondary_startup ENDPROC(rockchip_secondary_startup) |