diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2013-11-11 17:05:37 +0900 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2013-11-11 17:05:37 +0900 |
commit | 53575aa99dc1584484b99c8173042d8370f6ed88 (patch) | |
tree | 06fd13c8847c1e97cd5080ea31cec47c4ad54963 /arch/arm/mach-s3c24xx/common.c | |
parent | d5aabbcaee6bb5fb57ea8c67714516af4d8238ce (diff) | |
parent | 3316dee245ef297155fa45b8d14263dfd6a9164b (diff) |
Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM driver updates from Olof Johansson:
"Updates of SoC-near drivers and other driver updates that makes more
sense to take through our tree. In this case it's involved:
- Some Davinci driver updates that has required corresponding
platform code changes (gpio mostly)
- CCI bindings and a few driver updates
- Marvell mvebu patches for PCI MSI support (could have gone through
the PCI tree for this release, but they were acked by Bjorn for
3.12 so we kept them through arm-soc).
- Marvell dove switch-over to DT-based PCIe configuration
- Misc updates for Samsung platform dmaengine drivers"
* tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (32 commits)
ARM: S3C24XX: add dma pdata for s3c2410, s3c2440 and s3c2442
dmaengine: s3c24xx-dma: add support for the s3c2410 type of controller
ARM: S3C24XX: Fix possible dma selection warning
PCI: mvebu: make local functions static
PCI: mvebu: add I/O access wrappers
PCI: mvebu: Dynamically detect if the PEX link is up to enable hot plug
ARM: mvebu: fix gated clock documentation
ARM: dove: remove legacy pcie and clock init
ARM: dove: switch to DT probed mbus address windows
ARM: SAMSUNG: set s3c24xx_dma_filter for s3c64xx-spi0 device
ARM: S3C24XX: add platform-devices for new dma driver for s3c2412 and s3c2443
dmaengine: add driver for Samsung s3c24xx SoCs
ARM: S3C24XX: number the dma clocks
PCI: mvebu: add support for Marvell Dove SoCs
PCI: mvebu: add support for reset on GPIO
PCI: mvebu: remove subsys_initcall
PCI: mvebu: increment nports only for registered ports
PCI: mvebu: move clock enable before register access
PCI: mvebu: add support for MSI
irqchip: armada-370-xp: implement MSI support
...
Diffstat (limited to 'arch/arm/mach-s3c24xx/common.c')
-rw-r--r-- | arch/arm/mach-s3c24xx/common.c | 206 |
1 files changed, 206 insertions, 0 deletions
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c index 457261c98433..4adaa4b43ffe 100644 --- a/arch/arm/mach-s3c24xx/common.c +++ b/arch/arm/mach-s3c24xx/common.c @@ -31,6 +31,7 @@ #include <linux/platform_device.h> #include <linux/delay.h> #include <linux/io.h> +#include <linux/platform_data/dma-s3c24xx.h> #include <mach/hardware.h> #include <mach/regs-clock.h> @@ -44,6 +45,7 @@ #include <mach/regs-gpio.h> #include <plat/regs-serial.h> +#include <mach/dma.h> #include <plat/cpu.h> #include <plat/devs.h> @@ -329,3 +331,207 @@ void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk, clk_p.rate = pclk; clk_f.rate = fclk; } + +#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \ + defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442) +static struct resource s3c2410_dma_resource[] = { + [0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA), + [1] = DEFINE_RES_IRQ(IRQ_DMA0), + [2] = DEFINE_RES_IRQ(IRQ_DMA1), + [3] = DEFINE_RES_IRQ(IRQ_DMA2), + [4] = DEFINE_RES_IRQ(IRQ_DMA3), +}; +#endif + +#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2442) +static struct s3c24xx_dma_channel s3c2410_dma_channels[DMACH_MAX] = { + [DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), }, + [DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), }, + [DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) | + S3C24XX_DMA_CHANREQ(2, 2) | + S3C24XX_DMA_CHANREQ(1, 3), + }, + [DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), }, + [DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), }, + [DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), }, + [DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), }, + [DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), }, + [DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) | + S3C24XX_DMA_CHANREQ(3, 2) | + S3C24XX_DMA_CHANREQ(3, 3), + }, + [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) | + S3C24XX_DMA_CHANREQ(1, 2), + }, + [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 2), }, + [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), }, + [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), }, + [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), }, + [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), }, +}; + +static struct s3c24xx_dma_platdata s3c2410_dma_platdata = { + .num_phy_channels = 4, + .channels = s3c2410_dma_channels, + .num_channels = DMACH_MAX, +}; + +struct platform_device s3c2410_device_dma = { + .name = "s3c2410-dma", + .id = 0, + .num_resources = ARRAY_SIZE(s3c2410_dma_resource), + .resource = s3c2410_dma_resource, + .dev = { + .platform_data = &s3c2410_dma_platdata, + }, +}; +#endif + +#ifdef CONFIG_CPU_S3C2412 +static struct s3c24xx_dma_channel s3c2412_dma_channels[DMACH_MAX] = { + [DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 }, + [DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 }, + [DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 }, + [DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 }, + [DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 }, + [DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 }, + [DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 }, + [DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 }, + [DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 }, + [DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 }, + [DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 }, + [DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 }, + [DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 }, + [DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 }, + [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 }, + [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 }, + [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, 13 }, + [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, 14 }, + [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, 15 }, + [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, 16 }, +}; + +static struct s3c24xx_dma_platdata s3c2412_dma_platdata = { + .num_phy_channels = 4, + .channels = s3c2412_dma_channels, + .num_channels = DMACH_MAX, +}; + +struct platform_device s3c2412_device_dma = { + .name = "s3c2412-dma", + .id = 0, + .num_resources = ARRAY_SIZE(s3c2410_dma_resource), + .resource = s3c2410_dma_resource, + .dev = { + .platform_data = &s3c2412_dma_platdata, + }, +}; +#endif + +#if defined(CONFIG_CPU_S3C2440) +static struct s3c24xx_dma_channel s3c2440_dma_channels[DMACH_MAX] = { + [DMACH_XD0] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 0), }, + [DMACH_XD1] = { S3C24XX_DMA_AHB, true, S3C24XX_DMA_CHANREQ(0, 1), }, + [DMACH_SDI] = { S3C24XX_DMA_APB, false, S3C24XX_DMA_CHANREQ(2, 0) | + S3C24XX_DMA_CHANREQ(6, 1) | + S3C24XX_DMA_CHANREQ(2, 2) | + S3C24XX_DMA_CHANREQ(1, 3), + }, + [DMACH_SPI0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 1), }, + [DMACH_SPI1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 3), }, + [DMACH_UART0] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 0), }, + [DMACH_UART1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(1, 1), }, + [DMACH_UART2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(0, 3), }, + [DMACH_TIMER] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(3, 0) | + S3C24XX_DMA_CHANREQ(3, 2) | + S3C24XX_DMA_CHANREQ(3, 3), + }, + [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(2, 1) | + S3C24XX_DMA_CHANREQ(1, 2), + }, + [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 0) | + S3C24XX_DMA_CHANREQ(0, 2), + }, + [DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 0) | + S3C24XX_DMA_CHANREQ(5, 2), + }, + [DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(5, 1) | + S3C24XX_DMA_CHANREQ(6, 3), + }, + [DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(6, 2) | + S3C24XX_DMA_CHANREQ(5, 3), + }, + [DMACH_USB_EP1] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 0), }, + [DMACH_USB_EP2] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 1), }, + [DMACH_USB_EP3] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 2), }, + [DMACH_USB_EP4] = { S3C24XX_DMA_APB, true, S3C24XX_DMA_CHANREQ(4, 3), }, +}; + +static struct s3c24xx_dma_platdata s3c2440_dma_platdata = { + .num_phy_channels = 4, + .channels = s3c2440_dma_channels, + .num_channels = DMACH_MAX, +}; + +struct platform_device s3c2440_device_dma = { + .name = "s3c2410-dma", + .id = 0, + .num_resources = ARRAY_SIZE(s3c2410_dma_resource), + .resource = s3c2410_dma_resource, + .dev = { + .platform_data = &s3c2440_dma_platdata, + }, +}; +#endif + +#if defined(CONFIG_CPUS_3C2443) || defined(CONFIG_CPU_S3C2416) +static struct resource s3c2443_dma_resource[] = { + [0] = DEFINE_RES_MEM(S3C24XX_PA_DMA, S3C24XX_SZ_DMA), + [1] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA0), + [2] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA1), + [3] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA2), + [4] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA3), + [5] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA4), + [6] = DEFINE_RES_IRQ(IRQ_S3C2443_DMA5), +}; + +static struct s3c24xx_dma_channel s3c2443_dma_channels[DMACH_MAX] = { + [DMACH_XD0] = { S3C24XX_DMA_AHB, true, 17 }, + [DMACH_XD1] = { S3C24XX_DMA_AHB, true, 18 }, + [DMACH_SDI] = { S3C24XX_DMA_APB, false, 10 }, + [DMACH_SPI0_RX] = { S3C24XX_DMA_APB, true, 1 }, + [DMACH_SPI0_TX] = { S3C24XX_DMA_APB, true, 0 }, + [DMACH_SPI1_RX] = { S3C24XX_DMA_APB, true, 3 }, + [DMACH_SPI1_TX] = { S3C24XX_DMA_APB, true, 2 }, + [DMACH_UART0] = { S3C24XX_DMA_APB, true, 19 }, + [DMACH_UART1] = { S3C24XX_DMA_APB, true, 21 }, + [DMACH_UART2] = { S3C24XX_DMA_APB, true, 23 }, + [DMACH_UART3] = { S3C24XX_DMA_APB, true, 25 }, + [DMACH_UART0_SRC2] = { S3C24XX_DMA_APB, true, 20 }, + [DMACH_UART1_SRC2] = { S3C24XX_DMA_APB, true, 22 }, + [DMACH_UART2_SRC2] = { S3C24XX_DMA_APB, true, 24 }, + [DMACH_UART3_SRC2] = { S3C24XX_DMA_APB, true, 26 }, + [DMACH_TIMER] = { S3C24XX_DMA_APB, true, 9 }, + [DMACH_I2S_IN] = { S3C24XX_DMA_APB, true, 5 }, + [DMACH_I2S_OUT] = { S3C24XX_DMA_APB, true, 4 }, + [DMACH_PCM_IN] = { S3C24XX_DMA_APB, true, 28 }, + [DMACH_PCM_OUT] = { S3C24XX_DMA_APB, true, 27 }, + [DMACH_MIC_IN] = { S3C24XX_DMA_APB, true, 29 }, +}; + +static struct s3c24xx_dma_platdata s3c2443_dma_platdata = { + .num_phy_channels = 6, + .channels = s3c2443_dma_channels, + .num_channels = DMACH_MAX, +}; + +struct platform_device s3c2443_device_dma = { + .name = "s3c2443-dma", + .id = 0, + .num_resources = ARRAY_SIZE(s3c2443_dma_resource), + .resource = s3c2443_dma_resource, + .dev = { + .platform_data = &s3c2443_dma_platdata, + }, +}; +#endif |