diff options
| author | Ingo Molnar <mingo@elte.hu> | 2011-06-03 10:41:03 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2011-06-03 10:41:08 +0200 |
| commit | 27eb4a1e4a56afacb0540c24084b9e0342f9956b (patch) | |
| tree | 85bd26c6d7cdee8ee4c2d69d195f3e2bdbbc54fe /arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h | |
| parent | 64ce312618ef0e11d88def80effcefd1b59fdb1e (diff) | |
| parent | 55922c9d1b84b89cb946c777fddccb3247e7df2c (diff) | |
Merge commit 'v3.0-rc1' into perf/core
Merge reason: merge in the latest fixes.
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h')
| -rw-r--r-- | arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h | 44 |
1 files changed, 0 insertions, 44 deletions
diff --git a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h b/arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h deleted file mode 100644 index f057adb627dd..000000000000 --- a/arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h +++ /dev/null @@ -1,44 +0,0 @@ -/* linux/arch/arm/mach-s3c64xx/include/mach/gpio-bank-e.h - * - * Copyright 2008 Openmoko, Inc. - * Copyright 2008 Simtec Electronics - * Ben Dooks <ben@simtec.co.uk> - * http://armlinux.simtec.co.uk/ - * - * GPIO Bank E register and configuration definitions - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. -*/ - -#define S3C64XX_GPECON (S3C64XX_GPE_BASE + 0x00) -#define S3C64XX_GPEDAT (S3C64XX_GPE_BASE + 0x04) -#define S3C64XX_GPEPUD (S3C64XX_GPE_BASE + 0x08) -#define S3C64XX_GPECONSLP (S3C64XX_GPE_BASE + 0x0c) -#define S3C64XX_GPEPUDSLP (S3C64XX_GPE_BASE + 0x10) - -#define S3C64XX_GPE_CONMASK(__gpio) (0xf << ((__gpio) * 4)) -#define S3C64XX_GPE_INPUT(__gpio) (0x0 << ((__gpio) * 4)) -#define S3C64XX_GPE_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) - -#define S3C64XX_GPE0_PCM1_SCLK (0x02 << 0) -#define S3C64XX_GPE0_I2S1_CLK (0x03 << 0) -#define S3C64XX_GPE0_AC97_BITCLK (0x04 << 0) - -#define S3C64XX_GPE1_PCM1_EXTCLK (0x02 << 4) -#define S3C64XX_GPE1_I2S1_CDCLK (0x03 << 4) -#define S3C64XX_GPE1_AC97_nRESET (0x04 << 4) - -#define S3C64XX_GPE2_PCM1_FSYNC (0x02 << 8) -#define S3C64XX_GPE2_I2S1_LRCLK (0x03 << 8) -#define S3C64XX_GPE2_AC97_SYNC (0x04 << 8) - -#define S3C64XX_GPE3_PCM1_SIN (0x02 << 12) -#define S3C64XX_GPE3_I2S1_DI (0x03 << 12) -#define S3C64XX_GPE3_AC97_SDI (0x04 << 12) - -#define S3C64XX_GPE4_PCM1_SOUT (0x02 << 16) -#define S3C64XX_GPE4_I2S1_D0 (0x03 << 16) -#define S3C64XX_GPE4_AC97_SDO (0x04 << 16) - |