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authorRussell King <rmk+kernel@armlinux.org.uk>2016-08-31 08:49:54 +0100
committerRussell King (Oracle) <rmk+kernel@armlinux.org.uk>2022-05-23 15:58:13 +0100
commit359ec1380589fd7f736b36941ccb85a98b3fb76a (patch)
treeb1f9f5d6ff6f6fb07efbdfb9b316f8e0feaae0a0 /arch/arm/mach-sa1100/nanoengine.h
parentb9bb0deeb016b066b1bd47eb3ec8b49d3cbc1eb7 (diff)
ARM: sa1100/nanoengine: move nanoengine header file
Nothing outside arch/arm/mach-sa1100 needs the nanoengine header file, so move it into that directory. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'arch/arm/mach-sa1100/nanoengine.h')
-rw-r--r--arch/arm/mach-sa1100/nanoengine.h37
1 files changed, 37 insertions, 0 deletions
diff --git a/arch/arm/mach-sa1100/nanoengine.h b/arch/arm/mach-sa1100/nanoengine.h
new file mode 100644
index 000000000000..8c9513b03512
--- /dev/null
+++ b/arch/arm/mach-sa1100/nanoengine.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * arch/arm/mach-sa1100/include/mach/nanoengine.h
+ *
+ * This file contains the hardware specific definitions for nanoEngine.
+ * Only include this file from SA1100-specific files.
+ *
+ * Copyright (C) 2010 Marcelo Roberto Jimenez <mroberto@cpti.cetuc.puc-rio.br>
+ */
+#ifndef __ASM_ARCH_NANOENGINE_H
+#define __ASM_ARCH_NANOENGINE_H
+
+#include <mach/irqs.h>
+
+#define NANOENGINE_IRQ_GPIO_PCI IRQ_GPIO0
+
+/*
+ * nanoEngine Memory Map:
+ *
+ * 0000.0000 - 003F.0000 - 4 MB Flash
+ * C000.0000 - C1FF.FFFF - 32 MB SDRAM
+ * 1860.0000 - 186F.FFFF - 1 MB Internal PCI Memory Read/Write
+ * 18A1.0000 - 18A1.FFFF - 64 KB Internal PCI Config Space
+ * 4000.0000 - 47FF.FFFF - 128 MB External Bus I/O - Multiplexed Mode
+ * 4800.0000 - 4FFF.FFFF - 128 MB External Bus I/O - Non-Multiplexed Mode
+ *
+ */
+
+#define NANO_PCI_MEM_RW_PHYS 0x18600000
+#define NANO_PCI_MEM_RW_VIRT 0xf1000000
+#define NANO_PCI_MEM_RW_SIZE SZ_1M
+#define NANO_PCI_CONFIG_SPACE_PHYS 0x18A10000
+#define NANO_PCI_CONFIG_SPACE_VIRT 0xf2000000
+#define NANO_PCI_CONFIG_SPACE_SIZE SZ_64K
+
+#endif
+