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authorStephen Warren <swarren@nvidia.com>2012-04-20 16:58:18 -0600
committerStephen Warren <swarren@nvidia.com>2012-04-25 15:22:09 -0600
commit7ff4db0967bd7d617c77dc5a66c0d95166277817 (patch)
tree43328bab20e3fe0e2c0a613b5860eabd4802342f /arch/arm/mach-tegra/board-paz00.c
parent60f975b98cf41476ba0e156f7523b197b046cf2b (diff)
ARM: tegra: fix pclk rate
Commit 40f9cf0 "ARM: tegra: reparent sclk to pll_c_out1" changed the rate of hclk. Since pclk is derived from that, and only has integer dividers, the pclk rate needs to change in the same fashion, from 54MHz to 60MHz. Signed-off-by: Stephen Warren <swarren@nvidia.com>
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