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authorColin Cross <ccross@android.com>2011-02-09 22:17:17 -0800
committerColin Cross <ccross@android.com>2011-02-09 22:18:30 -0800
commit26d902c0c6d6254f471663305d48b63f027ddb0c (patch)
tree70cd9d540a6e9ab7b54d98cb4f89b00f34e0772a /arch/arm/mach-tegra/irq.c
parent3524b70ef3336a4f1351a489e83894b88106ab7c (diff)
ARM: tegra: irq: Implement retrigger
Signed-off-by: Colin Cross <ccross@android.com>
Diffstat (limited to 'arch/arm/mach-tegra/irq.c')
-rw-r--r--arch/arm/mach-tegra/irq.c17
1 files changed, 16 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 7fb73490eb55..dfbc219ea492 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -48,6 +48,7 @@ static u32 tegra_lp0_wake_level_any;
static void (*tegra_gic_mask_irq)(struct irq_data *d);
static void (*tegra_gic_unmask_irq)(struct irq_data *d);
+static void (*tegra_gic_ack_irq)(struct irq_data *d);
/* ensures that sufficient time is passed for a register write to
* serialize into the 32KHz domain */
@@ -112,10 +113,24 @@ static void tegra_unmask(struct irq_data *d)
tegra_legacy_unmask_irq(d->irq);
}
+static void tegra_ack(struct irq_data *d)
+{
+ tegra_legacy_force_irq_clr(d->irq);
+ tegra_gic_ack_irq(d);
+}
+
+static int tegra_retrigger(struct irq_data *d)
+{
+ tegra_legacy_force_irq_set(d->irq);
+ return 1;
+}
+
static struct irq_chip tegra_irq = {
.name = "PPI",
+ .irq_ack = tegra_ack,
.irq_mask = tegra_mask,
.irq_unmask = tegra_unmask,
+ .irq_retrigger = tegra_retrigger,
};
void __init tegra_init_irq(void)
@@ -132,7 +147,7 @@ void __init tegra_init_irq(void)
gic = get_irq_chip(29);
tegra_gic_unmask_irq = gic->irq_unmask;
tegra_gic_mask_irq = gic->irq_mask;
- tegra_irq.irq_ack = gic->irq_ack;
+ tegra_gic_ack_irq = gic->irq_ack;
#ifdef CONFIG_SMP
tegra_irq.irq_set_affinity = gic->irq_set_affinity;
#endif