diff options
| author | Joseph Lo <josephl@nvidia.com> | 2013-08-12 17:40:00 +0800 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2013-08-12 12:22:38 -0600 |
| commit | 5b795d051c61862cebf4f1d55edab6e9b3383b44 (patch) | |
| tree | c91e4a8aa4d89e65753ae383d9c9b3b99022f268 /arch/arm/mach-tegra/reset.c | |
| parent | 20984c44b5a08620778ea14fa5807489170fd5ca (diff) | |
ARM: tegra: add common resume handling code for LP1 resuming
Add support to the Tegra CPU reset vector to detect whether the CPU is
resuming from LP1 suspend state. If it is, branch to the LP1-specific
resume code.
When Tegra enters the LP1 suspend state, the SDRAM controller is placed
into a self-refresh state. For this reason, we must place the LP1 resume
code into IRAM, so that it is accessible before SDRAM access has been
re-enabled.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/reset.c')
| -rw-r--r-- | arch/arm/mach-tegra/reset.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c index 1ac434e0068f..fd0bbf8a6c94 100644 --- a/arch/arm/mach-tegra/reset.c +++ b/arch/arm/mach-tegra/reset.c @@ -81,6 +81,8 @@ void __init tegra_cpu_reset_handler_init(void) #endif #ifdef CONFIG_PM_SLEEP + __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP1] = + TEGRA_IRAM_CODE_AREA; __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] = virt_to_phys((void *)tegra_resume); #endif |