diff options
| author | Michal Simek <michal.simek@xilinx.com> | 2013-03-20 13:50:12 +0100 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2013-04-04 09:24:00 +0200 |
| commit | aa7eb2bb4e4a22e41bbe4612ff46e5885b13c33e (patch) | |
| tree | ef3f5e0578ee98f1e95b686796a64a80807ef795 /arch/arm/mach-zynq/slcr.c | |
| parent | 2f34e0a58f34db094257e33b461d58b578004b67 (diff) | |
arm: zynq: Add smp support
Zynq is dual core Cortex A9 which starts always
at zero. Using simple trampoline ensure long jump
to secondary_startup code.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Diffstat (limited to 'arch/arm/mach-zynq/slcr.c')
| -rw-r--r-- | arch/arm/mach-zynq/slcr.c | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c index d58c9964e883..c70969b9c258 100644 --- a/arch/arm/mach-zynq/slcr.c +++ b/arch/arm/mach-zynq/slcr.c @@ -33,6 +33,11 @@ #define SLCR_UNLOCK 0x8 /* SCLR unlock register */ #define SLCR_PS_RST_CTRL_OFFSET 0x200 /* PS Software Reset Control */ + +#define SLCR_A9_CPU_CLKSTOP 0x10 +#define SLCR_A9_CPU_RST 0x1 + +#define SLCR_A9_CPU_RST_CTRL 0x244 /* CPU Software Reset Control */ #define SLCR_REBOOT_STATUS 0x258 /* PS Reboot Status */ void __iomem *zynq_slcr_base; @@ -62,6 +67,30 @@ void zynq_slcr_system_reset(void) } /** + * zynq_slcr_cpu_start - Start cpu + * @cpu: cpu number + */ +void zynq_slcr_cpu_start(int cpu) +{ + /* enable CPUn */ + writel(SLCR_A9_CPU_CLKSTOP << cpu, + zynq_slcr_base + SLCR_A9_CPU_RST_CTRL); + /* enable CLK for CPUn */ + writel(0x0 << cpu, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL); +} + +/** + * zynq_slcr_cpu_stop - Stop cpu + * @cpu: cpu number + */ +void zynq_slcr_cpu_stop(int cpu) +{ + /* stop CLK and reset CPUn */ + writel((SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu, + zynq_slcr_base + SLCR_A9_CPU_RST_CTRL); +} + +/** * zynq_slcr_init * Returns 0 on success, negative errno otherwise. * |