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| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2015-10-02 13:42:19 +0900 |
|---|---|---|
| committer | Olof Johansson <olof@lixom.net> | 2015-10-27 09:20:50 +0900 |
| commit | e7ecbc057bc5cffb8ad10b6bf7a80684fd426d23 (patch) | |
| tree | d3d5e1647981c5690d4a66270ab246a60ebe7e01 /arch/arm/mm/Kconfig | |
| parent | 156746b1733057e50b3b3cb33c3669dac06676ab (diff) | |
ARM: uniphier: add outer cache support
This commit adds support for UniPhier outer cache controller.
All the UniPhier SoCs are equipped with the L2 cache, while the L3
cache is currently only integrated on PH1-Pro5 SoC.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/mm/Kconfig')
| -rw-r--r-- | arch/arm/mm/Kconfig | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index df7537f12469..a2e74b26d9db 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -986,6 +986,16 @@ config CACHE_TAUROS2 This option enables the Tauros2 L2 cache controller (as found on PJ1/PJ4). +config CACHE_UNIPHIER + bool "Enable the UniPhier outer cache controller" + depends on ARCH_UNIPHIER + default y + select OUTER_CACHE + select OUTER_CACHE_SYNC + help + This option enables the UniPhier outer cache (system cache) + controller. + config CACHE_XSC3L2 bool "Enable the L2 cache on XScale3" depends on CPU_XSC3 |