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| author | Julia Lawall <Julia.Lawall@inria.fr> | 2022-03-18 11:37:08 +0100 |
|---|---|---|
| committer | Florian Fainelli <f.fainelli@gmail.com> | 2022-04-04 10:18:54 -0700 |
| commit | 05e3a8cb079b965e4a0759551770bc507dcfa90f (patch) | |
| tree | da4dec1ce093cec6179f4f17f9214c0c6696f911 /arch/arm/mm/cache-b15-rac.c | |
| parent | 3123109284176b1532874591f7c81f3837bbdc17 (diff) | |
ARM: mm: fix typos in comments
Various spelling mistakes in comments.
Detected with the help of Coccinelle.
Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Diffstat (limited to 'arch/arm/mm/cache-b15-rac.c')
| -rw-r--r-- | arch/arm/mm/cache-b15-rac.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mm/cache-b15-rac.c b/arch/arm/mm/cache-b15-rac.c index bdc07030997b..9c1172f26885 100644 --- a/arch/arm/mm/cache-b15-rac.c +++ b/arch/arm/mm/cache-b15-rac.c @@ -74,7 +74,7 @@ static inline void __b15_rac_flush(void) __raw_writel(FLUSH_RAC, b15_rac_base + rac_flush_offset); do { /* This dmb() is required to force the Bus Interface Unit - * to clean oustanding writes, and forces an idle cycle + * to clean outstanding writes, and forces an idle cycle * to be inserted. */ dmb(); |