diff options
| author | Tejun Heo <tj@kernel.org> | 2010-01-05 09:17:33 +0900 |
|---|---|---|
| committer | Tejun Heo <tj@kernel.org> | 2010-01-05 09:17:33 +0900 |
| commit | 32032df6c2f6c9c6b2ada2ce42322231824f70c2 (patch) | |
| tree | b1ce838a37044bb38dfc128e2116ca35630e629a /arch/arm/mm/cache-v4wt.S | |
| parent | 22b737f4c75197372d64afc6ed1bccd58c00e549 (diff) | |
| parent | c5974b835a909ff15c3b7e6cf6789b5eb919f419 (diff) | |
Merge branch 'master' into percpu
Conflicts:
arch/powerpc/platforms/pseries/hvCall.S
include/linux/percpu.h
Diffstat (limited to 'arch/arm/mm/cache-v4wt.S')
| -rw-r--r-- | arch/arm/mm/cache-v4wt.S | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/arch/arm/mm/cache-v4wt.S b/arch/arm/mm/cache-v4wt.S index c54fa2cc40e6..b3b7410270b4 100644 --- a/arch/arm/mm/cache-v4wt.S +++ b/arch/arm/mm/cache-v4wt.S @@ -117,17 +117,18 @@ ENTRY(v4wt_coherent_user_range) mov pc, lr /* - * flush_kern_dcache_page(void *page) + * flush_kern_dcache_area(void *addr, size_t size) * * Ensure no D cache aliasing occurs, either with itself or * the I cache * - * - addr - page aligned address + * - addr - kernel address + * - size - region size */ -ENTRY(v4wt_flush_kern_dcache_page) +ENTRY(v4wt_flush_kern_dcache_area) mov r2, #0 mcr p15, 0, r2, c7, c5, 0 @ invalidate I cache - add r1, r0, #PAGE_SZ + add r1, r0, r1 /* fallthrough */ /* @@ -180,7 +181,7 @@ ENTRY(v4wt_cache_fns) .long v4wt_flush_user_cache_range .long v4wt_coherent_kern_range .long v4wt_coherent_user_range - .long v4wt_flush_kern_dcache_page + .long v4wt_flush_kern_dcache_area .long v4wt_dma_inv_range .long v4wt_dma_clean_range .long v4wt_dma_flush_range |