diff options
| author | afzal mohammed <afzal.mohd.ma@gmail.com> | 2017-03-23 13:49:32 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@armlinux.org.uk> | 2017-03-29 17:38:41 +0100 |
| commit | 3cc070c1c81948b33ebe2ea68cd39307ce2b312d (patch) | |
| tree | 06ffca2e2a9bc7fa144ae9e6445564064d648f58 /arch/arm/mm/nommu.c | |
| parent | 916a008b4b8ecc02fbd035cfb133773dba1ff3d7 (diff) | |
ARM: 8665/1: nommu: access ID_PFR1 only if CPUID scheme
Greg upon trying to boot no-MMU Kernel on ARM926EJ reported boot
failure. He root caused it to ID_PFR1 access introduced by the
commit mentioned in the fixes tag below.
All CP15 processors need not have processor feature registers, only
for architectures defined by CPUID scheme would have it. Hence check
for it before accessing processor feature register, ID_PFR1.
Fixes: f8300a0b5de0 ("ARM: 8647/2: nommu: dynamic exception base address setting")
Reported-by: Greg Ungerer <gerg@uclinux.org>
Signed-off-by: afzal mohammed <afzal.mohd.ma@gmail.com>
Tested-by: Greg Ungerer <gerg@uclinux.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'arch/arm/mm/nommu.c')
| -rw-r--r-- | arch/arm/mm/nommu.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c index 3b5c7aaf9c76..33a45bd96860 100644 --- a/arch/arm/mm/nommu.c +++ b/arch/arm/mm/nommu.c @@ -303,7 +303,10 @@ static inline void set_vbar(unsigned long val) */ static inline bool security_extensions_enabled(void) { - return !!cpuid_feature_extract(CPUID_EXT_PFR1, 4); + /* Check CPUID Identification Scheme before ID_PFR1 read */ + if ((read_cpuid_id() & 0x000f0000) == 0x000f0000) + return !!cpuid_feature_extract(CPUID_EXT_PFR1, 4); + return 0; } static unsigned long __init setup_vectors_base(void) |