diff options
| author | Vladimir Murzin <vladimir.murzin@arm.com> | 2017-10-16 12:57:48 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@armlinux.org.uk> | 2017-10-23 16:59:15 +0100 |
| commit | 9fcb01a9f54c28062a73a545c29137a4cc104c72 (patch) | |
| tree | 7cebf0b0de05a73132ef66ae9c1671206a58be77 /arch/arm/mm | |
| parent | 89a6dafe136952b3409d5e4ed04cb891e806e924 (diff) | |
ARM: 8711/1: V7M: Add support for MPU to M-class
This patch makes it possible to use MPU with v7M cores.
Tested-by: Szemző András <sza@esh.hu>
Tested-by: Alexandre TORGUE <alexandre.torgue@st.com>
Tested-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'arch/arm/mm')
| -rw-r--r-- | arch/arm/mm/pmsa-v7.c | 53 |
1 files changed, 51 insertions, 2 deletions
diff --git a/arch/arm/mm/pmsa-v7.c b/arch/arm/mm/pmsa-v7.c index cd798271a78d..06e2a853cab9 100644 --- a/arch/arm/mm/pmsa-v7.c +++ b/arch/arm/mm/pmsa-v7.c @@ -15,6 +15,8 @@ static unsigned int __initdata mpu_min_region_order; static unsigned int __initdata mpu_max_regions; +#ifndef CONFIG_CPU_V7M + #define DRBAR __ACCESS_CP15(c6, 0, c1, 0) #define IRBAR __ACCESS_CP15(c6, 0, c1, 1) #define DRSR __ACCESS_CP15(c6, 0, c1, 2) @@ -78,6 +80,51 @@ static inline u32 irbar_read(void) return read_sysreg(IRBAR); } +#else + +static inline void rgnr_write(u32 v) +{ + writel_relaxed(v, BASEADDR_V7M_SCB + MPU_RNR); +} + +/* Data-side / unified region attributes */ + +/* Region access control register */ +static inline void dracr_write(u32 v) +{ + u32 rsr = readl_relaxed(BASEADDR_V7M_SCB + MPU_RASR) & GENMASK(15, 0); + + writel_relaxed((v << 16) | rsr, BASEADDR_V7M_SCB + MPU_RASR); +} + +/* Region size register */ +static inline void drsr_write(u32 v) +{ + u32 racr = readl_relaxed(BASEADDR_V7M_SCB + MPU_RASR) & GENMASK(31, 16); + + writel_relaxed(v | racr, BASEADDR_V7M_SCB + MPU_RASR); +} + +/* Region base address register */ +static inline void drbar_write(u32 v) +{ + writel_relaxed(v, BASEADDR_V7M_SCB + MPU_RBAR); +} + +static inline u32 drbar_read(void) +{ + return readl_relaxed(BASEADDR_V7M_SCB + MPU_RBAR); +} + +/* ARMv7-M only supports a unified MPU, so I-side operations are nop */ + +static inline void iracr_write(u32 v) {} +static inline void irsr_write(u32 v) {} +static inline void irbar_write(u32 v) {} +static inline unsigned long irbar_read(void) {return 0;} + +#endif + static int __init mpu_present(void) { return ((read_cpuid_ext(CPUID_EXT_MMFR0) & MMFR0_PMSA) == MMFR0_PMSAv7); @@ -166,7 +213,7 @@ static int __init __mpu_max_regions(void) */ u32 dregions, iregions, mpuir; - mpuir = read_cpuid(CPUID_MPUIR); + mpuir = read_cpuid_mputype(); dregions = iregions = (mpuir & MPUIR_DREGION_SZMASK) >> MPUIR_DREGION; @@ -181,7 +228,7 @@ static int __init __mpu_max_regions(void) static int __init mpu_iside_independent(void) { /* MPUIR.nU specifies whether there is *not* a unified memory map */ - return read_cpuid(CPUID_MPUIR) & MPUIR_nU; + return read_cpuid_mputype() & MPUIR_nU; } static int __init __mpu_min_region_order(void) @@ -284,9 +331,11 @@ void __init mpu_setup(void) MPU_AP_PL1RW_PL0RW | MPU_RGN_NORMAL); /* Vectors */ +#ifndef CONFIG_CPU_V7M err |= mpu_setup_region(region++, vectors_base, ilog2(2 * PAGE_SIZE), MPU_AP_PL1RW_PL0NA | MPU_RGN_NORMAL); +#endif if (err) { panic("MPU region initialization failure! %d", err); } else { |