diff options
| author | Ard Biesheuvel <ardb@kernel.org> | 2023-03-21 12:01:51 +0100 |
|---|---|---|
| committer | Russell King (Oracle) <rmk+kernel@armlinux.org.uk> | 2023-04-11 11:07:10 +0100 |
| commit | 3a2bdad0b46649cc73fb3b3f9e2b91ef97a7fa63 (patch) | |
| tree | 317ce18fd4ae43d09d2b28c49b423def4563de2b /arch/arm/vfp | |
| parent | dae904d96ad6a5fa79bd9d99a3decf93685d398b (diff) | |
ARM: 9293/1: vfp: Pass successful return address via register R3
In preparation for reimplementing the do_vfp()->vfp_support_entry()
handover in C code, switch to using R3 to pass the 'success' return
address, rather than R9, as it cannot be used for parameter passing.
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Tested-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'arch/arm/vfp')
| -rw-r--r-- | arch/arm/vfp/entry.S | 1 | ||||
| -rw-r--r-- | arch/arm/vfp/vfphw.S | 14 |
2 files changed, 8 insertions, 7 deletions
diff --git a/arch/arm/vfp/entry.S b/arch/arm/vfp/entry.S index cfedc2a3dbd6..6dabb4761778 100644 --- a/arch/arm/vfp/entry.S +++ b/arch/arm/vfp/entry.S @@ -23,6 +23,7 @@ @ ENTRY(do_vfp) mov r1, r10 + mov r3, r9 ldr r4, .LCvfp ldr pc, [r4] @ call VFP entry point ENDPROC(do_vfp) diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S index 6d056d810e48..60acd42e0578 100644 --- a/arch/arm/vfp/vfphw.S +++ b/arch/arm/vfp/vfphw.S @@ -7,7 +7,7 @@ * * This code is called from the kernel's undefined instruction trap. * r1 holds the thread_info pointer - * r9 holds the return address for successful handling. + * r3 holds the return address for successful handling. * lr holds the return address for unrecognised instructions. * sp points to a struct pt_regs (as defined in include/asm/proc/ptrace.h) */ @@ -71,7 +71,7 @@ @ r0 = instruction opcode (32-bit ARM or two 16-bit Thumb) @ r1 = thread_info pointer @ r2 = PC value to resume execution after successful emulation -@ r9 = normal "successful" return address +@ r3 = normal "successful" return address @ lr = unrecognised instruction return address @ IRQs enabled. ENTRY(vfp_support_entry) @@ -89,9 +89,9 @@ ENTRY(vfp_support_entry) bne look_for_VFP_exceptions @ VFP is already enabled DBGSTR1 "enable %x", r10 - ldr r3, vfp_current_hw_state_address + ldr r9, vfp_current_hw_state_address orr r1, r1, #FPEXC_EN @ user FPEXC has the enable bit set - ldr r4, [r3, r11, lsl #2] @ vfp_current_hw_state pointer + ldr r4, [r9, r11, lsl #2] @ vfp_current_hw_state pointer bic r5, r1, #FPEXC_EX @ make sure exceptions are disabled cmp r4, r10 @ this thread owns the hw context? #ifndef CONFIG_SMP @@ -150,7 +150,7 @@ vfp_reload_hw: #endif DBGSTR1 "load state %p", r10 - str r10, [r3, r11, lsl #2] @ update the vfp_current_hw_state pointer + str r10, [r9, r11, lsl #2] @ update the vfp_current_hw_state pointer @ Load the saved state back into the VFP VFPFLDMIA r10, r5 @ reload the working registers while @ FPEXC is in a safe state @@ -180,7 +180,7 @@ vfp_hw_state_valid: @ always subtract 4 from the following @ instruction address. local_bh_enable_ti r10, r4 - ret r9 @ we think we have handled things + ret r3 @ we think we have handled things look_for_VFP_exceptions: @@ -210,7 +210,7 @@ skip: process_exception: DBGSTR "bounce" mov r2, sp @ nothing stacked - regdump is at TOS - mov lr, r9 @ setup for a return to the user code. + mov lr, r3 @ setup for a return to the user code. @ Now call the C code to package up the bounce to the support code @ r0 holds the trigger instruction |