summaryrefslogtreecommitdiff
path: root/arch/arm64/boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi
diff options
context:
space:
mode:
authorClément Péron <peron.clem@gmail.com>2022-09-06 17:30:32 +0200
committerJernej Skrabec <jernej.skrabec@gmail.com>2022-09-08 22:04:48 +0200
commit116745dd557b85e32adc9e1aa8b7d5c5079aba1b (patch)
treebca4d54ca1869f9abd955f0a33e2a31ef8767e18 /arch/arm64/boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi
parenta067916d20bd52bd7c13af02bda1eb4f93e68539 (diff)
arm64: dts: allwinner: h6: Add GPU OPP table
Add an Operating Performance Points table for the GPU to enable Dynamic Voltage & Frequency Scaling on the H6. The voltage range is set with minimal voltage set to the target and the maximal voltage set to 1.2V. This allow DVFS framework to work properly on board with fixed regulator. Signed-off-by: Clément Péron <peron.clem@gmail.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Link: https://lore.kernel.org/r/20220906153034.153321-4-peron.clem@gmail.com
Diffstat (limited to 'arch/arm64/boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi')
-rw-r--r--arch/arm64/boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi87
1 files changed, 87 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi
new file mode 100644
index 000000000000..b48049c4fc85
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-gpu-opp.dtsi
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (C) 2022 Clément Péron <peron.clem@gmail.com>
+
+/ {
+ gpu_opp_table: opp-table-gpu {
+ compatible = "operating-points-v2";
+
+ opp-216000000 {
+ opp-hz = /bits/ 64 <216000000>;
+ opp-microvolt = <810000 810000 1200000>;
+ };
+
+ opp-264000000 {
+ opp-hz = /bits/ 64 <264000000>;
+ opp-microvolt = <810000 810000 1200000>;
+ };
+
+ opp-312000000 {
+ opp-hz = /bits/ 64 <312000000>;
+ opp-microvolt = <810000 810000 1200000>;
+ };
+
+ opp-336000000 {
+ opp-hz = /bits/ 64 <336000000>;
+ opp-microvolt = <810000 810000 1200000>;
+ };
+
+ opp-360000000 {
+ opp-hz = /bits/ 64 <360000000>;
+ opp-microvolt = <820000 820000 1200000>;
+ };
+
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ opp-microvolt = <830000 830000 1200000>;
+ };
+
+ opp-408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <840000 840000 1200000>;
+ };
+
+ opp-420000000 {
+ opp-hz = /bits/ 64 <420000000>;
+ opp-microvolt = <850000 850000 1200000>;
+ };
+
+ opp-432000000 {
+ opp-hz = /bits/ 64 <432000000>;
+ opp-microvolt = <860000 860000 1200000>;
+ };
+
+ opp-456000000 {
+ opp-hz = /bits/ 64 <456000000>;
+ opp-microvolt = <870000 870000 1200000>;
+ };
+
+ opp-504000000 {
+ opp-hz = /bits/ 64 <504000000>;
+ opp-microvolt = <890000 890000 1200000>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ opp-microvolt = <910000 910000 1200000>;
+ };
+
+ opp-576000000 {
+ opp-hz = /bits/ 64 <576000000>;
+ opp-microvolt = <930000 930000 1200000>;
+ };
+
+ opp-624000000 {
+ opp-hz = /bits/ 64 <624000000>;
+ opp-microvolt = <950000 950000 1200000>;
+ };
+
+ opp-756000000 {
+ opp-hz = /bits/ 64 <756000000>;
+ opp-microvolt = <1040000 1040000 1200000>;
+ };
+ };
+};
+
+&gpu {
+ operating-points-v2 = <&gpu_opp_table>;
+};