diff options
author | Dan Williams <dan.j.williams@intel.com> | 2017-11-15 16:56:11 -0800 |
---|---|---|
committer | Dan Williams <dan.j.williams@intel.com> | 2017-11-15 16:56:11 -0800 |
commit | 4247f24c23589bcc3bc3490515ef8c9497e9ae55 (patch) | |
tree | 89726a0e171c443a3e8def2992b56dbd8a21df21 /arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | |
parent | 79ab67ede21f536851a99ea68ee6fc1f5435e055 (diff) | |
parent | 9f586fff6574f6ecbf323f92d44ffaf0d96225fe (diff) |
Merge branch 'for-4.15/dax' into libnvdimm-for-next
Diffstat (limited to 'arch/arm64/boot/dts/amlogic/meson-gxl.dtsi')
-rw-r--r-- | arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 39 |
1 files changed, 36 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi index d6876e64979e..d8dd3298b15c 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi @@ -281,6 +281,17 @@ }; }; + emmc_clk_gate_pins: emmc_clk_gate { + mux { + groups = "BOOT_8"; + function = "gpio_periphs"; + }; + cfg-pull-down { + pins = "BOOT_8"; + bias-pull-down; + }; + }; + nor_pins: nor { mux { groups = "nor_d", @@ -319,6 +330,17 @@ }; }; + sdcard_clk_gate_pins: sdcard_clk_gate { + mux { + groups = "CARD_2"; + function = "gpio_periphs"; + }; + cfg-pull-down { + pins = "CARD_2"; + bias-pull-down; + }; + }; + sdio_pins: sdio { mux { groups = "sdio_d0", @@ -331,6 +353,17 @@ }; }; + sdio_clk_gate_pins: sdio_clk_gate { + mux { + groups = "GPIOX_4"; + function = "gpio_periphs"; + }; + cfg-pull-down { + pins = "GPIOX_4"; + bias-pull-down; + }; + }; + sdio_irq_pins: sdio_irq { mux { groups = "sdio_irq"; @@ -603,21 +636,21 @@ &sd_emmc_a { clocks = <&clkc CLKID_SD_EMMC_A>, - <&xtal>, + <&clkc CLKID_SD_EMMC_A_CLK0>, <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; }; &sd_emmc_b { clocks = <&clkc CLKID_SD_EMMC_B>, - <&xtal>, + <&clkc CLKID_SD_EMMC_B_CLK0>, <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; }; &sd_emmc_c { clocks = <&clkc CLKID_SD_EMMC_C>, - <&xtal>, + <&clkc CLKID_SD_EMMC_C_CLK0>, <&clkc CLKID_FCLK_DIV2>; clock-names = "core", "clkin0", "clkin1"; }; |