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| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2019-11-30 19:53:37 +0100 |
|---|---|---|
| committer | Kevin Hilman <khilman@baylibre.com> | 2019-12-09 15:21:20 -0800 |
| commit | 4881873f4cc1460f63d85fa81363d56be328ccdc (patch) | |
| tree | 740c08d2bb966dce184e5fc2131bd03785ca1676 /arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts | |
| parent | c67aafd60d7e323fe74bf45fab60148f84cf9b95 (diff) | |
dt-bindings: reset: meson8b: fix duplicate reset IDs
According to the public S805 datasheet the RESET2 register uses the
following bits for the PIC_DC, PSC and NAND reset lines:
- PIC_DC is at bit 3 (meaning: RESET_VD_RMEM + 3)
- PSC is at bit 4 (meaning: RESET_VD_RMEM + 4)
- NAND is at bit 5 (meaning: RESET_VD_RMEM + 4)
Update the reset IDs of these three reset lines so they don't conflict
with PIC_DC and map to the actual hardware reset lines.
Fixes: 79795e20a184eb ("dt-bindings: reset: Add bindings for the Meson SoC Reset Controller")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Diffstat (limited to 'arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts')
0 files changed, 0 insertions, 0 deletions