diff options
| author | Daniel Thompson <daniel.thompson@linaro.org> | 2017-09-19 19:32:04 +0100 |
|---|---|---|
| committer | Sudeep Holla <sudeep.holla@arm.com> | 2017-10-03 15:10:17 +0100 |
| commit | bc3d3447b66a9eb398c7cce96f05b7c78d725abc (patch) | |
| tree | ac39d2efa83f71f509cabd0a7297a0270563f02b /arch/arm64/boot/dts/arm/Makefile | |
| parent | 2bd6bf03f4c1c59381d62c61d03f6cc3fe71f66e (diff) | |
arm64: dts: foundation-v8: Enable PSCI mode
Currently if the Foundation model is running ARM Trusted Firmware then
the kernel, which is configured to use spin tables, cannot start secondary
processors or "power off" the simulation.
After adding a couple of labels to the include file and splitting out the
spin-table configuration into a header, we add a couple of new headers
together with two new DTs (GICv2 + PSCI and GICv3 + PSCI).
The new GICv3+PSCI DT has been boot tested, the remaining three (two of
which existed prior to this patch) have been "tested" by decompiling the
blobs and comparing them against a reference.
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Diffstat (limited to 'arch/arm64/boot/dts/arm/Makefile')
| -rw-r--r-- | arch/arm64/boot/dts/arm/Makefile | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile index 75cc2aa10101..25f82c377f67 100644 --- a/arch/arm64/boot/dts/arm/Makefile +++ b/arch/arm64/boot/dts/arm/Makefile @@ -1,4 +1,6 @@ -dtb-$(CONFIG_ARCH_VEXPRESS) += foundation-v8.dtb foundation-v8-gicv3.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) += \ + foundation-v8.dtb foundation-v8-psci.dtb \ + foundation-v8-gicv3.dtb foundation-v8-gicv3-psci.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb juno-r2.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb |