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authorDaniel Thompson <daniel.thompson@linaro.org>2017-09-19 19:32:04 +0100
committerSudeep Holla <sudeep.holla@arm.com>2017-10-03 15:10:17 +0100
commitbc3d3447b66a9eb398c7cce96f05b7c78d725abc (patch)
treeac39d2efa83f71f509cabd0a7297a0270563f02b /arch/arm64/boot/dts/arm/foundation-v8.dtsi
parent2bd6bf03f4c1c59381d62c61d03f6cc3fe71f66e (diff)
arm64: dts: foundation-v8: Enable PSCI mode
Currently if the Foundation model is running ARM Trusted Firmware then the kernel, which is configured to use spin tables, cannot start secondary processors or "power off" the simulation. After adding a couple of labels to the include file and splitting out the spin-table configuration into a header, we add a couple of new headers together with two new DTs (GICv2 + PSCI and GICv3 + PSCI). The new GICv3+PSCI DT has been boot tested, the remaining three (two of which existed prior to this patch) have been "tested" by decompiling the blobs and comparing them against a reference. Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Diffstat (limited to 'arch/arm64/boot/dts/arm/foundation-v8.dtsi')
-rw-r--r--arch/arm64/boot/dts/arm/foundation-v8.dtsi16
1 files changed, 4 insertions, 12 deletions
diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dtsi b/arch/arm64/boot/dts/arm/foundation-v8.dtsi
index 8ecdd4331980..60f6ab920743 100644
--- a/arch/arm64/boot/dts/arm/foundation-v8.dtsi
+++ b/arch/arm64/boot/dts/arm/foundation-v8.dtsi
@@ -28,36 +28,28 @@
#address-cells = <2>;
#size-cells = <0>;
- cpu@0 {
+ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x0>;
- enable-method = "spin-table";
- cpu-release-addr = <0x0 0x8000fff8>;
next-level-cache = <&L2_0>;
};
- cpu@1 {
+ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x1>;
- enable-method = "spin-table";
- cpu-release-addr = <0x0 0x8000fff8>;
next-level-cache = <&L2_0>;
};
- cpu@2 {
+ cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x2>;
- enable-method = "spin-table";
- cpu-release-addr = <0x0 0x8000fff8>;
next-level-cache = <&L2_0>;
};
- cpu@3 {
+ cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,armv8";
reg = <0x0 0x3>;
- enable-method = "spin-table";
- cpu-release-addr = <0x0 0x8000fff8>;
next-level-cache = <&L2_0>;
};