diff options
| author | Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> | 2024-10-23 12:17:31 +0300 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2024-10-26 14:08:04 +0200 |
| commit | fa986d1073805154888a788eda38d46a796346e8 (patch) | |
| tree | 6c7fa6a9a5c81957512f8336d30bd19cc84f4138 /arch/arm64/boot/dts/exynos/exynos8895.dtsi | |
| parent | e54eb0465e548a7c6115e336ec5cfec04bbe8747 (diff) | |
arm64: dts: exynos8895: Add clock management unit nodes
Add clock management unit nodes for:
- cmu_top, which provides muxes, divs and gates for other CMUs
- cmu_peris, which provides clocks for GIC and MCT
- cmu_fsys0, which provides clocks for USBDRD30
- cmu_fsys1, which provides clocks for MMC, UFS and PCIE
- cmu_peric0, which provides clocks for UART_DBG, USI00 ~ USI03
- cmu_peric1, which provides clocks for SPI_CAM0/1, UART_BT,
USI04 ~ USI13
Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
Link: https://lore.kernel.org/r/20241023091734.538682-3-ivo.ivanov.ivanov1@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'arch/arm64/boot/dts/exynos/exynos8895.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/exynos/exynos8895.dtsi | 85 |
1 files changed, 85 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/exynos/exynos8895.dtsi b/arch/arm64/boot/dts/exynos/exynos8895.dtsi index 223ebd482f10..54037b0dc630 100644 --- a/arch/arm64/boot/dts/exynos/exynos8895.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos8895.dtsi @@ -5,6 +5,7 @@ * Copyright (c) 2024, Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> */ +#include <dt-bindings/clock/samsung,exynos8895.h> #include <dt-bindings/interrupt-controller/arm-gic.h> / { @@ -159,6 +160,15 @@ reg = <0x10000000 0x24>; }; + cmu_peris: clock-controller@10010000 { + compatible = "samsung,exynos8895-cmu-peris"; + reg = <0x10010000 0x8000>; + #clock-cells = <1>; + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_CMU_PERIS_BUS>; + clock-names = "oscclk", "bus"; + }; + gic: interrupt-controller@10201000 { compatible = "arm,gic-400"; reg = <0x10201000 0x1000>, @@ -173,24 +183,91 @@ #size-cells = <1>; }; + cmu_peric0: clock-controller@10400000 { + compatible = "samsung,exynos8895-cmu-peric0"; + reg = <0x10400000 0x8000>; + #clock-cells = <1>; + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_CMU_PERIC0_BUS>, + <&cmu_top CLK_DOUT_CMU_PERIC0_UART_DBG>, + <&cmu_top CLK_DOUT_CMU_PERIC0_USI00>, + <&cmu_top CLK_DOUT_CMU_PERIC0_USI01>, + <&cmu_top CLK_DOUT_CMU_PERIC0_USI02>, + <&cmu_top CLK_DOUT_CMU_PERIC0_USI03>; + clock-names = "oscclk", "bus", "uart", "usi0", + "usi1", "usi2", "usi3"; + }; + pinctrl_peric0: pinctrl@104d0000 { compatible = "samsung,exynos8895-pinctrl"; reg = <0x104d0000 0x1000>; interrupts = <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>; }; + cmu_peric1: clock-controller@10800000 { + compatible = "samsung,exynos8895-cmu-peric1"; + reg = <0x10800000 0x8000>; + #clock-cells = <1>; + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_CMU_PERIC1_BUS>, + <&cmu_top CLK_DOUT_CMU_PERIC1_SPEEDY2>, + <&cmu_top CLK_DOUT_CMU_PERIC1_SPI_CAM0>, + <&cmu_top CLK_DOUT_CMU_PERIC1_SPI_CAM1>, + <&cmu_top CLK_DOUT_CMU_PERIC1_UART_BT>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI04>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI05>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI06>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI07>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI08>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI09>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI10>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI11>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI12>, + <&cmu_top CLK_DOUT_CMU_PERIC1_USI13>; + clock-names = "oscclk", "bus", "speedy", "cam0", + "cam1", "uart", "usi4", "usi5", + "usi6", "usi7", "usi8", "usi9", + "usi10", "usi11", "usi12", "usi13"; + }; + pinctrl_peric1: pinctrl@10980000 { compatible = "samsung,exynos8895-pinctrl"; reg = <0x10980000 0x1000>; interrupts = <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; }; + cmu_fsys0: clock-controller@11000000 { + compatible = "samsung,exynos8895-cmu-fsys0"; + reg = <0x11000000 0x8000>; + #clock-cells = <1>; + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_CMU_FSYS0_BUS>, + <&cmu_top CLK_DOUT_CMU_FSYS0_DPGTC>, + <&cmu_top CLK_DOUT_CMU_FSYS0_MMC_EMBD>, + <&cmu_top CLK_DOUT_CMU_FSYS0_UFS_EMBD>, + <&cmu_top CLK_DOUT_CMU_FSYS0_USBDRD30>; + clock-names = "oscclk", "bus", "dpgtc", "mmc", + "ufs", "usbdrd30"; + }; + pinctrl_fsys0: pinctrl@11050000 { compatible = "samsung,exynos8895-pinctrl"; reg = <0x11050000 0x1000>; interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; }; + cmu_fsys1: clock-controller@11400000 { + compatible = "samsung,exynos8895-cmu-fsys1"; + reg = <0x11400000 0x8000>; + #clock-cells = <1>; + clocks = <&oscclk>, + <&cmu_top CLK_DOUT_CMU_FSYS1_BUS>, + <&cmu_top CLK_DOUT_CMU_FSYS1_PCIE>, + <&cmu_top CLK_DOUT_CMU_FSYS1_UFS_CARD>, + <&cmu_top CLK_DOUT_CMU_FSYS1_MMC_CARD>; + clock-names = "oscclk", "bus", "pcie", "ufs", "mmc"; + }; + pinctrl_fsys1: pinctrl@11430000 { compatible = "samsung,exynos8895-pinctrl"; reg = <0x11430000 0x1000>; @@ -213,6 +290,14 @@ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; }; + cmu_top: clock-controller@15a80000 { + compatible = "samsung,exynos8895-cmu-top"; + reg = <0x15a80000 0x8000>; + #clock-cells = <1>; + clocks = <&oscclk>; + clock-names = "oscclk"; + }; + pmu_system_controller: system-controller@16480000 { compatible = "samsung,exynos8895-pmu", "samsung,exynos7-pmu", "syscon"; |