diff options
| author | Chuanhua Han <chuanhua.han@nxp.com> | 2019-08-06 16:42:21 +0800 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2019-08-19 16:04:49 +0200 |
| commit | 52d3406ec72d20f847f108d70b17b2ab844956f6 (patch) | |
| tree | a33cd2dd575172b934eff013734d9a652ab05c70 /arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | |
| parent | 86c457e3991a89e866792f05bc5ae43f476d80d2 (diff) | |
arm64: dts: ls1012a: Fix incorrect I2C clock divider
Ls1012a platform, the i2c input clock is actually platform pll CLK / 4
(this is the hardware connection), other clock divider can not get the
correct i2c clock, resulting in the output of SCL pin clock is not
accurate.
Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com>
Acked-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index ec6257a5b251..124a7e2d8442 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -323,7 +323,7 @@ #size-cells = <0>; reg = <0x0 0x2180000 0x0 0x10000>; interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 0>; + clocks = <&clockgen 4 3>; status = "disabled"; }; @@ -333,7 +333,7 @@ #size-cells = <0>; reg = <0x0 0x2190000 0x0 0x10000>; interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clockgen 4 0>; + clocks = <&clockgen 4 3>; status = "disabled"; }; |