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authorWen He <wen.he_1@nxp.com>2019-05-10 10:49:28 +0800
committerShawn Guo <shawnguo@kernel.org>2019-05-20 09:09:48 +0800
commit7f538f199f71b0ee7bfc4e188b502ac95a57cc3f (patch)
tree12fbf3e3664e3b3fb7296bcca7934641f4754065 /arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
parenta188339ca5a396acc588e5851ed7e19f66b0ebd9 (diff)
arm64: dts: ls1028a: Add properties for Mali DP500 node
The LS1028A has a LCD controller and Displayport interface that connects to eDP and Displayport connectors on the LS1028A board. This patch enables the LCD controller driver on the LS1028A. Signed-off-by: Alison Wang <alison.wang@nxp.com> Signed-off-by: Wen He <wen.he_1@nxp.com> Reviewed-by: Liviu Dudau <liviu.dudau@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi')
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi38
1 files changed, 38 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index b04581249f0b..c0a13f9e5b95 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -70,6 +70,27 @@
clock-output-names = "sysclk";
};
+ dpclk: clock-dp {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <27000000>;
+ clock-output-names= "dpclk";
+ };
+
+ aclk: clock-axi {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <650000000>;
+ clock-output-names= "aclk";
+ };
+
+ pclk: clock-apb {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <650000000>;
+ clock-output-names= "pclk";
+ };
+
reboot {
compatible ="syscon-reboot";
regmap = <&dcfg>;
@@ -433,4 +454,21 @@
};
};
};
+
+ malidp0: display@f080000 {
+ compatible = "arm,mali-dp500";
+ reg = <0x0 0xf080000 0x0 0x10000>;
+ interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
+ <0 223 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "DE", "SE";
+ clocks = <&dpclk>, <&aclk>, <&aclk>, <&pclk>;
+ clock-names = "pxlclk", "mclk", "aclk", "pclk";
+ arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
+
+ port {
+ dp0_out: endpoint {
+
+ };
+ };
+ };
};