diff options
author | Madalin Bucur <madalin.bucur@nxp.com> | 2017-05-16 15:07:22 +0300 |
---|---|---|
committer | Shawn Guo <shawnguo@kernel.org> | 2017-05-21 10:13:47 +0800 |
commit | bf02f2ffe59c991f28519be2a37769d3e7c8f6a9 (patch) | |
tree | 3ff4933054c6a67627265cff1aff75b85f3229fb /arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | |
parent | 1ffbecdd8321a8eb38503b63a9018995b872ed95 (diff) |
arm64: dts: add LS1043A DPAA FMan support
Add the DPAA 1.x FMan device tree nodes for LS1043A boards.
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts')
-rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 73 |
1 files changed, 73 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts index d64370ed0738..df5b180a95a8 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts @@ -139,3 +139,76 @@ &duart1 { status = "okay"; }; + +#include "fsl-ls1043-post.dtsi" + +&fman0 { + ethernet@e0000 { + phy-handle = <&qsgmii_phy1>; + phy-connection-type = "qsgmii"; + }; + + ethernet@e2000 { + phy-handle = <&qsgmii_phy2>; + phy-connection-type = "qsgmii"; + }; + + ethernet@e4000 { + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii-txid"; + }; + + ethernet@e6000 { + phy-handle = <&rgmii_phy2>; + phy-connection-type = "rgmii-txid"; + }; + + ethernet@e8000 { + phy-handle = <&qsgmii_phy3>; + phy-connection-type = "qsgmii"; + }; + + ethernet@ea000 { + phy-handle = <&qsgmii_phy4>; + phy-connection-type = "qsgmii"; + }; + + ethernet@f0000 { /* 10GEC1 */ + phy-handle = <&aqr105_phy>; + phy-connection-type = "xgmii"; + }; + + mdio@fc000 { + rgmii_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + + rgmii_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + + qsgmii_phy1: ethernet-phy@4 { + reg = <0x4>; + }; + + qsgmii_phy2: ethernet-phy@5 { + reg = <0x5>; + }; + + qsgmii_phy3: ethernet-phy@6 { + reg = <0x6>; + }; + + qsgmii_phy4: ethernet-phy@7 { + reg = <0x7>; + }; + }; + + mdio@fd000 { + aqr105_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c45"; + interrupts = <0 132 4>; + reg = <0x1>; + }; + }; +}; |