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authorYork Sun <york.sun@nxp.com>2016-08-09 14:59:39 -0700
committerShawn Guo <shawnguo@kernel.org>2016-08-30 18:52:50 +0800
commit30062fb0b31956709445e6f91d4f723d3808e0fa (patch)
treeeec5e0209302f40033c1c659c425a9d9c590ebc1 /arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
parent29b4817d4018df78086157ea3a55c1d9424a7cfc (diff)
arm64: dts: Add DDR memory controller for Layerscape SoCs
Add DDR memory controller nodes to enable EDAC driver. Signed-off-by: York Sun <york.sun@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi')
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index e669fbd7f9c3..e6765404bb53 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -247,6 +247,13 @@
bus-width = <4>;
};
+ ddr: memory-controller@1080000 {
+ compatible = "fsl,qoriq-memory-controller";
+ reg = <0x0 0x1080000 0x0 0x1000>;
+ interrupts = <0 144 0x4>;
+ big-endian;
+ };
+
dspi0: dspi@2100000 {
compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;