diff options
author | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2023-04-22 00:32:06 +0200 |
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committer | Shawn Guo <shawnguo@kernel.org> | 2023-05-14 11:52:39 +0800 |
commit | c290d09a998c810d11cca972810849fe7c2ec711 (patch) | |
tree | 387e3f21f4260e6b099f4f068eb745fa518d634e /arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | |
parent | d2bd947176f855ea5a07fa9cce7bf15b0ce0467f (diff) |
arm64: dts: freescale: add missing cache properties
As all level 2 and level 3 caches are unified, add required
cache-unified properties to fix warnings like:
fsl-ls2080a-simu.dtb: l2-cache3: 'cache-unified' is a required property
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi')
-rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi index 1e5d76c4d83d..1aa38ed09aa4 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi @@ -96,21 +96,25 @@ cluster0_l2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster1_l2: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster2_l2: l2-cache2 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster3_l2: l2-cache3 { compatible = "cache"; cache-level = <2>; + cache-unified; }; CPU_PW20: cpu-pw20 { |