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authorFrank Li <Frank.Li@nxp.com>2022-09-30 13:34:25 -0500
committerShawn Guo <shawnguo@kernel.org>2022-10-24 10:14:04 +0800
commit8065fc937f0f147f0a6efdf14f3cbcb821ea18db (patch)
tree7562ca6e9b34d79bc92c35617873f941cbb7de18 /arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
parent375347575fb369255471e1142bd62621b85d1876 (diff)
arm64: dts: imx8dxl: add usb1 and usb2 support
There are two chipidea usb controller in 8dxl. Add usb node at common connect subsystem. Enable two usb at imx8dxl_evk boards dts. Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi')
-rw-r--r--arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi39
1 files changed, 39 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
index 82a1c4488378..bf72732e311a 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
@@ -34,6 +34,35 @@ conn_subsys: bus@5b000000 {
clock-output-names = "conn_ipg_clk";
};
+ usbotg1: usb@5b0d0000 {
+ compatible = "fsl,imx7ulp-usb";
+ reg = <0x5b0d0000 0x200>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,usbphy = <&usbphy1>;
+ fsl,usbmisc = <&usbmisc1 0>;
+ clocks = <&usb2_lpcg 0>;
+ ahb-burst-config = <0x0>;
+ tx-burst-size-dword = <0x10>;
+ rx-burst-size-dword = <0x10>;
+ power-domains = <&pd IMX_SC_R_USB_0>;
+ status = "disabled";
+ };
+
+ usbmisc1: usbmisc@5b0d0200 {
+ #index-cells = <1>;
+ compatible = "fsl,imx7ulp-usbmisc", "fsl,imx6q-usbmisc";
+ reg = <0x5b0d0200 0x200>;
+ };
+
+ usbphy1: usbphy@5b100000 {
+ compatible = "fsl,imx7ulp-usbphy";
+ reg = <0x5b100000 0x1000>;
+ clocks = <&usb2_lpcg 1>;
+ power-domains = <&pd IMX_SC_R_USB_0_PHY>;
+ status = "disabled";
+ };
+
usdhc1: mmc@5b010000 {
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x5b010000 0x10000>;
@@ -195,4 +224,14 @@ conn_subsys: bus@5b000000 {
"enet1_lpcg_ipg_s_clk";
power-domains = <&pd IMX_SC_R_ENET_1>;
};
+
+ usb2_lpcg: clock-controller@5b270000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5b270000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&conn_ahb_clk>, <&conn_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_6>, <IMX_LPCG_CLK_7>;
+ clock-output-names = "usboh3_ahb_clk", "usboh3_phy_ipg_clk";
+ power-domains = <&pd IMX_SC_R_USB_0_PHY>;
+ };
};