diff options
| author | Krzysztof Kozlowski <krzk@kernel.org> | 2020-09-17 20:54:47 +0200 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2020-09-22 17:06:04 +0800 |
| commit | 5f67317bd967bbdde945ce3a586d3841f8a5bf65 (patch) | |
| tree | 3b4b75c31285933c50e85985c7b2215b0877a3ab /arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi | |
| parent | 1d93b292af67e1848a87991c59be6929187cba23 (diff) | |
arm64: dts: imx8mm: correct interrupt flags
GPIO_ACTIVE_x flags are not correct in the context of interrupt flags.
These are simple defines so they could be used in DTS but they will not
have the same meaning:
1. GPIO_ACTIVE_HIGH = 0 = IRQ_TYPE_NONE
2. GPIO_ACTIVE_LOW = 1 = IRQ_TYPE_EDGE_RISING
Correct the interrupt flags, assuming the author of the code wanted same
logical behavior behind the name "ACTIVE_xxx", this is:
ACTIVE_LOW => IRQ_TYPE_LEVEL_LOW
ACTIVE_HIGH => IRQ_TYPE_LEVEL_HIGH
In case of level low interrupts, enable also internal pull up. It is
required at least on imx8mm-evk, according to schematics.
The schematics for Variscite imx8mm-var-som are not available and
I was unable to get proper configuration from Variscite.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-By: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi index 502faf6144b0..6de86a4f0ec4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi @@ -74,7 +74,7 @@ reg = <0x4b>; pinctrl-0 = <&pinctrl_pmic>; interrupt-parent = <&gpio1>; - interrupts = <3 GPIO_ACTIVE_LOW>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; rohm,reset-snvs-powered; regulators { @@ -292,7 +292,7 @@ pinctrl_pmic: pmicirqgrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 >; }; |