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authorKrzysztof Kozlowski <krzk@kernel.org>2020-08-28 18:47:40 +0200
committerShawn Guo <shawnguo@kernel.org>2020-09-05 14:29:15 +0800
commitfc54664e0bbfea639e720e838b48298fbaf59af4 (patch)
tree37a08c4441b9e1a3bc42cabb5eb328a187e4bd8b /arch/arm64/boot/dts/freescale/imx8mm-evk.dts
parenta6a355ede5747b668da056fbacdb75ac1ea71fc4 (diff)
arm64: dts: imx8mm-evk: Align pin configuration group names with schema
Device tree schema expects pin configuration groups to end with 'grp' suffix, otherwise dtbs_check complain with a warning like: ... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mm-evk.dts')
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm-evk.dts4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
index de53f1c2bf72..4e2820d19244 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
@@ -94,7 +94,7 @@
>;
};
- pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
@@ -110,7 +110,7 @@
>;
};
- pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6