diff options
| author | Adrien Grassein <adrien.grassein@gmail.com> | 2021-02-23 20:16:49 +0100 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2021-03-15 12:22:30 +0800 |
| commit | b399c13f0b4af8dbec756bccc52afa7d2a69a3e6 (patch) | |
| tree | d3fdcabd04c81e3e7ac7fded233e4a21a23274a7 /arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts | |
| parent | 2b6e7da251e3ae412d2ef6877a0e4c8f060225f0 (diff) | |
arm64: dts: imx8mm-nitrogen-r2: add PWMs
Add description for the four PWMs.
Signed-off-by: Adrien Grassein <adrien.grassein@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts b/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts index 6056dfe2c714..39fb52960b84 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts @@ -198,6 +198,33 @@ }; }; +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm2 { + assigned-clocks = <&clk IMX8MM_CLK_PWM2>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_40M>; + assigned-clock-rates = <40000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + /* BT */ &uart1 { pinctrl-names = "default"; @@ -354,6 +381,30 @@ >; }; + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x16 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x16 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x16 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_MCLK_PWM4_OUT 0x16 + >; + }; + pinctrl_reg_wlan_vmmc: reg-wlan-vmmcgrp { fsl,pins = < MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x16 |