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authorTim Harvey <tharvey@gateworks.com>2021-12-16 08:41:49 -0800
committerShawn Guo <shawnguo@kernel.org>2022-02-11 11:16:17 +0800
commitafb424b99e0f556bf1324c73570028cb56d5cadb (patch)
treeb0eda1fdcaf0b51fb3822dac0356edb8009c1ec3 /arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
parent9a0f3b157e22eb4a5f5bddd3ba820b2bee5407b0 (diff)
arm64: dts: imx8mm-venice*: add PCIe support
Add PCIe support to GW71xx/GW72xx/GW73xx/GW7901/GW7902 Signed-off-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts')
-rw-r--r--arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts36
1 files changed, 36 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
index 21c546c4628d..ca754dff918d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
@@ -8,6 +8,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/leds/common.h>
+#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mm.dtsi"
@@ -179,6 +180,12 @@
};
};
+ pcie0_refclk: pcie0-refclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
@@ -644,6 +651,28 @@
status = "okay";
};
+&pcie_phy {
+ fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
+ fsl,clkreq-unsupported;
+ clocks = <&pcie0_refclk>;
+ status = "okay";
+};
+
+&pcie0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie0>;
+ reset-gpio = <&gpio5 2 GPIO_ACTIVE_LOW>;
+ clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
+ <&pcie0_refclk>;
+ clock-names = "pcie", "pcie_aux", "pcie_bus";
+ assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
+ <&clk IMX8MM_CLK_PCIE1_CTRL>;
+ assigned-clock-rates = <10000000>, <250000000>;
+ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
+ <&clk IMX8MM_SYS_PLL2_250M>;
+ status = "okay";
+};
+
&pgc_gpu {
status = "disabled";
};
@@ -820,6 +849,13 @@
>;
};
+ pinctrl_pcie0: pciegrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x40000041 /* WDIS# */
+ MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x41
+ >;
+ };
+
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41